1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11/ { 12 compatible = "nvidia,tegra132", "nvidia,tegra124"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra124-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 43 <&tegra_car TEGRA124_CLK_AFI>, 44 <&tegra_car TEGRA124_CLK_PLL_E>, 45 <&tegra_car TEGRA124_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 54 phy-names = "pcie"; 55 56 pci@1,0 { 57 device_type = "pci"; 58 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 59 reg = <0x000800 0 0 0 0>; 60 bus-range = <0x00 0xff>; 61 status = "disabled"; 62 63 #address-cells = <3>; 64 #size-cells = <2>; 65 ranges; 66 67 nvidia,num-lanes = <2>; 68 }; 69 70 pci@2,0 { 71 device_type = "pci"; 72 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 73 reg = <0x001000 0 0 0 0>; 74 bus-range = <0x00 0xff>; 75 status = "disabled"; 76 77 #address-cells = <3>; 78 #size-cells = <2>; 79 ranges; 80 81 nvidia,num-lanes = <1>; 82 }; 83 }; 84 85 host1x@50000000 { 86 compatible = "nvidia,tegra132-host1x", 87 "nvidia,tegra124-host1x", 88 "simple-bus"; 89 reg = <0x0 0x50000000 0x0 0x00034000>; 90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 91 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 92 interrupt-names = "syncpt", "host1x"; 93 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 94 clock-names = "host1x"; 95 resets = <&tegra_car 28>; 96 reset-names = "host1x"; 97 98 #address-cells = <2>; 99 #size-cells = <2>; 100 101 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 102 103 dc@54200000 { 104 compatible = "nvidia,tegra124-dc"; 105 reg = <0x0 0x54200000 0x0 0x00040000>; 106 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 108 clock-names = "dc"; 109 resets = <&tegra_car 27>; 110 reset-names = "dc"; 111 112 iommus = <&mc TEGRA_SWGROUP_DC>; 113 114 nvidia,head = <0>; 115 }; 116 117 dc@54240000 { 118 compatible = "nvidia,tegra124-dc"; 119 reg = <0x0 0x54240000 0x0 0x00040000>; 120 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 122 clock-names = "dc"; 123 resets = <&tegra_car 26>; 124 reset-names = "dc"; 125 126 iommus = <&mc TEGRA_SWGROUP_DCB>; 127 128 nvidia,head = <1>; 129 }; 130 131 hdmi@54280000 { 132 compatible = "nvidia,tegra124-hdmi"; 133 reg = <0x0 0x54280000 0x0 0x00040000>; 134 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 136 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 137 clock-names = "hdmi", "parent"; 138 resets = <&tegra_car 51>; 139 reset-names = "hdmi"; 140 status = "disabled"; 141 }; 142 143 sor@54540000 { 144 compatible = "nvidia,tegra124-sor"; 145 reg = <0x0 0x54540000 0x0 0x00040000>; 146 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 148 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 149 <&tegra_car TEGRA124_CLK_PLL_DP>, 150 <&tegra_car TEGRA124_CLK_CLK_M>; 151 clock-names = "sor", "parent", "dp", "safe"; 152 resets = <&tegra_car 182>; 153 reset-names = "sor"; 154 status = "disabled"; 155 }; 156 157 dpaux: dpaux@545c0000 { 158 compatible = "nvidia,tegra124-dpaux"; 159 reg = <0x0 0x545c0000 0x0 0x00040000>; 160 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 162 <&tegra_car TEGRA124_CLK_PLL_DP>; 163 clock-names = "dpaux", "parent"; 164 resets = <&tegra_car 181>; 165 reset-names = "dpaux"; 166 status = "disabled"; 167 }; 168 }; 169 170 gic: interrupt-controller@50041000 { 171 compatible = "arm,cortex-a15-gic"; 172 #interrupt-cells = <3>; 173 interrupt-controller; 174 reg = <0x0 0x50041000 0x0 0x1000>, 175 <0x0 0x50042000 0x0 0x2000>, 176 <0x0 0x50044000 0x0 0x2000>, 177 <0x0 0x50046000 0x0 0x2000>; 178 interrupts = <GIC_PPI 9 179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 180 interrupt-parent = <&gic>; 181 }; 182 183 gpu@57000000 { 184 compatible = "nvidia,gk20a"; 185 reg = <0x0 0x57000000 0x0 0x01000000>, 186 <0x0 0x58000000 0x0 0x01000000>; 187 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 189 interrupt-names = "stall", "nonstall"; 190 clocks = <&tegra_car TEGRA124_CLK_GPU>, 191 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 192 clock-names = "gpu", "pwr"; 193 resets = <&tegra_car 184>; 194 reset-names = "gpu"; 195 status = "disabled"; 196 }; 197 198 lic: interrupt-controller@60004000 { 199 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 200 reg = <0x0 0x60004000 0x0 0x100>, 201 <0x0 0x60004100 0x0 0x100>, 202 <0x0 0x60004200 0x0 0x100>, 203 <0x0 0x60004300 0x0 0x100>, 204 <0x0 0x60004400 0x0 0x100>; 205 interrupt-controller; 206 #interrupt-cells = <3>; 207 interrupt-parent = <&gic>; 208 }; 209 210 timer@60005000 { 211 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 212 reg = <0x0 0x60005000 0x0 0x400>; 213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 220 clock-names = "timer"; 221 }; 222 223 tegra_car: clock@60006000 { 224 compatible = "nvidia,tegra132-car"; 225 reg = <0x0 0x60006000 0x0 0x1000>; 226 #clock-cells = <1>; 227 #reset-cells = <1>; 228 nvidia,external-memory-controller = <&emc>; 229 }; 230 231 flow-controller@60007000 { 232 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 233 reg = <0x0 0x60007000 0x0 0x1000>; 234 }; 235 236 actmon@6000c800 { 237 compatible = "nvidia,tegra124-actmon"; 238 reg = <0x0 0x6000c800 0x0 0x400>; 239 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 241 <&tegra_car TEGRA124_CLK_EMC>; 242 clock-names = "actmon", "emc"; 243 resets = <&tegra_car 119>; 244 reset-names = "actmon"; 245 }; 246 247 gpio: gpio@6000d000 { 248 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 249 reg = <0x0 0x6000d000 0x0 0x1000>; 250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 258 #gpio-cells = <2>; 259 gpio-controller; 260 #interrupt-cells = <2>; 261 interrupt-controller; 262 }; 263 264 apbdma: dma@60020000 { 265 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 266 reg = <0x0 0x60020000 0x0 0x1400>; 267 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 300 clock-names = "dma"; 301 resets = <&tegra_car 34>; 302 reset-names = "dma"; 303 #dma-cells = <1>; 304 }; 305 306 apbmisc@70000800 { 307 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 308 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 309 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 310 }; 311 312 pinmux: pinmux@70000868 { 313 compatible = "nvidia,tegra124-pinmux"; 314 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 315 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 316 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 317 }; 318 319 /* 320 * There are two serial driver i.e. 8250 based simple serial 321 * driver and APB DMA based serial driver for higher baudrate 322 * and performance. To enable the 8250 based driver, the compatible 323 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 324 * the APB DMA based serial driver, the compatible is 325 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 326 */ 327 uarta: serial@70006000 { 328 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 329 reg = <0x0 0x70006000 0x0 0x40>; 330 reg-shift = <2>; 331 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 333 clock-names = "serial"; 334 resets = <&tegra_car 6>; 335 reset-names = "serial"; 336 dmas = <&apbdma 8>, <&apbdma 8>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 }; 340 341 uartb: serial@70006040 { 342 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 343 reg = <0x0 0x70006040 0x0 0x40>; 344 reg-shift = <2>; 345 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 347 clock-names = "serial"; 348 resets = <&tegra_car 7>; 349 reset-names = "serial"; 350 dmas = <&apbdma 9>, <&apbdma 9>; 351 dma-names = "rx", "tx"; 352 status = "disabled"; 353 }; 354 355 uartc: serial@70006200 { 356 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 357 reg = <0x0 0x70006200 0x0 0x40>; 358 reg-shift = <2>; 359 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 361 clock-names = "serial"; 362 resets = <&tegra_car 55>; 363 reset-names = "serial"; 364 dmas = <&apbdma 10>, <&apbdma 10>; 365 dma-names = "rx", "tx"; 366 status = "disabled"; 367 }; 368 369 uartd: serial@70006300 { 370 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 371 reg = <0x0 0x70006300 0x0 0x40>; 372 reg-shift = <2>; 373 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 375 clock-names = "serial"; 376 resets = <&tegra_car 65>; 377 reset-names = "serial"; 378 dmas = <&apbdma 19>, <&apbdma 19>; 379 dma-names = "rx", "tx"; 380 status = "disabled"; 381 }; 382 383 pwm: pwm@7000a000 { 384 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 385 reg = <0x0 0x7000a000 0x0 0x100>; 386 #pwm-cells = <2>; 387 clocks = <&tegra_car TEGRA124_CLK_PWM>; 388 clock-names = "pwm"; 389 resets = <&tegra_car 17>; 390 reset-names = "pwm"; 391 status = "disabled"; 392 }; 393 394 i2c@7000c000 { 395 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 396 reg = <0x0 0x7000c000 0x0 0x100>; 397 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 401 clock-names = "div-clk"; 402 resets = <&tegra_car 12>; 403 reset-names = "i2c"; 404 dmas = <&apbdma 21>, <&apbdma 21>; 405 dma-names = "rx", "tx"; 406 status = "disabled"; 407 }; 408 409 i2c@7000c400 { 410 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 411 reg = <0x0 0x7000c400 0x0 0x100>; 412 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 416 clock-names = "div-clk"; 417 resets = <&tegra_car 54>; 418 reset-names = "i2c"; 419 dmas = <&apbdma 22>, <&apbdma 22>; 420 dma-names = "rx", "tx"; 421 status = "disabled"; 422 }; 423 424 i2c@7000c500 { 425 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 426 reg = <0x0 0x7000c500 0x0 0x100>; 427 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 431 clock-names = "div-clk"; 432 resets = <&tegra_car 67>; 433 reset-names = "i2c"; 434 dmas = <&apbdma 23>, <&apbdma 23>; 435 dma-names = "rx", "tx"; 436 status = "disabled"; 437 }; 438 439 i2c@7000c700 { 440 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 441 reg = <0x0 0x7000c700 0x0 0x100>; 442 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 446 clock-names = "div-clk"; 447 resets = <&tegra_car 103>; 448 reset-names = "i2c"; 449 dmas = <&apbdma 26>, <&apbdma 26>; 450 dma-names = "rx", "tx"; 451 status = "disabled"; 452 }; 453 454 i2c@7000d000 { 455 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 456 reg = <0x0 0x7000d000 0x0 0x100>; 457 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 461 clock-names = "div-clk"; 462 resets = <&tegra_car 47>; 463 reset-names = "i2c"; 464 dmas = <&apbdma 24>, <&apbdma 24>; 465 dma-names = "rx", "tx"; 466 status = "disabled"; 467 }; 468 469 i2c@7000d100 { 470 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 471 reg = <0x0 0x7000d100 0x0 0x100>; 472 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 476 clock-names = "div-clk"; 477 resets = <&tegra_car 166>; 478 reset-names = "i2c"; 479 dmas = <&apbdma 30>, <&apbdma 30>; 480 dma-names = "rx", "tx"; 481 status = "disabled"; 482 }; 483 484 spi@7000d400 { 485 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 486 reg = <0x0 0x7000d400 0x0 0x200>; 487 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 491 clock-names = "spi"; 492 resets = <&tegra_car 41>; 493 reset-names = "spi"; 494 dmas = <&apbdma 15>, <&apbdma 15>; 495 dma-names = "rx", "tx"; 496 status = "disabled"; 497 }; 498 499 spi@7000d600 { 500 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 501 reg = <0x0 0x7000d600 0x0 0x200>; 502 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 506 clock-names = "spi"; 507 resets = <&tegra_car 44>; 508 reset-names = "spi"; 509 dmas = <&apbdma 16>, <&apbdma 16>; 510 dma-names = "rx", "tx"; 511 status = "disabled"; 512 }; 513 514 spi@7000d800 { 515 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 516 reg = <0x0 0x7000d800 0x0 0x200>; 517 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 521 clock-names = "spi"; 522 resets = <&tegra_car 46>; 523 reset-names = "spi"; 524 dmas = <&apbdma 17>, <&apbdma 17>; 525 dma-names = "rx", "tx"; 526 status = "disabled"; 527 }; 528 529 spi@7000da00 { 530 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 531 reg = <0x0 0x7000da00 0x0 0x200>; 532 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 536 clock-names = "spi"; 537 resets = <&tegra_car 68>; 538 reset-names = "spi"; 539 dmas = <&apbdma 18>, <&apbdma 18>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 }; 543 544 spi@7000dc00 { 545 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 546 reg = <0x0 0x7000dc00 0x0 0x200>; 547 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 551 clock-names = "spi"; 552 resets = <&tegra_car 104>; 553 reset-names = "spi"; 554 dmas = <&apbdma 27>, <&apbdma 27>; 555 dma-names = "rx", "tx"; 556 status = "disabled"; 557 }; 558 559 spi@7000de00 { 560 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 561 reg = <0x0 0x7000de00 0x0 0x200>; 562 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 566 clock-names = "spi"; 567 resets = <&tegra_car 105>; 568 reset-names = "spi"; 569 dmas = <&apbdma 28>, <&apbdma 28>; 570 dma-names = "rx", "tx"; 571 status = "disabled"; 572 }; 573 574 rtc@7000e000 { 575 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 576 reg = <0x0 0x7000e000 0x0 0x100>; 577 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&tegra_car TEGRA124_CLK_RTC>; 579 clock-names = "rtc"; 580 }; 581 582 tegra_pmc: pmc@7000e400 { 583 compatible = "nvidia,tegra124-pmc"; 584 reg = <0x0 0x7000e400 0x0 0x400>; 585 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 586 clock-names = "pclk", "clk32k_in"; 587 #clock-cells = <1>; 588 }; 589 590 fuse@7000f800 { 591 compatible = "nvidia,tegra124-efuse"; 592 reg = <0x0 0x7000f800 0x0 0x400>; 593 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 594 clock-names = "fuse"; 595 resets = <&tegra_car 39>; 596 reset-names = "fuse"; 597 }; 598 599 mc: memory-controller@70019000 { 600 compatible = "nvidia,tegra132-mc"; 601 reg = <0x0 0x70019000 0x0 0x1000>; 602 clocks = <&tegra_car TEGRA124_CLK_MC>; 603 clock-names = "mc"; 604 605 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 606 607 #iommu-cells = <1>; 608 }; 609 610 emc: external-memory-controller@7001b000 { 611 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 612 reg = <0x0 0x7001b000 0x0 0x1000>; 613 clocks = <&tegra_car TEGRA124_CLK_EMC>; 614 clock-names = "emc"; 615 616 nvidia,memory-controller = <&mc>; 617 }; 618 619 sata@70020000 { 620 compatible = "nvidia,tegra124-ahci"; 621 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 622 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 623 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&tegra_car TEGRA124_CLK_SATA>, 625 <&tegra_car TEGRA124_CLK_SATA_OOB>, 626 <&tegra_car TEGRA124_CLK_CML1>, 627 <&tegra_car TEGRA124_CLK_PLL_E>; 628 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 629 resets = <&tegra_car 124>, 630 <&tegra_car 123>, 631 <&tegra_car 129>; 632 reset-names = "sata", "sata-oob", "sata-cold"; 633 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 634 phy-names = "sata-phy"; 635 status = "disabled"; 636 }; 637 638 hda@70030000 { 639 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 640 "nvidia,tegra30-hda"; 641 reg = <0x0 0x70030000 0x0 0x10000>; 642 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&tegra_car TEGRA124_CLK_HDA>, 644 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 645 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 646 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 647 resets = <&tegra_car 125>, /* hda */ 648 <&tegra_car 128>, /* hda2hdmi */ 649 <&tegra_car 111>; /* hda2codec_2x */ 650 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 651 status = "disabled"; 652 }; 653 654 padctl: padctl@7009f000 { 655 compatible = "nvidia,tegra132-xusb-padctl", 656 "nvidia,tegra124-xusb-padctl"; 657 reg = <0x0 0x7009f000 0x0 0x1000>; 658 resets = <&tegra_car 142>; 659 reset-names = "padctl"; 660 661 #phy-cells = <1>; 662 663 phys { 664 pcie-0 { 665 status = "disabled"; 666 }; 667 668 sata-0 { 669 status = "disabled"; 670 }; 671 672 usb3-0 { 673 status = "disabled"; 674 }; 675 676 usb3-1 { 677 status = "disabled"; 678 }; 679 680 utmi-0 { 681 status = "disabled"; 682 }; 683 684 utmi-1 { 685 status = "disabled"; 686 }; 687 688 utmi-2 { 689 status = "disabled"; 690 }; 691 }; 692 }; 693 694 mmc@700b0000 { 695 compatible = "nvidia,tegra124-sdhci"; 696 reg = <0x0 0x700b0000 0x0 0x200>; 697 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 699 clock-names = "sdhci"; 700 resets = <&tegra_car 14>; 701 reset-names = "sdhci"; 702 status = "disabled"; 703 }; 704 705 mmc@700b0200 { 706 compatible = "nvidia,tegra124-sdhci"; 707 reg = <0x0 0x700b0200 0x0 0x200>; 708 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 710 clock-names = "sdhci"; 711 resets = <&tegra_car 9>; 712 reset-names = "sdhci"; 713 status = "disabled"; 714 }; 715 716 mmc@700b0400 { 717 compatible = "nvidia,tegra124-sdhci"; 718 reg = <0x0 0x700b0400 0x0 0x200>; 719 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 721 clock-names = "sdhci"; 722 resets = <&tegra_car 69>; 723 reset-names = "sdhci"; 724 status = "disabled"; 725 }; 726 727 mmc@700b0600 { 728 compatible = "nvidia,tegra124-sdhci"; 729 reg = <0x0 0x700b0600 0x0 0x200>; 730 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 732 clock-names = "sdhci"; 733 resets = <&tegra_car 15>; 734 reset-names = "sdhci"; 735 status = "disabled"; 736 }; 737 738 soctherm: thermal-sensor@700e2000 { 739 compatible = "nvidia,tegra132-soctherm"; 740 reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */ 741 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 742 reg-names = "soctherm-reg", "ccroc-reg"; 743 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 745 <&tegra_car TEGRA124_CLK_SOC_THERM>; 746 clock-names = "tsensor", "soctherm"; 747 resets = <&tegra_car 78>; 748 reset-names = "soctherm"; 749 #thermal-sensor-cells = <1>; 750 751 throttle-cfgs { 752 throttle_heavy: heavy { 753 nvidia,priority = <100>; 754 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 755 756 #cooling-cells = <2>; 757 }; 758 }; 759 }; 760 761 thermal-zones { 762 cpu { 763 polling-delay-passive = <1000>; 764 polling-delay = <0>; 765 766 thermal-sensors = 767 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 768 769 trips { 770 cpu_shutdown_trip { 771 temperature = <105000>; 772 hysteresis = <1000>; 773 type = "critical"; 774 }; 775 776 cpu_throttle_trip: throttle-trip { 777 temperature = <102000>; 778 hysteresis = <1000>; 779 type = "hot"; 780 }; 781 }; 782 783 cooling-maps { 784 map0 { 785 trip = <&cpu_throttle_trip>; 786 cooling-device = <&throttle_heavy 1 1>; 787 }; 788 }; 789 }; 790 mem { 791 polling-delay-passive = <0>; 792 polling-delay = <0>; 793 794 thermal-sensors = 795 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 796 797 trips { 798 mem_shutdown_trip { 799 temperature = <101000>; 800 hysteresis = <1000>; 801 type = "critical"; 802 }; 803 }; 804 805 cooling-maps { 806 /* 807 * There are currently no cooling maps, 808 * because there are no cooling devices. 809 */ 810 }; 811 }; 812 gpu { 813 polling-delay-passive = <1000>; 814 polling-delay = <0>; 815 816 thermal-sensors = 817 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 818 819 trips { 820 gpu_shutdown_trip { 821 temperature = <101000>; 822 hysteresis = <1000>; 823 type = "critical"; 824 }; 825 826 gpu_throttle_trip: throttle-trip { 827 temperature = <99000>; 828 hysteresis = <1000>; 829 type = "hot"; 830 }; 831 }; 832 833 cooling-maps { 834 map0 { 835 trip = <&gpu_throttle_trip>; 836 cooling-device = <&throttle_heavy 1 1>; 837 }; 838 }; 839 }; 840 pllx { 841 polling-delay-passive = <0>; 842 polling-delay = <0>; 843 844 thermal-sensors = 845 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 846 847 trips { 848 pllx_shutdown_trip { 849 temperature = <105000>; 850 hysteresis = <1000>; 851 type = "critical"; 852 }; 853 }; 854 855 cooling-maps { 856 /* 857 * There are currently no cooling maps, 858 * because there are no cooling devices. 859 */ 860 }; 861 }; 862 }; 863 864 ahub@70300000 { 865 compatible = "nvidia,tegra124-ahub"; 866 reg = <0x0 0x70300000 0x0 0x200>, 867 <0x0 0x70300800 0x0 0x800>, 868 <0x0 0x70300200 0x0 0x600>; 869 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 871 <&tegra_car TEGRA124_CLK_APBIF>; 872 clock-names = "d_audio", "apbif"; 873 resets = <&tegra_car 106>, /* d_audio */ 874 <&tegra_car 107>, /* apbif */ 875 <&tegra_car 30>, /* i2s0 */ 876 <&tegra_car 11>, /* i2s1 */ 877 <&tegra_car 18>, /* i2s2 */ 878 <&tegra_car 101>, /* i2s3 */ 879 <&tegra_car 102>, /* i2s4 */ 880 <&tegra_car 108>, /* dam0 */ 881 <&tegra_car 109>, /* dam1 */ 882 <&tegra_car 110>, /* dam2 */ 883 <&tegra_car 10>, /* spdif */ 884 <&tegra_car 153>, /* amx */ 885 <&tegra_car 185>, /* amx1 */ 886 <&tegra_car 154>, /* adx */ 887 <&tegra_car 180>, /* adx1 */ 888 <&tegra_car 186>, /* afc0 */ 889 <&tegra_car 187>, /* afc1 */ 890 <&tegra_car 188>, /* afc2 */ 891 <&tegra_car 189>, /* afc3 */ 892 <&tegra_car 190>, /* afc4 */ 893 <&tegra_car 191>; /* afc5 */ 894 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 895 "i2s3", "i2s4", "dam0", "dam1", "dam2", 896 "spdif", "amx", "amx1", "adx", "adx1", 897 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 898 dmas = <&apbdma 1>, <&apbdma 1>, 899 <&apbdma 2>, <&apbdma 2>, 900 <&apbdma 3>, <&apbdma 3>, 901 <&apbdma 4>, <&apbdma 4>, 902 <&apbdma 6>, <&apbdma 6>, 903 <&apbdma 7>, <&apbdma 7>, 904 <&apbdma 12>, <&apbdma 12>, 905 <&apbdma 13>, <&apbdma 13>, 906 <&apbdma 14>, <&apbdma 14>, 907 <&apbdma 29>, <&apbdma 29>; 908 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 909 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 910 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 911 "rx9", "tx9"; 912 ranges; 913 #address-cells = <2>; 914 #size-cells = <2>; 915 916 tegra_i2s0: i2s@70301000 { 917 compatible = "nvidia,tegra124-i2s"; 918 reg = <0x0 0x70301000 0x0 0x100>; 919 nvidia,ahub-cif-ids = <4 4>; 920 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 921 clock-names = "i2s"; 922 resets = <&tegra_car 30>; 923 reset-names = "i2s"; 924 status = "disabled"; 925 }; 926 927 tegra_i2s1: i2s@70301100 { 928 compatible = "nvidia,tegra124-i2s"; 929 reg = <0x0 0x70301100 0x0 0x100>; 930 nvidia,ahub-cif-ids = <5 5>; 931 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 932 clock-names = "i2s"; 933 resets = <&tegra_car 11>; 934 reset-names = "i2s"; 935 status = "disabled"; 936 }; 937 938 tegra_i2s2: i2s@70301200 { 939 compatible = "nvidia,tegra124-i2s"; 940 reg = <0x0 0x70301200 0x0 0x100>; 941 nvidia,ahub-cif-ids = <6 6>; 942 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 943 clock-names = "i2s"; 944 resets = <&tegra_car 18>; 945 reset-names = "i2s"; 946 status = "disabled"; 947 }; 948 949 tegra_i2s3: i2s@70301300 { 950 compatible = "nvidia,tegra124-i2s"; 951 reg = <0x0 0x70301300 0x0 0x100>; 952 nvidia,ahub-cif-ids = <7 7>; 953 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 954 clock-names = "i2s"; 955 resets = <&tegra_car 101>; 956 reset-names = "i2s"; 957 status = "disabled"; 958 }; 959 960 tegra_i2s4: i2s@70301400 { 961 compatible = "nvidia,tegra124-i2s"; 962 reg = <0x0 0x70301400 0x0 0x100>; 963 nvidia,ahub-cif-ids = <8 8>; 964 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 965 clock-names = "i2s"; 966 resets = <&tegra_car 102>; 967 reset-names = "i2s"; 968 status = "disabled"; 969 }; 970 }; 971 972 usb@7d000000 { 973 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 974 reg = <0x0 0x7d000000 0x0 0x4000>; 975 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 976 phy_type = "utmi"; 977 clocks = <&tegra_car TEGRA124_CLK_USBD>; 978 clock-names = "usb"; 979 resets = <&tegra_car 22>; 980 reset-names = "usb"; 981 nvidia,phy = <&phy1>; 982 status = "disabled"; 983 }; 984 985 phy1: usb-phy@7d000000 { 986 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 987 reg = <0x0 0x7d000000 0x0 0x4000>, 988 <0x0 0x7d000000 0x0 0x4000>; 989 phy_type = "utmi"; 990 clocks = <&tegra_car TEGRA124_CLK_USBD>, 991 <&tegra_car TEGRA124_CLK_PLL_U>, 992 <&tegra_car TEGRA124_CLK_USBD>; 993 clock-names = "reg", "pll_u", "utmi-pads"; 994 resets = <&tegra_car 22>, <&tegra_car 22>; 995 reset-names = "usb", "utmi-pads"; 996 nvidia,hssync-start-delay = <0>; 997 nvidia,idle-wait-delay = <17>; 998 nvidia,elastic-limit = <16>; 999 nvidia,term-range-adj = <6>; 1000 nvidia,xcvr-setup = <9>; 1001 nvidia,xcvr-lsfslew = <0>; 1002 nvidia,xcvr-lsrslew = <3>; 1003 nvidia,hssquelch-level = <2>; 1004 nvidia,hsdiscon-level = <5>; 1005 nvidia,xcvr-hsslew = <12>; 1006 nvidia,has-utmi-pad-registers; 1007 status = "disabled"; 1008 }; 1009 1010 usb@7d004000 { 1011 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1012 reg = <0x0 0x7d004000 0x0 0x4000>; 1013 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1014 phy_type = "utmi"; 1015 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1016 clock-names = "usb"; 1017 resets = <&tegra_car 58>; 1018 reset-names = "usb"; 1019 nvidia,phy = <&phy2>; 1020 status = "disabled"; 1021 }; 1022 1023 phy2: usb-phy@7d004000 { 1024 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1025 reg = <0x0 0x7d004000 0x0 0x4000>, 1026 <0x0 0x7d000000 0x0 0x4000>; 1027 phy_type = "utmi"; 1028 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1029 <&tegra_car TEGRA124_CLK_PLL_U>, 1030 <&tegra_car TEGRA124_CLK_USBD>; 1031 clock-names = "reg", "pll_u", "utmi-pads"; 1032 resets = <&tegra_car 58>, <&tegra_car 22>; 1033 reset-names = "usb", "utmi-pads"; 1034 nvidia,hssync-start-delay = <0>; 1035 nvidia,idle-wait-delay = <17>; 1036 nvidia,elastic-limit = <16>; 1037 nvidia,term-range-adj = <6>; 1038 nvidia,xcvr-setup = <9>; 1039 nvidia,xcvr-lsfslew = <0>; 1040 nvidia,xcvr-lsrslew = <3>; 1041 nvidia,hssquelch-level = <2>; 1042 nvidia,hsdiscon-level = <5>; 1043 nvidia,xcvr-hsslew = <12>; 1044 status = "disabled"; 1045 }; 1046 1047 usb@7d008000 { 1048 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1049 reg = <0x0 0x7d008000 0x0 0x4000>; 1050 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1051 phy_type = "utmi"; 1052 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1053 clock-names = "usb"; 1054 resets = <&tegra_car 59>; 1055 reset-names = "usb"; 1056 nvidia,phy = <&phy3>; 1057 status = "disabled"; 1058 }; 1059 1060 phy3: usb-phy@7d008000 { 1061 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1062 reg = <0x0 0x7d008000 0x0 0x4000>, 1063 <0x0 0x7d000000 0x0 0x4000>; 1064 phy_type = "utmi"; 1065 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1066 <&tegra_car TEGRA124_CLK_PLL_U>, 1067 <&tegra_car TEGRA124_CLK_USBD>; 1068 clock-names = "reg", "pll_u", "utmi-pads"; 1069 resets = <&tegra_car 59>, <&tegra_car 22>; 1070 reset-names = "usb", "utmi-pads"; 1071 nvidia,hssync-start-delay = <0>; 1072 nvidia,idle-wait-delay = <17>; 1073 nvidia,elastic-limit = <16>; 1074 nvidia,term-range-adj = <6>; 1075 nvidia,xcvr-setup = <9>; 1076 nvidia,xcvr-lsfslew = <0>; 1077 nvidia,xcvr-lsrslew = <3>; 1078 nvidia,hssquelch-level = <2>; 1079 nvidia,hsdiscon-level = <5>; 1080 nvidia,xcvr-hsslew = <12>; 1081 status = "disabled"; 1082 }; 1083 1084 cpus { 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 1088 cpu@0 { 1089 device_type = "cpu"; 1090 compatible = "nvidia,denver"; 1091 reg = <0>; 1092 }; 1093 1094 cpu@1 { 1095 device_type = "cpu"; 1096 compatible = "nvidia,denver"; 1097 reg = <1>; 1098 }; 1099 }; 1100 1101 timer { 1102 compatible = "arm,armv7-timer"; 1103 interrupts = <GIC_PPI 13 1104 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1105 <GIC_PPI 14 1106 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1107 <GIC_PPI 11 1108 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1109 <GIC_PPI 10 1110 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1111 interrupt-parent = <&gic>; 1112 }; 1113}; 1114