1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11/ { 12 compatible = "nvidia,tegra132", "nvidia,tegra124"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra124-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 21 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 22 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 37 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 38 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 39 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 40 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 43 <&tegra_car TEGRA124_CLK_AFI>, 44 <&tegra_car TEGRA124_CLK_PLL_E>, 45 <&tegra_car TEGRA124_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 pci@1,0 { 54 device_type = "pci"; 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 56 reg = <0x000800 0 0 0 0>; 57 bus-range = <0x00 0xff>; 58 status = "disabled"; 59 60 #address-cells = <3>; 61 #size-cells = <2>; 62 ranges; 63 64 nvidia,num-lanes = <2>; 65 }; 66 67 pci@2,0 { 68 device_type = "pci"; 69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 70 reg = <0x001000 0 0 0 0>; 71 bus-range = <0x00 0xff>; 72 status = "disabled"; 73 74 #address-cells = <3>; 75 #size-cells = <2>; 76 ranges; 77 78 nvidia,num-lanes = <1>; 79 }; 80 }; 81 82 host1x@50000000 { 83 compatible = "nvidia,tegra132-host1x", 84 "nvidia,tegra124-host1x"; 85 reg = <0x0 0x50000000 0x0 0x00034000>; 86 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 87 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 88 interrupt-names = "syncpt", "host1x"; 89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 90 clock-names = "host1x"; 91 resets = <&tegra_car 28>; 92 reset-names = "host1x"; 93 94 #address-cells = <2>; 95 #size-cells = <2>; 96 97 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 98 99 dc@54200000 { 100 compatible = "nvidia,tegra124-dc"; 101 reg = <0x0 0x54200000 0x0 0x00040000>; 102 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 104 clock-names = "dc"; 105 resets = <&tegra_car 27>; 106 reset-names = "dc"; 107 108 iommus = <&mc TEGRA_SWGROUP_DC>; 109 110 nvidia,head = <0>; 111 }; 112 113 dc@54240000 { 114 compatible = "nvidia,tegra124-dc"; 115 reg = <0x0 0x54240000 0x0 0x00040000>; 116 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 118 clock-names = "dc"; 119 resets = <&tegra_car 26>; 120 reset-names = "dc"; 121 122 iommus = <&mc TEGRA_SWGROUP_DCB>; 123 124 nvidia,head = <1>; 125 }; 126 127 hdmi@54280000 { 128 compatible = "nvidia,tegra124-hdmi"; 129 reg = <0x0 0x54280000 0x0 0x00040000>; 130 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 132 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 133 clock-names = "hdmi", "parent"; 134 resets = <&tegra_car 51>; 135 reset-names = "hdmi"; 136 status = "disabled"; 137 }; 138 139 sor@54540000 { 140 compatible = "nvidia,tegra124-sor"; 141 reg = <0x0 0x54540000 0x0 0x00040000>; 142 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 144 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 145 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 146 <&tegra_car TEGRA124_CLK_PLL_DP>, 147 <&tegra_car TEGRA124_CLK_CLK_M>; 148 clock-names = "sor", "out", "parent", "dp", "safe"; 149 resets = <&tegra_car 182>; 150 reset-names = "sor"; 151 status = "disabled"; 152 }; 153 154 dpaux: dpaux@545c0000 { 155 compatible = "nvidia,tegra124-dpaux"; 156 reg = <0x0 0x545c0000 0x0 0x00040000>; 157 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 159 <&tegra_car TEGRA124_CLK_PLL_DP>; 160 clock-names = "dpaux", "parent"; 161 resets = <&tegra_car 181>; 162 reset-names = "dpaux"; 163 status = "disabled"; 164 }; 165 }; 166 167 gic: interrupt-controller@50041000 { 168 compatible = "arm,cortex-a15-gic"; 169 #interrupt-cells = <3>; 170 interrupt-controller; 171 reg = <0x0 0x50041000 0x0 0x1000>, 172 <0x0 0x50042000 0x0 0x2000>, 173 <0x0 0x50044000 0x0 0x2000>, 174 <0x0 0x50046000 0x0 0x2000>; 175 interrupts = <GIC_PPI 9 176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 177 interrupt-parent = <&gic>; 178 }; 179 180 gpu@57000000 { 181 compatible = "nvidia,gk20a"; 182 reg = <0x0 0x57000000 0x0 0x01000000>, 183 <0x0 0x58000000 0x0 0x01000000>; 184 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "stall", "nonstall"; 187 clocks = <&tegra_car TEGRA124_CLK_GPU>, 188 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 189 clock-names = "gpu", "pwr"; 190 resets = <&tegra_car 184>; 191 reset-names = "gpu"; 192 status = "disabled"; 193 }; 194 195 lic: interrupt-controller@60004000 { 196 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 197 reg = <0x0 0x60004000 0x0 0x100>, 198 <0x0 0x60004100 0x0 0x100>, 199 <0x0 0x60004200 0x0 0x100>, 200 <0x0 0x60004300 0x0 0x100>, 201 <0x0 0x60004400 0x0 0x100>; 202 interrupt-controller; 203 #interrupt-cells = <3>; 204 interrupt-parent = <&gic>; 205 }; 206 207 timer@60005000 { 208 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 209 reg = <0x0 0x60005000 0x0 0x400>; 210 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 217 clock-names = "timer"; 218 }; 219 220 tegra_car: clock@60006000 { 221 compatible = "nvidia,tegra132-car"; 222 reg = <0x0 0x60006000 0x0 0x1000>; 223 #clock-cells = <1>; 224 #reset-cells = <1>; 225 nvidia,external-memory-controller = <&emc>; 226 }; 227 228 flow-controller@60007000 { 229 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 230 reg = <0x0 0x60007000 0x0 0x1000>; 231 }; 232 233 actmon@6000c800 { 234 compatible = "nvidia,tegra124-actmon"; 235 reg = <0x0 0x6000c800 0x0 0x400>; 236 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 238 <&tegra_car TEGRA124_CLK_EMC>; 239 clock-names = "actmon", "emc"; 240 resets = <&tegra_car 119>; 241 reset-names = "actmon"; 242 }; 243 244 gpio: gpio@6000d000 { 245 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 246 reg = <0x0 0x6000d000 0x0 0x1000>; 247 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 255 #gpio-cells = <2>; 256 gpio-controller; 257 #interrupt-cells = <2>; 258 interrupt-controller; 259 }; 260 261 apbdma: dma@60020000 { 262 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 263 reg = <0x0 0x60020000 0x0 0x1400>; 264 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 297 clock-names = "dma"; 298 resets = <&tegra_car 34>; 299 reset-names = "dma"; 300 #dma-cells = <1>; 301 }; 302 303 apbmisc@70000800 { 304 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 305 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 306 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 307 }; 308 309 pinmux: pinmux@70000868 { 310 compatible = "nvidia,tegra124-pinmux"; 311 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 312 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 313 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 314 }; 315 316 /* 317 * There are two serial driver i.e. 8250 based simple serial 318 * driver and APB DMA based serial driver for higher baudrate 319 * and performance. To enable the 8250 based driver, the compatible 320 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 321 * the APB DMA based serial driver, the compatible is 322 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 323 */ 324 uarta: serial@70006000 { 325 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 326 reg = <0x0 0x70006000 0x0 0x40>; 327 reg-shift = <2>; 328 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 330 clock-names = "serial"; 331 resets = <&tegra_car 6>; 332 reset-names = "serial"; 333 dmas = <&apbdma 8>, <&apbdma 8>; 334 dma-names = "rx", "tx"; 335 status = "disabled"; 336 }; 337 338 uartb: serial@70006040 { 339 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 340 reg = <0x0 0x70006040 0x0 0x40>; 341 reg-shift = <2>; 342 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 344 clock-names = "serial"; 345 resets = <&tegra_car 7>; 346 reset-names = "serial"; 347 dmas = <&apbdma 9>, <&apbdma 9>; 348 dma-names = "rx", "tx"; 349 status = "disabled"; 350 }; 351 352 uartc: serial@70006200 { 353 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 354 reg = <0x0 0x70006200 0x0 0x40>; 355 reg-shift = <2>; 356 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 358 clock-names = "serial"; 359 resets = <&tegra_car 55>; 360 reset-names = "serial"; 361 dmas = <&apbdma 10>, <&apbdma 10>; 362 dma-names = "rx", "tx"; 363 status = "disabled"; 364 }; 365 366 uartd: serial@70006300 { 367 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 368 reg = <0x0 0x70006300 0x0 0x40>; 369 reg-shift = <2>; 370 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 372 clock-names = "serial"; 373 resets = <&tegra_car 65>; 374 reset-names = "serial"; 375 dmas = <&apbdma 19>, <&apbdma 19>; 376 dma-names = "rx", "tx"; 377 status = "disabled"; 378 }; 379 380 pwm: pwm@7000a000 { 381 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 382 reg = <0x0 0x7000a000 0x0 0x100>; 383 #pwm-cells = <2>; 384 clocks = <&tegra_car TEGRA124_CLK_PWM>; 385 clock-names = "pwm"; 386 resets = <&tegra_car 17>; 387 reset-names = "pwm"; 388 status = "disabled"; 389 }; 390 391 i2c@7000c000 { 392 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 393 reg = <0x0 0x7000c000 0x0 0x100>; 394 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 398 clock-names = "div-clk"; 399 resets = <&tegra_car 12>; 400 reset-names = "i2c"; 401 dmas = <&apbdma 21>, <&apbdma 21>; 402 dma-names = "rx", "tx"; 403 status = "disabled"; 404 }; 405 406 i2c@7000c400 { 407 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 408 reg = <0x0 0x7000c400 0x0 0x100>; 409 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 413 clock-names = "div-clk"; 414 resets = <&tegra_car 54>; 415 reset-names = "i2c"; 416 dmas = <&apbdma 22>, <&apbdma 22>; 417 dma-names = "rx", "tx"; 418 status = "disabled"; 419 }; 420 421 i2c@7000c500 { 422 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 423 reg = <0x0 0x7000c500 0x0 0x100>; 424 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 428 clock-names = "div-clk"; 429 resets = <&tegra_car 67>; 430 reset-names = "i2c"; 431 dmas = <&apbdma 23>, <&apbdma 23>; 432 dma-names = "rx", "tx"; 433 status = "disabled"; 434 }; 435 436 i2c@7000c700 { 437 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 438 reg = <0x0 0x7000c700 0x0 0x100>; 439 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 443 clock-names = "div-clk"; 444 resets = <&tegra_car 103>; 445 reset-names = "i2c"; 446 dmas = <&apbdma 26>, <&apbdma 26>; 447 dma-names = "rx", "tx"; 448 status = "disabled"; 449 }; 450 451 i2c@7000d000 { 452 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 453 reg = <0x0 0x7000d000 0x0 0x100>; 454 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 458 clock-names = "div-clk"; 459 resets = <&tegra_car 47>; 460 reset-names = "i2c"; 461 dmas = <&apbdma 24>, <&apbdma 24>; 462 dma-names = "rx", "tx"; 463 status = "disabled"; 464 }; 465 466 i2c@7000d100 { 467 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 468 reg = <0x0 0x7000d100 0x0 0x100>; 469 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 473 clock-names = "div-clk"; 474 resets = <&tegra_car 166>; 475 reset-names = "i2c"; 476 dmas = <&apbdma 30>, <&apbdma 30>; 477 dma-names = "rx", "tx"; 478 status = "disabled"; 479 }; 480 481 spi@7000d400 { 482 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 483 reg = <0x0 0x7000d400 0x0 0x200>; 484 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 488 clock-names = "spi"; 489 resets = <&tegra_car 41>; 490 reset-names = "spi"; 491 dmas = <&apbdma 15>, <&apbdma 15>; 492 dma-names = "rx", "tx"; 493 status = "disabled"; 494 }; 495 496 spi@7000d600 { 497 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 498 reg = <0x0 0x7000d600 0x0 0x200>; 499 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 503 clock-names = "spi"; 504 resets = <&tegra_car 44>; 505 reset-names = "spi"; 506 dmas = <&apbdma 16>, <&apbdma 16>; 507 dma-names = "rx", "tx"; 508 status = "disabled"; 509 }; 510 511 spi@7000d800 { 512 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 513 reg = <0x0 0x7000d800 0x0 0x200>; 514 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 518 clock-names = "spi"; 519 resets = <&tegra_car 46>; 520 reset-names = "spi"; 521 dmas = <&apbdma 17>, <&apbdma 17>; 522 dma-names = "rx", "tx"; 523 status = "disabled"; 524 }; 525 526 spi@7000da00 { 527 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 528 reg = <0x0 0x7000da00 0x0 0x200>; 529 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 533 clock-names = "spi"; 534 resets = <&tegra_car 68>; 535 reset-names = "spi"; 536 dmas = <&apbdma 18>, <&apbdma 18>; 537 dma-names = "rx", "tx"; 538 status = "disabled"; 539 }; 540 541 spi@7000dc00 { 542 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 543 reg = <0x0 0x7000dc00 0x0 0x200>; 544 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 548 clock-names = "spi"; 549 resets = <&tegra_car 104>; 550 reset-names = "spi"; 551 dmas = <&apbdma 27>, <&apbdma 27>; 552 dma-names = "rx", "tx"; 553 status = "disabled"; 554 }; 555 556 spi@7000de00 { 557 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 558 reg = <0x0 0x7000de00 0x0 0x200>; 559 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 563 clock-names = "spi"; 564 resets = <&tegra_car 105>; 565 reset-names = "spi"; 566 dmas = <&apbdma 28>, <&apbdma 28>; 567 dma-names = "rx", "tx"; 568 status = "disabled"; 569 }; 570 571 rtc@7000e000 { 572 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 573 reg = <0x0 0x7000e000 0x0 0x100>; 574 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&tegra_car TEGRA124_CLK_RTC>; 576 clock-names = "rtc"; 577 }; 578 579 tegra_pmc: pmc@7000e400 { 580 compatible = "nvidia,tegra124-pmc"; 581 reg = <0x0 0x7000e400 0x0 0x400>; 582 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 583 clock-names = "pclk", "clk32k_in"; 584 #clock-cells = <1>; 585 }; 586 587 fuse@7000f800 { 588 compatible = "nvidia,tegra124-efuse"; 589 reg = <0x0 0x7000f800 0x0 0x400>; 590 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 591 clock-names = "fuse"; 592 resets = <&tegra_car 39>; 593 reset-names = "fuse"; 594 }; 595 596 mc: memory-controller@70019000 { 597 compatible = "nvidia,tegra132-mc"; 598 reg = <0x0 0x70019000 0x0 0x1000>; 599 clocks = <&tegra_car TEGRA124_CLK_MC>; 600 clock-names = "mc"; 601 602 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 603 604 #iommu-cells = <1>; 605 }; 606 607 emc: external-memory-controller@7001b000 { 608 compatible = "nvidia,tegra132-emc"; 609 reg = <0x0 0x7001b000 0x0 0x1000>; 610 clocks = <&tegra_car TEGRA124_CLK_EMC>; 611 clock-names = "emc"; 612 613 nvidia,memory-controller = <&mc>; 614 }; 615 616 sata@70020000 { 617 compatible = "nvidia,tegra124-ahci"; 618 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 619 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 620 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&tegra_car TEGRA124_CLK_SATA>, 622 <&tegra_car TEGRA124_CLK_SATA_OOB>, 623 <&tegra_car TEGRA124_CLK_CML1>, 624 <&tegra_car TEGRA124_CLK_PLL_E>; 625 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 626 resets = <&tegra_car 124>, 627 <&tegra_car 123>, 628 <&tegra_car 129>; 629 reset-names = "sata", "sata-oob", "sata-cold"; 630 status = "disabled"; 631 }; 632 633 hda@70030000 { 634 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 635 "nvidia,tegra30-hda"; 636 reg = <0x0 0x70030000 0x0 0x10000>; 637 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&tegra_car TEGRA124_CLK_HDA>, 639 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 640 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 641 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 642 resets = <&tegra_car 125>, /* hda */ 643 <&tegra_car 128>, /* hda2hdmi */ 644 <&tegra_car 111>; /* hda2codec_2x */ 645 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 646 status = "disabled"; 647 }; 648 649 usb@70090000 { 650 compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; 651 reg = <0x0 0x70090000 0x0 0x8000>, 652 <0x0 0x70098000 0x0 0x1000>, 653 <0x0 0x70099000 0x0 0x1000>; 654 reg-names = "hcd", "fpci", "ipfs"; 655 656 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 658 659 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 660 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 661 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 662 <&tegra_car TEGRA124_CLK_XUSB_SS>, 663 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 664 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 665 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 666 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 667 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 668 <&tegra_car TEGRA124_CLK_CLK_M>, 669 <&tegra_car TEGRA124_CLK_PLL_E>; 670 clock-names = "xusb_host", "xusb_host_src", 671 "xusb_falcon_src", "xusb_ss", 672 "xusb_ss_src", "xusb_ss_div2", 673 "xusb_hs_src", "xusb_fs_src", 674 "pll_u_480m", "clk_m", "pll_e"; 675 resets = <&tegra_car 89>, <&tegra_car 156>, 676 <&tegra_car 143>; 677 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 678 679 nvidia,xusb-padctl = <&padctl>; 680 681 status = "disabled"; 682 }; 683 684 padctl: padctl@7009f000 { 685 compatible = "nvidia,tegra132-xusb-padctl", 686 "nvidia,tegra124-xusb-padctl"; 687 reg = <0x0 0x7009f000 0x0 0x1000>; 688 resets = <&tegra_car 142>; 689 reset-names = "padctl"; 690 691 pads { 692 usb2 { 693 status = "disabled"; 694 695 lanes { 696 usb2-0 { 697 status = "disabled"; 698 #phy-cells = <0>; 699 }; 700 701 usb2-1 { 702 status = "disabled"; 703 #phy-cells = <0>; 704 }; 705 706 usb2-2 { 707 status = "disabled"; 708 #phy-cells = <0>; 709 }; 710 }; 711 }; 712 713 ulpi { 714 status = "disabled"; 715 716 lanes { 717 ulpi-0 { 718 status = "disabled"; 719 #phy-cells = <0>; 720 }; 721 }; 722 }; 723 724 hsic { 725 status = "disabled"; 726 727 lanes { 728 hsic-0 { 729 status = "disabled"; 730 #phy-cells = <0>; 731 }; 732 733 hsic-1 { 734 status = "disabled"; 735 #phy-cells = <0>; 736 }; 737 }; 738 }; 739 740 pcie { 741 status = "disabled"; 742 743 lanes { 744 pcie-0 { 745 status = "disabled"; 746 #phy-cells = <0>; 747 }; 748 749 pcie-1 { 750 status = "disabled"; 751 #phy-cells = <0>; 752 }; 753 754 pcie-2 { 755 status = "disabled"; 756 #phy-cells = <0>; 757 }; 758 759 pcie-3 { 760 status = "disabled"; 761 #phy-cells = <0>; 762 }; 763 764 pcie-4 { 765 status = "disabled"; 766 #phy-cells = <0>; 767 }; 768 }; 769 }; 770 771 sata { 772 status = "disabled"; 773 774 lanes { 775 sata-0 { 776 status = "disabled"; 777 #phy-cells = <0>; 778 }; 779 }; 780 }; 781 }; 782 783 ports { 784 usb2-0 { 785 status = "disabled"; 786 }; 787 788 usb2-1 { 789 status = "disabled"; 790 }; 791 792 usb2-2 { 793 status = "disabled"; 794 }; 795 796 hsic-0 { 797 status = "disabled"; 798 }; 799 800 hsic-1 { 801 status = "disabled"; 802 }; 803 804 usb3-0 { 805 status = "disabled"; 806 }; 807 808 usb3-1 { 809 status = "disabled"; 810 }; 811 }; 812 }; 813 814 mmc@700b0000 { 815 compatible = "nvidia,tegra124-sdhci"; 816 reg = <0x0 0x700b0000 0x0 0x200>; 817 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 819 clock-names = "sdhci"; 820 resets = <&tegra_car 14>; 821 reset-names = "sdhci"; 822 status = "disabled"; 823 }; 824 825 mmc@700b0200 { 826 compatible = "nvidia,tegra124-sdhci"; 827 reg = <0x0 0x700b0200 0x0 0x200>; 828 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 830 clock-names = "sdhci"; 831 resets = <&tegra_car 9>; 832 reset-names = "sdhci"; 833 status = "disabled"; 834 }; 835 836 mmc@700b0400 { 837 compatible = "nvidia,tegra124-sdhci"; 838 reg = <0x0 0x700b0400 0x0 0x200>; 839 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 841 clock-names = "sdhci"; 842 resets = <&tegra_car 69>; 843 reset-names = "sdhci"; 844 status = "disabled"; 845 }; 846 847 mmc@700b0600 { 848 compatible = "nvidia,tegra124-sdhci"; 849 reg = <0x0 0x700b0600 0x0 0x200>; 850 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 852 clock-names = "sdhci"; 853 resets = <&tegra_car 15>; 854 reset-names = "sdhci"; 855 status = "disabled"; 856 }; 857 858 soctherm: thermal-sensor@700e2000 { 859 compatible = "nvidia,tegra132-soctherm"; 860 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ 861 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 862 reg-names = "soctherm-reg", "ccroc-reg"; 863 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 865 <&tegra_car TEGRA124_CLK_SOC_THERM>; 866 clock-names = "tsensor", "soctherm"; 867 resets = <&tegra_car 78>; 868 reset-names = "soctherm"; 869 #thermal-sensor-cells = <1>; 870 871 throttle-cfgs { 872 throttle_heavy: heavy { 873 nvidia,priority = <100>; 874 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 875 876 #cooling-cells = <2>; 877 }; 878 }; 879 }; 880 881 thermal-zones { 882 cpu { 883 polling-delay-passive = <1000>; 884 polling-delay = <0>; 885 886 thermal-sensors = 887 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 888 889 trips { 890 cpu_shutdown_trip { 891 temperature = <105000>; 892 hysteresis = <1000>; 893 type = "critical"; 894 }; 895 896 cpu_throttle_trip: throttle-trip { 897 temperature = <102000>; 898 hysteresis = <1000>; 899 type = "hot"; 900 }; 901 }; 902 903 cooling-maps { 904 map0 { 905 trip = <&cpu_throttle_trip>; 906 cooling-device = <&throttle_heavy 1 1>; 907 }; 908 }; 909 }; 910 mem { 911 polling-delay-passive = <0>; 912 polling-delay = <0>; 913 914 thermal-sensors = 915 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 916 917 trips { 918 mem_shutdown_trip { 919 temperature = <101000>; 920 hysteresis = <1000>; 921 type = "critical"; 922 }; 923 }; 924 925 cooling-maps { 926 /* 927 * There are currently no cooling maps, 928 * because there are no cooling devices. 929 */ 930 }; 931 }; 932 gpu { 933 polling-delay-passive = <1000>; 934 polling-delay = <0>; 935 936 thermal-sensors = 937 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 938 939 trips { 940 gpu_shutdown_trip { 941 temperature = <101000>; 942 hysteresis = <1000>; 943 type = "critical"; 944 }; 945 946 gpu_throttle_trip: throttle-trip { 947 temperature = <99000>; 948 hysteresis = <1000>; 949 type = "hot"; 950 }; 951 }; 952 953 cooling-maps { 954 map0 { 955 trip = <&gpu_throttle_trip>; 956 cooling-device = <&throttle_heavy 1 1>; 957 }; 958 }; 959 }; 960 pllx { 961 polling-delay-passive = <0>; 962 polling-delay = <0>; 963 964 thermal-sensors = 965 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 966 967 trips { 968 pllx_shutdown_trip { 969 temperature = <105000>; 970 hysteresis = <1000>; 971 type = "critical"; 972 }; 973 }; 974 975 cooling-maps { 976 /* 977 * There are currently no cooling maps, 978 * because there are no cooling devices. 979 */ 980 }; 981 }; 982 }; 983 984 ahub@70300000 { 985 compatible = "nvidia,tegra124-ahub"; 986 reg = <0x0 0x70300000 0x0 0x200>, 987 <0x0 0x70300800 0x0 0x800>, 988 <0x0 0x70300200 0x0 0x600>; 989 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 991 <&tegra_car TEGRA124_CLK_APBIF>; 992 clock-names = "d_audio", "apbif"; 993 resets = <&tegra_car 106>, /* d_audio */ 994 <&tegra_car 107>, /* apbif */ 995 <&tegra_car 30>, /* i2s0 */ 996 <&tegra_car 11>, /* i2s1 */ 997 <&tegra_car 18>, /* i2s2 */ 998 <&tegra_car 101>, /* i2s3 */ 999 <&tegra_car 102>, /* i2s4 */ 1000 <&tegra_car 108>, /* dam0 */ 1001 <&tegra_car 109>, /* dam1 */ 1002 <&tegra_car 110>, /* dam2 */ 1003 <&tegra_car 10>, /* spdif */ 1004 <&tegra_car 153>, /* amx */ 1005 <&tegra_car 185>, /* amx1 */ 1006 <&tegra_car 154>, /* adx */ 1007 <&tegra_car 180>, /* adx1 */ 1008 <&tegra_car 186>, /* afc0 */ 1009 <&tegra_car 187>, /* afc1 */ 1010 <&tegra_car 188>, /* afc2 */ 1011 <&tegra_car 189>, /* afc3 */ 1012 <&tegra_car 190>, /* afc4 */ 1013 <&tegra_car 191>; /* afc5 */ 1014 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 1015 "i2s3", "i2s4", "dam0", "dam1", "dam2", 1016 "spdif", "amx", "amx1", "adx", "adx1", 1017 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 1018 dmas = <&apbdma 1>, <&apbdma 1>, 1019 <&apbdma 2>, <&apbdma 2>, 1020 <&apbdma 3>, <&apbdma 3>, 1021 <&apbdma 4>, <&apbdma 4>, 1022 <&apbdma 6>, <&apbdma 6>, 1023 <&apbdma 7>, <&apbdma 7>, 1024 <&apbdma 12>, <&apbdma 12>, 1025 <&apbdma 13>, <&apbdma 13>, 1026 <&apbdma 14>, <&apbdma 14>, 1027 <&apbdma 29>, <&apbdma 29>; 1028 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1029 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 1030 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 1031 "rx9", "tx9"; 1032 ranges; 1033 #address-cells = <2>; 1034 #size-cells = <2>; 1035 1036 tegra_i2s0: i2s@70301000 { 1037 compatible = "nvidia,tegra124-i2s"; 1038 reg = <0x0 0x70301000 0x0 0x100>; 1039 nvidia,ahub-cif-ids = <4 4>; 1040 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 1041 clock-names = "i2s"; 1042 resets = <&tegra_car 30>; 1043 reset-names = "i2s"; 1044 status = "disabled"; 1045 }; 1046 1047 tegra_i2s1: i2s@70301100 { 1048 compatible = "nvidia,tegra124-i2s"; 1049 reg = <0x0 0x70301100 0x0 0x100>; 1050 nvidia,ahub-cif-ids = <5 5>; 1051 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 1052 clock-names = "i2s"; 1053 resets = <&tegra_car 11>; 1054 reset-names = "i2s"; 1055 status = "disabled"; 1056 }; 1057 1058 tegra_i2s2: i2s@70301200 { 1059 compatible = "nvidia,tegra124-i2s"; 1060 reg = <0x0 0x70301200 0x0 0x100>; 1061 nvidia,ahub-cif-ids = <6 6>; 1062 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 1063 clock-names = "i2s"; 1064 resets = <&tegra_car 18>; 1065 reset-names = "i2s"; 1066 status = "disabled"; 1067 }; 1068 1069 tegra_i2s3: i2s@70301300 { 1070 compatible = "nvidia,tegra124-i2s"; 1071 reg = <0x0 0x70301300 0x0 0x100>; 1072 nvidia,ahub-cif-ids = <7 7>; 1073 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 1074 clock-names = "i2s"; 1075 resets = <&tegra_car 101>; 1076 reset-names = "i2s"; 1077 status = "disabled"; 1078 }; 1079 1080 tegra_i2s4: i2s@70301400 { 1081 compatible = "nvidia,tegra124-i2s"; 1082 reg = <0x0 0x70301400 0x0 0x100>; 1083 nvidia,ahub-cif-ids = <8 8>; 1084 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 1085 clock-names = "i2s"; 1086 resets = <&tegra_car 102>; 1087 reset-names = "i2s"; 1088 status = "disabled"; 1089 }; 1090 }; 1091 1092 usb@7d000000 { 1093 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1094 reg = <0x0 0x7d000000 0x0 0x4000>; 1095 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1096 phy_type = "utmi"; 1097 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1098 clock-names = "usb"; 1099 resets = <&tegra_car 22>; 1100 reset-names = "usb"; 1101 nvidia,phy = <&phy1>; 1102 status = "disabled"; 1103 }; 1104 1105 phy1: usb-phy@7d000000 { 1106 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1107 reg = <0x0 0x7d000000 0x0 0x4000>, 1108 <0x0 0x7d000000 0x0 0x4000>; 1109 phy_type = "utmi"; 1110 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1111 <&tegra_car TEGRA124_CLK_PLL_U>, 1112 <&tegra_car TEGRA124_CLK_USBD>; 1113 clock-names = "reg", "pll_u", "utmi-pads"; 1114 resets = <&tegra_car 22>, <&tegra_car 22>; 1115 reset-names = "usb", "utmi-pads"; 1116 #phy-cells = <0>; 1117 nvidia,hssync-start-delay = <0>; 1118 nvidia,idle-wait-delay = <17>; 1119 nvidia,elastic-limit = <16>; 1120 nvidia,term-range-adj = <6>; 1121 nvidia,xcvr-setup = <9>; 1122 nvidia,xcvr-lsfslew = <0>; 1123 nvidia,xcvr-lsrslew = <3>; 1124 nvidia,hssquelch-level = <2>; 1125 nvidia,hsdiscon-level = <5>; 1126 nvidia,xcvr-hsslew = <12>; 1127 nvidia,has-utmi-pad-registers; 1128 status = "disabled"; 1129 }; 1130 1131 usb@7d004000 { 1132 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1133 reg = <0x0 0x7d004000 0x0 0x4000>; 1134 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1135 phy_type = "utmi"; 1136 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1137 clock-names = "usb"; 1138 resets = <&tegra_car 58>; 1139 reset-names = "usb"; 1140 nvidia,phy = <&phy2>; 1141 status = "disabled"; 1142 }; 1143 1144 phy2: usb-phy@7d004000 { 1145 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1146 reg = <0x0 0x7d004000 0x0 0x4000>, 1147 <0x0 0x7d000000 0x0 0x4000>; 1148 phy_type = "utmi"; 1149 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1150 <&tegra_car TEGRA124_CLK_PLL_U>, 1151 <&tegra_car TEGRA124_CLK_USBD>; 1152 clock-names = "reg", "pll_u", "utmi-pads"; 1153 resets = <&tegra_car 58>, <&tegra_car 22>; 1154 reset-names = "usb", "utmi-pads"; 1155 #phy-cells = <0>; 1156 nvidia,hssync-start-delay = <0>; 1157 nvidia,idle-wait-delay = <17>; 1158 nvidia,elastic-limit = <16>; 1159 nvidia,term-range-adj = <6>; 1160 nvidia,xcvr-setup = <9>; 1161 nvidia,xcvr-lsfslew = <0>; 1162 nvidia,xcvr-lsrslew = <3>; 1163 nvidia,hssquelch-level = <2>; 1164 nvidia,hsdiscon-level = <5>; 1165 nvidia,xcvr-hsslew = <12>; 1166 status = "disabled"; 1167 }; 1168 1169 usb@7d008000 { 1170 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1171 reg = <0x0 0x7d008000 0x0 0x4000>; 1172 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1173 phy_type = "utmi"; 1174 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1175 clock-names = "usb"; 1176 resets = <&tegra_car 59>; 1177 reset-names = "usb"; 1178 nvidia,phy = <&phy3>; 1179 status = "disabled"; 1180 }; 1181 1182 phy3: usb-phy@7d008000 { 1183 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1184 reg = <0x0 0x7d008000 0x0 0x4000>, 1185 <0x0 0x7d000000 0x0 0x4000>; 1186 phy_type = "utmi"; 1187 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1188 <&tegra_car TEGRA124_CLK_PLL_U>, 1189 <&tegra_car TEGRA124_CLK_USBD>; 1190 clock-names = "reg", "pll_u", "utmi-pads"; 1191 resets = <&tegra_car 59>, <&tegra_car 22>; 1192 reset-names = "usb", "utmi-pads"; 1193 #phy-cells = <0>; 1194 nvidia,hssync-start-delay = <0>; 1195 nvidia,idle-wait-delay = <17>; 1196 nvidia,elastic-limit = <16>; 1197 nvidia,term-range-adj = <6>; 1198 nvidia,xcvr-setup = <9>; 1199 nvidia,xcvr-lsfslew = <0>; 1200 nvidia,xcvr-lsrslew = <3>; 1201 nvidia,hssquelch-level = <2>; 1202 nvidia,hsdiscon-level = <5>; 1203 nvidia,xcvr-hsslew = <12>; 1204 status = "disabled"; 1205 }; 1206 1207 cpus { 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 1211 cpu@0 { 1212 device_type = "cpu"; 1213 compatible = "nvidia,denver"; 1214 reg = <0>; 1215 }; 1216 1217 cpu@1 { 1218 device_type = "cpu"; 1219 compatible = "nvidia,denver"; 1220 reg = <1>; 1221 }; 1222 }; 1223 1224 timer { 1225 compatible = "arm,armv7-timer"; 1226 interrupts = <GIC_PPI 13 1227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1228 <GIC_PPI 14 1229 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1230 <GIC_PPI 11 1231 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1232 <GIC_PPI 10 1233 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1234 interrupt-parent = <&gic>; 1235 }; 1236}; 1237