1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11/ { 12 compatible = "nvidia,tegra132", "nvidia,tegra124"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra124-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 43 <&tegra_car TEGRA124_CLK_AFI>, 44 <&tegra_car TEGRA124_CLK_PLL_E>, 45 <&tegra_car TEGRA124_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 54 phy-names = "pcie"; 55 56 pci@1,0 { 57 device_type = "pci"; 58 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 59 reg = <0x000800 0 0 0 0>; 60 bus-range = <0x00 0xff>; 61 status = "disabled"; 62 63 #address-cells = <3>; 64 #size-cells = <2>; 65 ranges; 66 67 nvidia,num-lanes = <2>; 68 }; 69 70 pci@2,0 { 71 device_type = "pci"; 72 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 73 reg = <0x001000 0 0 0 0>; 74 bus-range = <0x00 0xff>; 75 status = "disabled"; 76 77 #address-cells = <3>; 78 #size-cells = <2>; 79 ranges; 80 81 nvidia,num-lanes = <1>; 82 }; 83 }; 84 85 host1x@50000000 { 86 compatible = "nvidia,tegra124-host1x", "simple-bus"; 87 reg = <0x0 0x50000000 0x0 0x00034000>; 88 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 89 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 90 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 91 clock-names = "host1x"; 92 resets = <&tegra_car 28>; 93 reset-names = "host1x"; 94 95 #address-cells = <2>; 96 #size-cells = <2>; 97 98 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 99 100 dc@54200000 { 101 compatible = "nvidia,tegra124-dc"; 102 reg = <0x0 0x54200000 0x0 0x00040000>; 103 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 104 clocks = <&tegra_car TEGRA124_CLK_DISP1>, 105 <&tegra_car TEGRA124_CLK_PLL_P>; 106 clock-names = "dc", "parent"; 107 resets = <&tegra_car 27>; 108 reset-names = "dc"; 109 110 iommus = <&mc TEGRA_SWGROUP_DC>; 111 112 nvidia,head = <0>; 113 }; 114 115 dc@54240000 { 116 compatible = "nvidia,tegra124-dc"; 117 reg = <0x0 0x54240000 0x0 0x00040000>; 118 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&tegra_car TEGRA124_CLK_DISP2>, 120 <&tegra_car TEGRA124_CLK_PLL_P>; 121 clock-names = "dc", "parent"; 122 resets = <&tegra_car 26>; 123 reset-names = "dc"; 124 125 iommus = <&mc TEGRA_SWGROUP_DCB>; 126 127 nvidia,head = <1>; 128 }; 129 130 hdmi@54280000 { 131 compatible = "nvidia,tegra124-hdmi"; 132 reg = <0x0 0x54280000 0x0 0x00040000>; 133 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 135 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 136 clock-names = "hdmi", "parent"; 137 resets = <&tegra_car 51>; 138 reset-names = "hdmi"; 139 status = "disabled"; 140 }; 141 142 sor@54540000 { 143 compatible = "nvidia,tegra124-sor"; 144 reg = <0x0 0x54540000 0x0 0x00040000>; 145 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 147 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 148 <&tegra_car TEGRA124_CLK_PLL_DP>, 149 <&tegra_car TEGRA124_CLK_CLK_M>; 150 clock-names = "sor", "parent", "dp", "safe"; 151 resets = <&tegra_car 182>; 152 reset-names = "sor"; 153 status = "disabled"; 154 }; 155 156 dpaux: dpaux@545c0000 { 157 compatible = "nvidia,tegra124-dpaux"; 158 reg = <0x0 0x545c0000 0x0 0x00040000>; 159 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 161 <&tegra_car TEGRA124_CLK_PLL_DP>; 162 clock-names = "dpaux", "parent"; 163 resets = <&tegra_car 181>; 164 reset-names = "dpaux"; 165 status = "disabled"; 166 }; 167 }; 168 169 gic: interrupt-controller@50041000 { 170 compatible = "arm,cortex-a15-gic"; 171 #interrupt-cells = <3>; 172 interrupt-controller; 173 reg = <0x0 0x50041000 0x0 0x1000>, 174 <0x0 0x50042000 0x0 0x2000>, 175 <0x0 0x50044000 0x0 0x2000>, 176 <0x0 0x50046000 0x0 0x2000>; 177 interrupts = <GIC_PPI 9 178 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 179 interrupt-parent = <&gic>; 180 }; 181 182 gpu@57000000 { 183 compatible = "nvidia,gk20a"; 184 reg = <0x0 0x57000000 0x0 0x01000000>, 185 <0x0 0x58000000 0x0 0x01000000>; 186 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 188 interrupt-names = "stall", "nonstall"; 189 clocks = <&tegra_car TEGRA124_CLK_GPU>, 190 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 191 clock-names = "gpu", "pwr"; 192 resets = <&tegra_car 184>; 193 reset-names = "gpu"; 194 status = "disabled"; 195 }; 196 197 lic: interrupt-controller@60004000 { 198 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 199 reg = <0x0 0x60004000 0x0 0x100>, 200 <0x0 0x60004100 0x0 0x100>, 201 <0x0 0x60004200 0x0 0x100>, 202 <0x0 0x60004300 0x0 0x100>, 203 <0x0 0x60004400 0x0 0x100>; 204 interrupt-controller; 205 #interrupt-cells = <3>; 206 interrupt-parent = <&gic>; 207 }; 208 209 timer@60005000 { 210 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 211 reg = <0x0 0x60005000 0x0 0x400>; 212 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 219 clock-names = "timer"; 220 }; 221 222 tegra_car: clock@60006000 { 223 compatible = "nvidia,tegra132-car"; 224 reg = <0x0 0x60006000 0x0 0x1000>; 225 #clock-cells = <1>; 226 #reset-cells = <1>; 227 nvidia,external-memory-controller = <&emc>; 228 }; 229 230 flow-controller@60007000 { 231 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 232 reg = <0x0 0x60007000 0x0 0x1000>; 233 }; 234 235 actmon@6000c800 { 236 compatible = "nvidia,tegra124-actmon"; 237 reg = <0x0 0x6000c800 0x0 0x400>; 238 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 240 <&tegra_car TEGRA124_CLK_EMC>; 241 clock-names = "actmon", "emc"; 242 resets = <&tegra_car 119>; 243 reset-names = "actmon"; 244 }; 245 246 gpio: gpio@6000d000 { 247 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 248 reg = <0x0 0x6000d000 0x0 0x1000>; 249 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 257 #gpio-cells = <2>; 258 gpio-controller; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 }; 262 263 apbdma: dma@60020000 { 264 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 265 reg = <0x0 0x60020000 0x0 0x1400>; 266 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 299 clock-names = "dma"; 300 resets = <&tegra_car 34>; 301 reset-names = "dma"; 302 #dma-cells = <1>; 303 }; 304 305 apbmisc@70000800 { 306 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 307 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 308 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 309 }; 310 311 pinmux: pinmux@70000868 { 312 compatible = "nvidia,tegra124-pinmux"; 313 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 314 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 315 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 316 }; 317 318 /* 319 * There are two serial driver i.e. 8250 based simple serial 320 * driver and APB DMA based serial driver for higher baudrate 321 * and performance. To enable the 8250 based driver, the compatible 322 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 323 * the APB DMA based serial driver, the compatible is 324 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 325 */ 326 uarta: serial@70006000 { 327 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 328 reg = <0x0 0x70006000 0x0 0x40>; 329 reg-shift = <2>; 330 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 332 clock-names = "serial"; 333 resets = <&tegra_car 6>; 334 reset-names = "serial"; 335 dmas = <&apbdma 8>, <&apbdma 8>; 336 dma-names = "rx", "tx"; 337 status = "disabled"; 338 }; 339 340 uartb: serial@70006040 { 341 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 342 reg = <0x0 0x70006040 0x0 0x40>; 343 reg-shift = <2>; 344 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 346 clock-names = "serial"; 347 resets = <&tegra_car 7>; 348 reset-names = "serial"; 349 dmas = <&apbdma 9>, <&apbdma 9>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 uartc: serial@70006200 { 355 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 356 reg = <0x0 0x70006200 0x0 0x40>; 357 reg-shift = <2>; 358 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 360 clock-names = "serial"; 361 resets = <&tegra_car 55>; 362 reset-names = "serial"; 363 dmas = <&apbdma 10>, <&apbdma 10>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 uartd: serial@70006300 { 369 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 370 reg = <0x0 0x70006300 0x0 0x40>; 371 reg-shift = <2>; 372 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 374 clock-names = "serial"; 375 resets = <&tegra_car 65>; 376 reset-names = "serial"; 377 dmas = <&apbdma 19>, <&apbdma 19>; 378 dma-names = "rx", "tx"; 379 status = "disabled"; 380 }; 381 382 pwm: pwm@7000a000 { 383 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 384 reg = <0x0 0x7000a000 0x0 0x100>; 385 #pwm-cells = <2>; 386 clocks = <&tegra_car TEGRA124_CLK_PWM>; 387 clock-names = "pwm"; 388 resets = <&tegra_car 17>; 389 reset-names = "pwm"; 390 status = "disabled"; 391 }; 392 393 i2c@7000c000 { 394 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 395 reg = <0x0 0x7000c000 0x0 0x100>; 396 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 400 clock-names = "div-clk"; 401 resets = <&tegra_car 12>; 402 reset-names = "i2c"; 403 dmas = <&apbdma 21>, <&apbdma 21>; 404 dma-names = "rx", "tx"; 405 status = "disabled"; 406 }; 407 408 i2c@7000c400 { 409 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 410 reg = <0x0 0x7000c400 0x0 0x100>; 411 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 415 clock-names = "div-clk"; 416 resets = <&tegra_car 54>; 417 reset-names = "i2c"; 418 dmas = <&apbdma 22>, <&apbdma 22>; 419 dma-names = "rx", "tx"; 420 status = "disabled"; 421 }; 422 423 i2c@7000c500 { 424 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 425 reg = <0x0 0x7000c500 0x0 0x100>; 426 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 430 clock-names = "div-clk"; 431 resets = <&tegra_car 67>; 432 reset-names = "i2c"; 433 dmas = <&apbdma 23>, <&apbdma 23>; 434 dma-names = "rx", "tx"; 435 status = "disabled"; 436 }; 437 438 i2c@7000c700 { 439 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 440 reg = <0x0 0x7000c700 0x0 0x100>; 441 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 445 clock-names = "div-clk"; 446 resets = <&tegra_car 103>; 447 reset-names = "i2c"; 448 dmas = <&apbdma 26>, <&apbdma 26>; 449 dma-names = "rx", "tx"; 450 status = "disabled"; 451 }; 452 453 i2c@7000d000 { 454 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 455 reg = <0x0 0x7000d000 0x0 0x100>; 456 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 460 clock-names = "div-clk"; 461 resets = <&tegra_car 47>; 462 reset-names = "i2c"; 463 dmas = <&apbdma 24>, <&apbdma 24>; 464 dma-names = "rx", "tx"; 465 status = "disabled"; 466 }; 467 468 i2c@7000d100 { 469 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 470 reg = <0x0 0x7000d100 0x0 0x100>; 471 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 475 clock-names = "div-clk"; 476 resets = <&tegra_car 166>; 477 reset-names = "i2c"; 478 dmas = <&apbdma 30>, <&apbdma 30>; 479 dma-names = "rx", "tx"; 480 status = "disabled"; 481 }; 482 483 spi@7000d400 { 484 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 485 reg = <0x0 0x7000d400 0x0 0x200>; 486 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 490 clock-names = "spi"; 491 resets = <&tegra_car 41>; 492 reset-names = "spi"; 493 dmas = <&apbdma 15>, <&apbdma 15>; 494 dma-names = "rx", "tx"; 495 status = "disabled"; 496 }; 497 498 spi@7000d600 { 499 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 500 reg = <0x0 0x7000d600 0x0 0x200>; 501 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 505 clock-names = "spi"; 506 resets = <&tegra_car 44>; 507 reset-names = "spi"; 508 dmas = <&apbdma 16>, <&apbdma 16>; 509 dma-names = "rx", "tx"; 510 status = "disabled"; 511 }; 512 513 spi@7000d800 { 514 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 515 reg = <0x0 0x7000d800 0x0 0x200>; 516 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 520 clock-names = "spi"; 521 resets = <&tegra_car 46>; 522 reset-names = "spi"; 523 dmas = <&apbdma 17>, <&apbdma 17>; 524 dma-names = "rx", "tx"; 525 status = "disabled"; 526 }; 527 528 spi@7000da00 { 529 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 530 reg = <0x0 0x7000da00 0x0 0x200>; 531 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 535 clock-names = "spi"; 536 resets = <&tegra_car 68>; 537 reset-names = "spi"; 538 dmas = <&apbdma 18>, <&apbdma 18>; 539 dma-names = "rx", "tx"; 540 status = "disabled"; 541 }; 542 543 spi@7000dc00 { 544 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 545 reg = <0x0 0x7000dc00 0x0 0x200>; 546 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 550 clock-names = "spi"; 551 resets = <&tegra_car 104>; 552 reset-names = "spi"; 553 dmas = <&apbdma 27>, <&apbdma 27>; 554 dma-names = "rx", "tx"; 555 status = "disabled"; 556 }; 557 558 spi@7000de00 { 559 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 560 reg = <0x0 0x7000de00 0x0 0x200>; 561 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 565 clock-names = "spi"; 566 resets = <&tegra_car 105>; 567 reset-names = "spi"; 568 dmas = <&apbdma 28>, <&apbdma 28>; 569 dma-names = "rx", "tx"; 570 status = "disabled"; 571 }; 572 573 rtc@7000e000 { 574 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 575 reg = <0x0 0x7000e000 0x0 0x100>; 576 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&tegra_car TEGRA124_CLK_RTC>; 578 clock-names = "rtc"; 579 }; 580 581 tegra_pmc: pmc@7000e400 { 582 compatible = "nvidia,tegra124-pmc"; 583 reg = <0x0 0x7000e400 0x0 0x400>; 584 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 585 clock-names = "pclk", "clk32k_in"; 586 #clock-cells = <1>; 587 }; 588 589 fuse@7000f800 { 590 compatible = "nvidia,tegra124-efuse"; 591 reg = <0x0 0x7000f800 0x0 0x400>; 592 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 593 clock-names = "fuse"; 594 resets = <&tegra_car 39>; 595 reset-names = "fuse"; 596 }; 597 598 mc: memory-controller@70019000 { 599 compatible = "nvidia,tegra132-mc"; 600 reg = <0x0 0x70019000 0x0 0x1000>; 601 clocks = <&tegra_car TEGRA124_CLK_MC>; 602 clock-names = "mc"; 603 604 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 605 606 #iommu-cells = <1>; 607 }; 608 609 emc: external-memory-controller@7001b000 { 610 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 611 reg = <0x0 0x7001b000 0x0 0x1000>; 612 clocks = <&tegra_car TEGRA124_CLK_EMC>; 613 clock-names = "emc"; 614 615 nvidia,memory-controller = <&mc>; 616 }; 617 618 sata@70020000 { 619 compatible = "nvidia,tegra124-ahci"; 620 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 621 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 622 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&tegra_car TEGRA124_CLK_SATA>, 624 <&tegra_car TEGRA124_CLK_SATA_OOB>, 625 <&tegra_car TEGRA124_CLK_CML1>, 626 <&tegra_car TEGRA124_CLK_PLL_E>; 627 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 628 resets = <&tegra_car 124>, 629 <&tegra_car 123>, 630 <&tegra_car 129>; 631 reset-names = "sata", "sata-oob", "sata-cold"; 632 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 633 phy-names = "sata-phy"; 634 status = "disabled"; 635 }; 636 637 hda@70030000 { 638 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 639 "nvidia,tegra30-hda"; 640 reg = <0x0 0x70030000 0x0 0x10000>; 641 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&tegra_car TEGRA124_CLK_HDA>, 643 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 644 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 645 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 646 resets = <&tegra_car 125>, /* hda */ 647 <&tegra_car 128>, /* hda2hdmi */ 648 <&tegra_car 111>; /* hda2codec_2x */ 649 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 650 status = "disabled"; 651 }; 652 653 padctl: padctl@7009f000 { 654 compatible = "nvidia,tegra132-xusb-padctl", 655 "nvidia,tegra124-xusb-padctl"; 656 reg = <0x0 0x7009f000 0x0 0x1000>; 657 resets = <&tegra_car 142>; 658 reset-names = "padctl"; 659 660 #phy-cells = <1>; 661 662 phys { 663 pcie-0 { 664 status = "disabled"; 665 }; 666 667 sata-0 { 668 status = "disabled"; 669 }; 670 671 usb3-0 { 672 status = "disabled"; 673 }; 674 675 usb3-1 { 676 status = "disabled"; 677 }; 678 679 utmi-0 { 680 status = "disabled"; 681 }; 682 683 utmi-1 { 684 status = "disabled"; 685 }; 686 687 utmi-2 { 688 status = "disabled"; 689 }; 690 }; 691 }; 692 693 sdhci@700b0000 { 694 compatible = "nvidia,tegra124-sdhci"; 695 reg = <0x0 0x700b0000 0x0 0x200>; 696 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 698 clock-names = "sdhci"; 699 resets = <&tegra_car 14>; 700 reset-names = "sdhci"; 701 status = "disabled"; 702 }; 703 704 sdhci@700b0200 { 705 compatible = "nvidia,tegra124-sdhci"; 706 reg = <0x0 0x700b0200 0x0 0x200>; 707 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 709 clock-names = "sdhci"; 710 resets = <&tegra_car 9>; 711 reset-names = "sdhci"; 712 status = "disabled"; 713 }; 714 715 sdhci@700b0400 { 716 compatible = "nvidia,tegra124-sdhci"; 717 reg = <0x0 0x700b0400 0x0 0x200>; 718 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 720 clock-names = "sdhci"; 721 resets = <&tegra_car 69>; 722 reset-names = "sdhci"; 723 status = "disabled"; 724 }; 725 726 sdhci@700b0600 { 727 compatible = "nvidia,tegra124-sdhci"; 728 reg = <0x0 0x700b0600 0x0 0x200>; 729 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 731 clock-names = "sdhci"; 732 resets = <&tegra_car 15>; 733 reset-names = "sdhci"; 734 status = "disabled"; 735 }; 736 737 soctherm: thermal-sensor@700e2000 { 738 compatible = "nvidia,tegra132-soctherm"; 739 reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */ 740 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 741 reg-names = "soctherm-reg", "ccroc-reg"; 742 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 744 <&tegra_car TEGRA124_CLK_SOC_THERM>; 745 clock-names = "tsensor", "soctherm"; 746 resets = <&tegra_car 78>; 747 reset-names = "soctherm"; 748 #thermal-sensor-cells = <1>; 749 750 throttle-cfgs { 751 throttle_heavy: heavy { 752 nvidia,priority = <100>; 753 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 754 755 #cooling-cells = <2>; 756 }; 757 }; 758 }; 759 760 thermal-zones { 761 cpu { 762 polling-delay-passive = <1000>; 763 polling-delay = <0>; 764 765 thermal-sensors = 766 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 767 768 trips { 769 cpu_shutdown_trip { 770 temperature = <105000>; 771 hysteresis = <1000>; 772 type = "critical"; 773 }; 774 775 cpu_throttle_trip: throttle-trip { 776 temperature = <102000>; 777 hysteresis = <1000>; 778 type = "hot"; 779 }; 780 }; 781 782 cooling-maps { 783 map0 { 784 trip = <&cpu_throttle_trip>; 785 cooling-device = <&throttle_heavy 1 1>; 786 }; 787 }; 788 }; 789 mem { 790 polling-delay-passive = <0>; 791 polling-delay = <0>; 792 793 thermal-sensors = 794 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 795 796 trips { 797 mem_shutdown_trip { 798 temperature = <101000>; 799 hysteresis = <1000>; 800 type = "critical"; 801 }; 802 }; 803 804 cooling-maps { 805 /* 806 * There are currently no cooling maps, 807 * because there are no cooling devices. 808 */ 809 }; 810 }; 811 gpu { 812 polling-delay-passive = <1000>; 813 polling-delay = <0>; 814 815 thermal-sensors = 816 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 817 818 trips { 819 gpu_shutdown_trip { 820 temperature = <101000>; 821 hysteresis = <1000>; 822 type = "critical"; 823 }; 824 825 gpu_throttle_trip: throttle-trip { 826 temperature = <99000>; 827 hysteresis = <1000>; 828 type = "hot"; 829 }; 830 }; 831 832 cooling-maps { 833 map0 { 834 trip = <&gpu_throttle_trip>; 835 cooling-device = <&throttle_heavy 1 1>; 836 }; 837 }; 838 }; 839 pllx { 840 polling-delay-passive = <0>; 841 polling-delay = <0>; 842 843 thermal-sensors = 844 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 845 846 trips { 847 pllx_shutdown_trip { 848 temperature = <105000>; 849 hysteresis = <1000>; 850 type = "critical"; 851 }; 852 }; 853 854 cooling-maps { 855 /* 856 * There are currently no cooling maps, 857 * because there are no cooling devices. 858 */ 859 }; 860 }; 861 }; 862 863 ahub@70300000 { 864 compatible = "nvidia,tegra124-ahub"; 865 reg = <0x0 0x70300000 0x0 0x200>, 866 <0x0 0x70300800 0x0 0x800>, 867 <0x0 0x70300200 0x0 0x600>; 868 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 870 <&tegra_car TEGRA124_CLK_APBIF>; 871 clock-names = "d_audio", "apbif"; 872 resets = <&tegra_car 106>, /* d_audio */ 873 <&tegra_car 107>, /* apbif */ 874 <&tegra_car 30>, /* i2s0 */ 875 <&tegra_car 11>, /* i2s1 */ 876 <&tegra_car 18>, /* i2s2 */ 877 <&tegra_car 101>, /* i2s3 */ 878 <&tegra_car 102>, /* i2s4 */ 879 <&tegra_car 108>, /* dam0 */ 880 <&tegra_car 109>, /* dam1 */ 881 <&tegra_car 110>, /* dam2 */ 882 <&tegra_car 10>, /* spdif */ 883 <&tegra_car 153>, /* amx */ 884 <&tegra_car 185>, /* amx1 */ 885 <&tegra_car 154>, /* adx */ 886 <&tegra_car 180>, /* adx1 */ 887 <&tegra_car 186>, /* afc0 */ 888 <&tegra_car 187>, /* afc1 */ 889 <&tegra_car 188>, /* afc2 */ 890 <&tegra_car 189>, /* afc3 */ 891 <&tegra_car 190>, /* afc4 */ 892 <&tegra_car 191>; /* afc5 */ 893 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 894 "i2s3", "i2s4", "dam0", "dam1", "dam2", 895 "spdif", "amx", "amx1", "adx", "adx1", 896 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 897 dmas = <&apbdma 1>, <&apbdma 1>, 898 <&apbdma 2>, <&apbdma 2>, 899 <&apbdma 3>, <&apbdma 3>, 900 <&apbdma 4>, <&apbdma 4>, 901 <&apbdma 6>, <&apbdma 6>, 902 <&apbdma 7>, <&apbdma 7>, 903 <&apbdma 12>, <&apbdma 12>, 904 <&apbdma 13>, <&apbdma 13>, 905 <&apbdma 14>, <&apbdma 14>, 906 <&apbdma 29>, <&apbdma 29>; 907 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 908 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 909 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 910 "rx9", "tx9"; 911 ranges; 912 #address-cells = <2>; 913 #size-cells = <2>; 914 915 tegra_i2s0: i2s@70301000 { 916 compatible = "nvidia,tegra124-i2s"; 917 reg = <0x0 0x70301000 0x0 0x100>; 918 nvidia,ahub-cif-ids = <4 4>; 919 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 920 clock-names = "i2s"; 921 resets = <&tegra_car 30>; 922 reset-names = "i2s"; 923 status = "disabled"; 924 }; 925 926 tegra_i2s1: i2s@70301100 { 927 compatible = "nvidia,tegra124-i2s"; 928 reg = <0x0 0x70301100 0x0 0x100>; 929 nvidia,ahub-cif-ids = <5 5>; 930 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 931 clock-names = "i2s"; 932 resets = <&tegra_car 11>; 933 reset-names = "i2s"; 934 status = "disabled"; 935 }; 936 937 tegra_i2s2: i2s@70301200 { 938 compatible = "nvidia,tegra124-i2s"; 939 reg = <0x0 0x70301200 0x0 0x100>; 940 nvidia,ahub-cif-ids = <6 6>; 941 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 942 clock-names = "i2s"; 943 resets = <&tegra_car 18>; 944 reset-names = "i2s"; 945 status = "disabled"; 946 }; 947 948 tegra_i2s3: i2s@70301300 { 949 compatible = "nvidia,tegra124-i2s"; 950 reg = <0x0 0x70301300 0x0 0x100>; 951 nvidia,ahub-cif-ids = <7 7>; 952 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 953 clock-names = "i2s"; 954 resets = <&tegra_car 101>; 955 reset-names = "i2s"; 956 status = "disabled"; 957 }; 958 959 tegra_i2s4: i2s@70301400 { 960 compatible = "nvidia,tegra124-i2s"; 961 reg = <0x0 0x70301400 0x0 0x100>; 962 nvidia,ahub-cif-ids = <8 8>; 963 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 964 clock-names = "i2s"; 965 resets = <&tegra_car 102>; 966 reset-names = "i2s"; 967 status = "disabled"; 968 }; 969 }; 970 971 usb@7d000000 { 972 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 973 reg = <0x0 0x7d000000 0x0 0x4000>; 974 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 975 phy_type = "utmi"; 976 clocks = <&tegra_car TEGRA124_CLK_USBD>; 977 clock-names = "usb"; 978 resets = <&tegra_car 22>; 979 reset-names = "usb"; 980 nvidia,phy = <&phy1>; 981 status = "disabled"; 982 }; 983 984 phy1: usb-phy@7d000000 { 985 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 986 reg = <0x0 0x7d000000 0x0 0x4000>, 987 <0x0 0x7d000000 0x0 0x4000>; 988 phy_type = "utmi"; 989 clocks = <&tegra_car TEGRA124_CLK_USBD>, 990 <&tegra_car TEGRA124_CLK_PLL_U>, 991 <&tegra_car TEGRA124_CLK_USBD>; 992 clock-names = "reg", "pll_u", "utmi-pads"; 993 resets = <&tegra_car 22>, <&tegra_car 22>; 994 reset-names = "usb", "utmi-pads"; 995 nvidia,hssync-start-delay = <0>; 996 nvidia,idle-wait-delay = <17>; 997 nvidia,elastic-limit = <16>; 998 nvidia,term-range-adj = <6>; 999 nvidia,xcvr-setup = <9>; 1000 nvidia,xcvr-lsfslew = <0>; 1001 nvidia,xcvr-lsrslew = <3>; 1002 nvidia,hssquelch-level = <2>; 1003 nvidia,hsdiscon-level = <5>; 1004 nvidia,xcvr-hsslew = <12>; 1005 nvidia,has-utmi-pad-registers; 1006 status = "disabled"; 1007 }; 1008 1009 usb@7d004000 { 1010 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1011 reg = <0x0 0x7d004000 0x0 0x4000>; 1012 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1013 phy_type = "utmi"; 1014 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1015 clock-names = "usb"; 1016 resets = <&tegra_car 58>; 1017 reset-names = "usb"; 1018 nvidia,phy = <&phy2>; 1019 status = "disabled"; 1020 }; 1021 1022 phy2: usb-phy@7d004000 { 1023 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1024 reg = <0x0 0x7d004000 0x0 0x4000>, 1025 <0x0 0x7d000000 0x0 0x4000>; 1026 phy_type = "utmi"; 1027 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1028 <&tegra_car TEGRA124_CLK_PLL_U>, 1029 <&tegra_car TEGRA124_CLK_USBD>; 1030 clock-names = "reg", "pll_u", "utmi-pads"; 1031 resets = <&tegra_car 58>, <&tegra_car 22>; 1032 reset-names = "usb", "utmi-pads"; 1033 nvidia,hssync-start-delay = <0>; 1034 nvidia,idle-wait-delay = <17>; 1035 nvidia,elastic-limit = <16>; 1036 nvidia,term-range-adj = <6>; 1037 nvidia,xcvr-setup = <9>; 1038 nvidia,xcvr-lsfslew = <0>; 1039 nvidia,xcvr-lsrslew = <3>; 1040 nvidia,hssquelch-level = <2>; 1041 nvidia,hsdiscon-level = <5>; 1042 nvidia,xcvr-hsslew = <12>; 1043 status = "disabled"; 1044 }; 1045 1046 usb@7d008000 { 1047 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1048 reg = <0x0 0x7d008000 0x0 0x4000>; 1049 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1050 phy_type = "utmi"; 1051 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1052 clock-names = "usb"; 1053 resets = <&tegra_car 59>; 1054 reset-names = "usb"; 1055 nvidia,phy = <&phy3>; 1056 status = "disabled"; 1057 }; 1058 1059 phy3: usb-phy@7d008000 { 1060 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1061 reg = <0x0 0x7d008000 0x0 0x4000>, 1062 <0x0 0x7d000000 0x0 0x4000>; 1063 phy_type = "utmi"; 1064 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1065 <&tegra_car TEGRA124_CLK_PLL_U>, 1066 <&tegra_car TEGRA124_CLK_USBD>; 1067 clock-names = "reg", "pll_u", "utmi-pads"; 1068 resets = <&tegra_car 59>, <&tegra_car 22>; 1069 reset-names = "usb", "utmi-pads"; 1070 nvidia,hssync-start-delay = <0>; 1071 nvidia,idle-wait-delay = <17>; 1072 nvidia,elastic-limit = <16>; 1073 nvidia,term-range-adj = <6>; 1074 nvidia,xcvr-setup = <9>; 1075 nvidia,xcvr-lsfslew = <0>; 1076 nvidia,xcvr-lsrslew = <3>; 1077 nvidia,hssquelch-level = <2>; 1078 nvidia,hsdiscon-level = <5>; 1079 nvidia,xcvr-hsslew = <12>; 1080 status = "disabled"; 1081 }; 1082 1083 cpus { 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 1087 cpu@0 { 1088 device_type = "cpu"; 1089 compatible = "nvidia,denver"; 1090 reg = <0>; 1091 }; 1092 1093 cpu@1 { 1094 device_type = "cpu"; 1095 compatible = "nvidia,denver"; 1096 reg = <1>; 1097 }; 1098 }; 1099 1100 timer { 1101 compatible = "arm,armv7-timer"; 1102 interrupts = <GIC_PPI 13 1103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1104 <GIC_PPI 14 1105 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1106 <GIC_PPI 11 1107 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1108 <GIC_PPI 10 1109 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1110 interrupt-parent = <&gic>; 1111 }; 1112}; 1113