1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11/ { 12 compatible = "nvidia,tegra132", "nvidia,tegra124"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra124-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 43 <&tegra_car TEGRA124_CLK_AFI>, 44 <&tegra_car TEGRA124_CLK_PLL_E>, 45 <&tegra_car TEGRA124_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 54 phy-names = "pcie"; 55 56 pci@1,0 { 57 device_type = "pci"; 58 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 59 reg = <0x000800 0 0 0 0>; 60 bus-range = <0x00 0xff>; 61 status = "disabled"; 62 63 #address-cells = <3>; 64 #size-cells = <2>; 65 ranges; 66 67 nvidia,num-lanes = <2>; 68 }; 69 70 pci@2,0 { 71 device_type = "pci"; 72 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 73 reg = <0x001000 0 0 0 0>; 74 bus-range = <0x00 0xff>; 75 status = "disabled"; 76 77 #address-cells = <3>; 78 #size-cells = <2>; 79 ranges; 80 81 nvidia,num-lanes = <1>; 82 }; 83 }; 84 85 host1x@50000000 { 86 compatible = "nvidia,tegra132-host1x", 87 "nvidia,tegra124-host1x", 88 "simple-bus"; 89 reg = <0x0 0x50000000 0x0 0x00034000>; 90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 91 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 92 interrupt-names = "syncpt", "host1x"; 93 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 94 clock-names = "host1x"; 95 resets = <&tegra_car 28>; 96 reset-names = "host1x"; 97 98 #address-cells = <2>; 99 #size-cells = <2>; 100 101 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 102 103 dc@54200000 { 104 compatible = "nvidia,tegra124-dc"; 105 reg = <0x0 0x54200000 0x0 0x00040000>; 106 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&tegra_car TEGRA124_CLK_DISP1>, 108 <&tegra_car TEGRA124_CLK_PLL_P>; 109 clock-names = "dc", "parent"; 110 resets = <&tegra_car 27>; 111 reset-names = "dc"; 112 113 iommus = <&mc TEGRA_SWGROUP_DC>; 114 115 nvidia,head = <0>; 116 }; 117 118 dc@54240000 { 119 compatible = "nvidia,tegra124-dc"; 120 reg = <0x0 0x54240000 0x0 0x00040000>; 121 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&tegra_car TEGRA124_CLK_DISP2>, 123 <&tegra_car TEGRA124_CLK_PLL_P>; 124 clock-names = "dc", "parent"; 125 resets = <&tegra_car 26>; 126 reset-names = "dc"; 127 128 iommus = <&mc TEGRA_SWGROUP_DCB>; 129 130 nvidia,head = <1>; 131 }; 132 133 hdmi@54280000 { 134 compatible = "nvidia,tegra124-hdmi"; 135 reg = <0x0 0x54280000 0x0 0x00040000>; 136 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 138 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 139 clock-names = "hdmi", "parent"; 140 resets = <&tegra_car 51>; 141 reset-names = "hdmi"; 142 status = "disabled"; 143 }; 144 145 sor@54540000 { 146 compatible = "nvidia,tegra124-sor"; 147 reg = <0x0 0x54540000 0x0 0x00040000>; 148 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 149 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 150 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 151 <&tegra_car TEGRA124_CLK_PLL_DP>, 152 <&tegra_car TEGRA124_CLK_CLK_M>; 153 clock-names = "sor", "parent", "dp", "safe"; 154 resets = <&tegra_car 182>; 155 reset-names = "sor"; 156 status = "disabled"; 157 }; 158 159 dpaux: dpaux@545c0000 { 160 compatible = "nvidia,tegra124-dpaux"; 161 reg = <0x0 0x545c0000 0x0 0x00040000>; 162 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 164 <&tegra_car TEGRA124_CLK_PLL_DP>; 165 clock-names = "dpaux", "parent"; 166 resets = <&tegra_car 181>; 167 reset-names = "dpaux"; 168 status = "disabled"; 169 }; 170 }; 171 172 gic: interrupt-controller@50041000 { 173 compatible = "arm,cortex-a15-gic"; 174 #interrupt-cells = <3>; 175 interrupt-controller; 176 reg = <0x0 0x50041000 0x0 0x1000>, 177 <0x0 0x50042000 0x0 0x2000>, 178 <0x0 0x50044000 0x0 0x2000>, 179 <0x0 0x50046000 0x0 0x2000>; 180 interrupts = <GIC_PPI 9 181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 182 interrupt-parent = <&gic>; 183 }; 184 185 gpu@57000000 { 186 compatible = "nvidia,gk20a"; 187 reg = <0x0 0x57000000 0x0 0x01000000>, 188 <0x0 0x58000000 0x0 0x01000000>; 189 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 191 interrupt-names = "stall", "nonstall"; 192 clocks = <&tegra_car TEGRA124_CLK_GPU>, 193 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 194 clock-names = "gpu", "pwr"; 195 resets = <&tegra_car 184>; 196 reset-names = "gpu"; 197 status = "disabled"; 198 }; 199 200 lic: interrupt-controller@60004000 { 201 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 202 reg = <0x0 0x60004000 0x0 0x100>, 203 <0x0 0x60004100 0x0 0x100>, 204 <0x0 0x60004200 0x0 0x100>, 205 <0x0 0x60004300 0x0 0x100>, 206 <0x0 0x60004400 0x0 0x100>; 207 interrupt-controller; 208 #interrupt-cells = <3>; 209 interrupt-parent = <&gic>; 210 }; 211 212 timer@60005000 { 213 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 214 reg = <0x0 0x60005000 0x0 0x400>; 215 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 222 clock-names = "timer"; 223 }; 224 225 tegra_car: clock@60006000 { 226 compatible = "nvidia,tegra132-car"; 227 reg = <0x0 0x60006000 0x0 0x1000>; 228 #clock-cells = <1>; 229 #reset-cells = <1>; 230 nvidia,external-memory-controller = <&emc>; 231 }; 232 233 flow-controller@60007000 { 234 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 235 reg = <0x0 0x60007000 0x0 0x1000>; 236 }; 237 238 actmon@6000c800 { 239 compatible = "nvidia,tegra124-actmon"; 240 reg = <0x0 0x6000c800 0x0 0x400>; 241 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 243 <&tegra_car TEGRA124_CLK_EMC>; 244 clock-names = "actmon", "emc"; 245 resets = <&tegra_car 119>; 246 reset-names = "actmon"; 247 }; 248 249 gpio: gpio@6000d000 { 250 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 251 reg = <0x0 0x6000d000 0x0 0x1000>; 252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 260 #gpio-cells = <2>; 261 gpio-controller; 262 #interrupt-cells = <2>; 263 interrupt-controller; 264 }; 265 266 apbdma: dma@60020000 { 267 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 268 reg = <0x0 0x60020000 0x0 0x1400>; 269 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 302 clock-names = "dma"; 303 resets = <&tegra_car 34>; 304 reset-names = "dma"; 305 #dma-cells = <1>; 306 }; 307 308 apbmisc@70000800 { 309 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 310 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 311 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 312 }; 313 314 pinmux: pinmux@70000868 { 315 compatible = "nvidia,tegra124-pinmux"; 316 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 317 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 318 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 319 }; 320 321 /* 322 * There are two serial driver i.e. 8250 based simple serial 323 * driver and APB DMA based serial driver for higher baudrate 324 * and performance. To enable the 8250 based driver, the compatible 325 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 326 * the APB DMA based serial driver, the compatible is 327 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 328 */ 329 uarta: serial@70006000 { 330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 331 reg = <0x0 0x70006000 0x0 0x40>; 332 reg-shift = <2>; 333 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 335 clock-names = "serial"; 336 resets = <&tegra_car 6>; 337 reset-names = "serial"; 338 dmas = <&apbdma 8>, <&apbdma 8>; 339 dma-names = "rx", "tx"; 340 status = "disabled"; 341 }; 342 343 uartb: serial@70006040 { 344 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 345 reg = <0x0 0x70006040 0x0 0x40>; 346 reg-shift = <2>; 347 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 349 clock-names = "serial"; 350 resets = <&tegra_car 7>; 351 reset-names = "serial"; 352 dmas = <&apbdma 9>, <&apbdma 9>; 353 dma-names = "rx", "tx"; 354 status = "disabled"; 355 }; 356 357 uartc: serial@70006200 { 358 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 359 reg = <0x0 0x70006200 0x0 0x40>; 360 reg-shift = <2>; 361 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 363 clock-names = "serial"; 364 resets = <&tegra_car 55>; 365 reset-names = "serial"; 366 dmas = <&apbdma 10>, <&apbdma 10>; 367 dma-names = "rx", "tx"; 368 status = "disabled"; 369 }; 370 371 uartd: serial@70006300 { 372 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 373 reg = <0x0 0x70006300 0x0 0x40>; 374 reg-shift = <2>; 375 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 377 clock-names = "serial"; 378 resets = <&tegra_car 65>; 379 reset-names = "serial"; 380 dmas = <&apbdma 19>, <&apbdma 19>; 381 dma-names = "rx", "tx"; 382 status = "disabled"; 383 }; 384 385 pwm: pwm@7000a000 { 386 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 387 reg = <0x0 0x7000a000 0x0 0x100>; 388 #pwm-cells = <2>; 389 clocks = <&tegra_car TEGRA124_CLK_PWM>; 390 clock-names = "pwm"; 391 resets = <&tegra_car 17>; 392 reset-names = "pwm"; 393 status = "disabled"; 394 }; 395 396 i2c@7000c000 { 397 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 398 reg = <0x0 0x7000c000 0x0 0x100>; 399 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 403 clock-names = "div-clk"; 404 resets = <&tegra_car 12>; 405 reset-names = "i2c"; 406 dmas = <&apbdma 21>, <&apbdma 21>; 407 dma-names = "rx", "tx"; 408 status = "disabled"; 409 }; 410 411 i2c@7000c400 { 412 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 413 reg = <0x0 0x7000c400 0x0 0x100>; 414 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 418 clock-names = "div-clk"; 419 resets = <&tegra_car 54>; 420 reset-names = "i2c"; 421 dmas = <&apbdma 22>, <&apbdma 22>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 426 i2c@7000c500 { 427 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 428 reg = <0x0 0x7000c500 0x0 0x100>; 429 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 433 clock-names = "div-clk"; 434 resets = <&tegra_car 67>; 435 reset-names = "i2c"; 436 dmas = <&apbdma 23>, <&apbdma 23>; 437 dma-names = "rx", "tx"; 438 status = "disabled"; 439 }; 440 441 i2c@7000c700 { 442 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 443 reg = <0x0 0x7000c700 0x0 0x100>; 444 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 448 clock-names = "div-clk"; 449 resets = <&tegra_car 103>; 450 reset-names = "i2c"; 451 dmas = <&apbdma 26>, <&apbdma 26>; 452 dma-names = "rx", "tx"; 453 status = "disabled"; 454 }; 455 456 i2c@7000d000 { 457 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 458 reg = <0x0 0x7000d000 0x0 0x100>; 459 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 463 clock-names = "div-clk"; 464 resets = <&tegra_car 47>; 465 reset-names = "i2c"; 466 dmas = <&apbdma 24>, <&apbdma 24>; 467 dma-names = "rx", "tx"; 468 status = "disabled"; 469 }; 470 471 i2c@7000d100 { 472 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 473 reg = <0x0 0x7000d100 0x0 0x100>; 474 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 478 clock-names = "div-clk"; 479 resets = <&tegra_car 166>; 480 reset-names = "i2c"; 481 dmas = <&apbdma 30>, <&apbdma 30>; 482 dma-names = "rx", "tx"; 483 status = "disabled"; 484 }; 485 486 spi@7000d400 { 487 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 488 reg = <0x0 0x7000d400 0x0 0x200>; 489 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 493 clock-names = "spi"; 494 resets = <&tegra_car 41>; 495 reset-names = "spi"; 496 dmas = <&apbdma 15>, <&apbdma 15>; 497 dma-names = "rx", "tx"; 498 status = "disabled"; 499 }; 500 501 spi@7000d600 { 502 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 503 reg = <0x0 0x7000d600 0x0 0x200>; 504 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 508 clock-names = "spi"; 509 resets = <&tegra_car 44>; 510 reset-names = "spi"; 511 dmas = <&apbdma 16>, <&apbdma 16>; 512 dma-names = "rx", "tx"; 513 status = "disabled"; 514 }; 515 516 spi@7000d800 { 517 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 518 reg = <0x0 0x7000d800 0x0 0x200>; 519 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 523 clock-names = "spi"; 524 resets = <&tegra_car 46>; 525 reset-names = "spi"; 526 dmas = <&apbdma 17>, <&apbdma 17>; 527 dma-names = "rx", "tx"; 528 status = "disabled"; 529 }; 530 531 spi@7000da00 { 532 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 533 reg = <0x0 0x7000da00 0x0 0x200>; 534 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 538 clock-names = "spi"; 539 resets = <&tegra_car 68>; 540 reset-names = "spi"; 541 dmas = <&apbdma 18>, <&apbdma 18>; 542 dma-names = "rx", "tx"; 543 status = "disabled"; 544 }; 545 546 spi@7000dc00 { 547 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 548 reg = <0x0 0x7000dc00 0x0 0x200>; 549 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 553 clock-names = "spi"; 554 resets = <&tegra_car 104>; 555 reset-names = "spi"; 556 dmas = <&apbdma 27>, <&apbdma 27>; 557 dma-names = "rx", "tx"; 558 status = "disabled"; 559 }; 560 561 spi@7000de00 { 562 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 563 reg = <0x0 0x7000de00 0x0 0x200>; 564 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 568 clock-names = "spi"; 569 resets = <&tegra_car 105>; 570 reset-names = "spi"; 571 dmas = <&apbdma 28>, <&apbdma 28>; 572 dma-names = "rx", "tx"; 573 status = "disabled"; 574 }; 575 576 rtc@7000e000 { 577 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 578 reg = <0x0 0x7000e000 0x0 0x100>; 579 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&tegra_car TEGRA124_CLK_RTC>; 581 clock-names = "rtc"; 582 }; 583 584 tegra_pmc: pmc@7000e400 { 585 compatible = "nvidia,tegra124-pmc"; 586 reg = <0x0 0x7000e400 0x0 0x400>; 587 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 588 clock-names = "pclk", "clk32k_in"; 589 #clock-cells = <1>; 590 }; 591 592 fuse@7000f800 { 593 compatible = "nvidia,tegra124-efuse"; 594 reg = <0x0 0x7000f800 0x0 0x400>; 595 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 596 clock-names = "fuse"; 597 resets = <&tegra_car 39>; 598 reset-names = "fuse"; 599 }; 600 601 mc: memory-controller@70019000 { 602 compatible = "nvidia,tegra132-mc"; 603 reg = <0x0 0x70019000 0x0 0x1000>; 604 clocks = <&tegra_car TEGRA124_CLK_MC>; 605 clock-names = "mc"; 606 607 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 608 609 #iommu-cells = <1>; 610 }; 611 612 emc: external-memory-controller@7001b000 { 613 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 614 reg = <0x0 0x7001b000 0x0 0x1000>; 615 clocks = <&tegra_car TEGRA124_CLK_EMC>; 616 clock-names = "emc"; 617 618 nvidia,memory-controller = <&mc>; 619 }; 620 621 sata@70020000 { 622 compatible = "nvidia,tegra124-ahci"; 623 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 624 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 625 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&tegra_car TEGRA124_CLK_SATA>, 627 <&tegra_car TEGRA124_CLK_SATA_OOB>, 628 <&tegra_car TEGRA124_CLK_CML1>, 629 <&tegra_car TEGRA124_CLK_PLL_E>; 630 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 631 resets = <&tegra_car 124>, 632 <&tegra_car 123>, 633 <&tegra_car 129>; 634 reset-names = "sata", "sata-oob", "sata-cold"; 635 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 636 phy-names = "sata-phy"; 637 status = "disabled"; 638 }; 639 640 hda@70030000 { 641 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 642 "nvidia,tegra30-hda"; 643 reg = <0x0 0x70030000 0x0 0x10000>; 644 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&tegra_car TEGRA124_CLK_HDA>, 646 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 647 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 648 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 649 resets = <&tegra_car 125>, /* hda */ 650 <&tegra_car 128>, /* hda2hdmi */ 651 <&tegra_car 111>; /* hda2codec_2x */ 652 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 653 status = "disabled"; 654 }; 655 656 padctl: padctl@7009f000 { 657 compatible = "nvidia,tegra132-xusb-padctl", 658 "nvidia,tegra124-xusb-padctl"; 659 reg = <0x0 0x7009f000 0x0 0x1000>; 660 resets = <&tegra_car 142>; 661 reset-names = "padctl"; 662 663 #phy-cells = <1>; 664 665 phys { 666 pcie-0 { 667 status = "disabled"; 668 }; 669 670 sata-0 { 671 status = "disabled"; 672 }; 673 674 usb3-0 { 675 status = "disabled"; 676 }; 677 678 usb3-1 { 679 status = "disabled"; 680 }; 681 682 utmi-0 { 683 status = "disabled"; 684 }; 685 686 utmi-1 { 687 status = "disabled"; 688 }; 689 690 utmi-2 { 691 status = "disabled"; 692 }; 693 }; 694 }; 695 696 sdhci@700b0000 { 697 compatible = "nvidia,tegra124-sdhci"; 698 reg = <0x0 0x700b0000 0x0 0x200>; 699 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 701 clock-names = "sdhci"; 702 resets = <&tegra_car 14>; 703 reset-names = "sdhci"; 704 status = "disabled"; 705 }; 706 707 sdhci@700b0200 { 708 compatible = "nvidia,tegra124-sdhci"; 709 reg = <0x0 0x700b0200 0x0 0x200>; 710 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 712 clock-names = "sdhci"; 713 resets = <&tegra_car 9>; 714 reset-names = "sdhci"; 715 status = "disabled"; 716 }; 717 718 sdhci@700b0400 { 719 compatible = "nvidia,tegra124-sdhci"; 720 reg = <0x0 0x700b0400 0x0 0x200>; 721 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 723 clock-names = "sdhci"; 724 resets = <&tegra_car 69>; 725 reset-names = "sdhci"; 726 status = "disabled"; 727 }; 728 729 sdhci@700b0600 { 730 compatible = "nvidia,tegra124-sdhci"; 731 reg = <0x0 0x700b0600 0x0 0x200>; 732 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 734 clock-names = "sdhci"; 735 resets = <&tegra_car 15>; 736 reset-names = "sdhci"; 737 status = "disabled"; 738 }; 739 740 soctherm: thermal-sensor@700e2000 { 741 compatible = "nvidia,tegra132-soctherm"; 742 reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */ 743 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 744 reg-names = "soctherm-reg", "ccroc-reg"; 745 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 747 <&tegra_car TEGRA124_CLK_SOC_THERM>; 748 clock-names = "tsensor", "soctherm"; 749 resets = <&tegra_car 78>; 750 reset-names = "soctherm"; 751 #thermal-sensor-cells = <1>; 752 753 throttle-cfgs { 754 throttle_heavy: heavy { 755 nvidia,priority = <100>; 756 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 757 758 #cooling-cells = <2>; 759 }; 760 }; 761 }; 762 763 thermal-zones { 764 cpu { 765 polling-delay-passive = <1000>; 766 polling-delay = <0>; 767 768 thermal-sensors = 769 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 770 771 trips { 772 cpu_shutdown_trip { 773 temperature = <105000>; 774 hysteresis = <1000>; 775 type = "critical"; 776 }; 777 778 cpu_throttle_trip: throttle-trip { 779 temperature = <102000>; 780 hysteresis = <1000>; 781 type = "hot"; 782 }; 783 }; 784 785 cooling-maps { 786 map0 { 787 trip = <&cpu_throttle_trip>; 788 cooling-device = <&throttle_heavy 1 1>; 789 }; 790 }; 791 }; 792 mem { 793 polling-delay-passive = <0>; 794 polling-delay = <0>; 795 796 thermal-sensors = 797 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 798 799 trips { 800 mem_shutdown_trip { 801 temperature = <101000>; 802 hysteresis = <1000>; 803 type = "critical"; 804 }; 805 }; 806 807 cooling-maps { 808 /* 809 * There are currently no cooling maps, 810 * because there are no cooling devices. 811 */ 812 }; 813 }; 814 gpu { 815 polling-delay-passive = <1000>; 816 polling-delay = <0>; 817 818 thermal-sensors = 819 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 820 821 trips { 822 gpu_shutdown_trip { 823 temperature = <101000>; 824 hysteresis = <1000>; 825 type = "critical"; 826 }; 827 828 gpu_throttle_trip: throttle-trip { 829 temperature = <99000>; 830 hysteresis = <1000>; 831 type = "hot"; 832 }; 833 }; 834 835 cooling-maps { 836 map0 { 837 trip = <&gpu_throttle_trip>; 838 cooling-device = <&throttle_heavy 1 1>; 839 }; 840 }; 841 }; 842 pllx { 843 polling-delay-passive = <0>; 844 polling-delay = <0>; 845 846 thermal-sensors = 847 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 848 849 trips { 850 pllx_shutdown_trip { 851 temperature = <105000>; 852 hysteresis = <1000>; 853 type = "critical"; 854 }; 855 }; 856 857 cooling-maps { 858 /* 859 * There are currently no cooling maps, 860 * because there are no cooling devices. 861 */ 862 }; 863 }; 864 }; 865 866 ahub@70300000 { 867 compatible = "nvidia,tegra124-ahub"; 868 reg = <0x0 0x70300000 0x0 0x200>, 869 <0x0 0x70300800 0x0 0x800>, 870 <0x0 0x70300200 0x0 0x600>; 871 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 873 <&tegra_car TEGRA124_CLK_APBIF>; 874 clock-names = "d_audio", "apbif"; 875 resets = <&tegra_car 106>, /* d_audio */ 876 <&tegra_car 107>, /* apbif */ 877 <&tegra_car 30>, /* i2s0 */ 878 <&tegra_car 11>, /* i2s1 */ 879 <&tegra_car 18>, /* i2s2 */ 880 <&tegra_car 101>, /* i2s3 */ 881 <&tegra_car 102>, /* i2s4 */ 882 <&tegra_car 108>, /* dam0 */ 883 <&tegra_car 109>, /* dam1 */ 884 <&tegra_car 110>, /* dam2 */ 885 <&tegra_car 10>, /* spdif */ 886 <&tegra_car 153>, /* amx */ 887 <&tegra_car 185>, /* amx1 */ 888 <&tegra_car 154>, /* adx */ 889 <&tegra_car 180>, /* adx1 */ 890 <&tegra_car 186>, /* afc0 */ 891 <&tegra_car 187>, /* afc1 */ 892 <&tegra_car 188>, /* afc2 */ 893 <&tegra_car 189>, /* afc3 */ 894 <&tegra_car 190>, /* afc4 */ 895 <&tegra_car 191>; /* afc5 */ 896 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 897 "i2s3", "i2s4", "dam0", "dam1", "dam2", 898 "spdif", "amx", "amx1", "adx", "adx1", 899 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 900 dmas = <&apbdma 1>, <&apbdma 1>, 901 <&apbdma 2>, <&apbdma 2>, 902 <&apbdma 3>, <&apbdma 3>, 903 <&apbdma 4>, <&apbdma 4>, 904 <&apbdma 6>, <&apbdma 6>, 905 <&apbdma 7>, <&apbdma 7>, 906 <&apbdma 12>, <&apbdma 12>, 907 <&apbdma 13>, <&apbdma 13>, 908 <&apbdma 14>, <&apbdma 14>, 909 <&apbdma 29>, <&apbdma 29>; 910 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 911 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 912 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 913 "rx9", "tx9"; 914 ranges; 915 #address-cells = <2>; 916 #size-cells = <2>; 917 918 tegra_i2s0: i2s@70301000 { 919 compatible = "nvidia,tegra124-i2s"; 920 reg = <0x0 0x70301000 0x0 0x100>; 921 nvidia,ahub-cif-ids = <4 4>; 922 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 923 clock-names = "i2s"; 924 resets = <&tegra_car 30>; 925 reset-names = "i2s"; 926 status = "disabled"; 927 }; 928 929 tegra_i2s1: i2s@70301100 { 930 compatible = "nvidia,tegra124-i2s"; 931 reg = <0x0 0x70301100 0x0 0x100>; 932 nvidia,ahub-cif-ids = <5 5>; 933 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 934 clock-names = "i2s"; 935 resets = <&tegra_car 11>; 936 reset-names = "i2s"; 937 status = "disabled"; 938 }; 939 940 tegra_i2s2: i2s@70301200 { 941 compatible = "nvidia,tegra124-i2s"; 942 reg = <0x0 0x70301200 0x0 0x100>; 943 nvidia,ahub-cif-ids = <6 6>; 944 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 945 clock-names = "i2s"; 946 resets = <&tegra_car 18>; 947 reset-names = "i2s"; 948 status = "disabled"; 949 }; 950 951 tegra_i2s3: i2s@70301300 { 952 compatible = "nvidia,tegra124-i2s"; 953 reg = <0x0 0x70301300 0x0 0x100>; 954 nvidia,ahub-cif-ids = <7 7>; 955 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 956 clock-names = "i2s"; 957 resets = <&tegra_car 101>; 958 reset-names = "i2s"; 959 status = "disabled"; 960 }; 961 962 tegra_i2s4: i2s@70301400 { 963 compatible = "nvidia,tegra124-i2s"; 964 reg = <0x0 0x70301400 0x0 0x100>; 965 nvidia,ahub-cif-ids = <8 8>; 966 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 967 clock-names = "i2s"; 968 resets = <&tegra_car 102>; 969 reset-names = "i2s"; 970 status = "disabled"; 971 }; 972 }; 973 974 usb@7d000000 { 975 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 976 reg = <0x0 0x7d000000 0x0 0x4000>; 977 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 978 phy_type = "utmi"; 979 clocks = <&tegra_car TEGRA124_CLK_USBD>; 980 clock-names = "usb"; 981 resets = <&tegra_car 22>; 982 reset-names = "usb"; 983 nvidia,phy = <&phy1>; 984 status = "disabled"; 985 }; 986 987 phy1: usb-phy@7d000000 { 988 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 989 reg = <0x0 0x7d000000 0x0 0x4000>, 990 <0x0 0x7d000000 0x0 0x4000>; 991 phy_type = "utmi"; 992 clocks = <&tegra_car TEGRA124_CLK_USBD>, 993 <&tegra_car TEGRA124_CLK_PLL_U>, 994 <&tegra_car TEGRA124_CLK_USBD>; 995 clock-names = "reg", "pll_u", "utmi-pads"; 996 resets = <&tegra_car 22>, <&tegra_car 22>; 997 reset-names = "usb", "utmi-pads"; 998 nvidia,hssync-start-delay = <0>; 999 nvidia,idle-wait-delay = <17>; 1000 nvidia,elastic-limit = <16>; 1001 nvidia,term-range-adj = <6>; 1002 nvidia,xcvr-setup = <9>; 1003 nvidia,xcvr-lsfslew = <0>; 1004 nvidia,xcvr-lsrslew = <3>; 1005 nvidia,hssquelch-level = <2>; 1006 nvidia,hsdiscon-level = <5>; 1007 nvidia,xcvr-hsslew = <12>; 1008 nvidia,has-utmi-pad-registers; 1009 status = "disabled"; 1010 }; 1011 1012 usb@7d004000 { 1013 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1014 reg = <0x0 0x7d004000 0x0 0x4000>; 1015 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1016 phy_type = "utmi"; 1017 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1018 clock-names = "usb"; 1019 resets = <&tegra_car 58>; 1020 reset-names = "usb"; 1021 nvidia,phy = <&phy2>; 1022 status = "disabled"; 1023 }; 1024 1025 phy2: usb-phy@7d004000 { 1026 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1027 reg = <0x0 0x7d004000 0x0 0x4000>, 1028 <0x0 0x7d000000 0x0 0x4000>; 1029 phy_type = "utmi"; 1030 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1031 <&tegra_car TEGRA124_CLK_PLL_U>, 1032 <&tegra_car TEGRA124_CLK_USBD>; 1033 clock-names = "reg", "pll_u", "utmi-pads"; 1034 resets = <&tegra_car 58>, <&tegra_car 22>; 1035 reset-names = "usb", "utmi-pads"; 1036 nvidia,hssync-start-delay = <0>; 1037 nvidia,idle-wait-delay = <17>; 1038 nvidia,elastic-limit = <16>; 1039 nvidia,term-range-adj = <6>; 1040 nvidia,xcvr-setup = <9>; 1041 nvidia,xcvr-lsfslew = <0>; 1042 nvidia,xcvr-lsrslew = <3>; 1043 nvidia,hssquelch-level = <2>; 1044 nvidia,hsdiscon-level = <5>; 1045 nvidia,xcvr-hsslew = <12>; 1046 status = "disabled"; 1047 }; 1048 1049 usb@7d008000 { 1050 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1051 reg = <0x0 0x7d008000 0x0 0x4000>; 1052 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1053 phy_type = "utmi"; 1054 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1055 clock-names = "usb"; 1056 resets = <&tegra_car 59>; 1057 reset-names = "usb"; 1058 nvidia,phy = <&phy3>; 1059 status = "disabled"; 1060 }; 1061 1062 phy3: usb-phy@7d008000 { 1063 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1064 reg = <0x0 0x7d008000 0x0 0x4000>, 1065 <0x0 0x7d000000 0x0 0x4000>; 1066 phy_type = "utmi"; 1067 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1068 <&tegra_car TEGRA124_CLK_PLL_U>, 1069 <&tegra_car TEGRA124_CLK_USBD>; 1070 clock-names = "reg", "pll_u", "utmi-pads"; 1071 resets = <&tegra_car 59>, <&tegra_car 22>; 1072 reset-names = "usb", "utmi-pads"; 1073 nvidia,hssync-start-delay = <0>; 1074 nvidia,idle-wait-delay = <17>; 1075 nvidia,elastic-limit = <16>; 1076 nvidia,term-range-adj = <6>; 1077 nvidia,xcvr-setup = <9>; 1078 nvidia,xcvr-lsfslew = <0>; 1079 nvidia,xcvr-lsrslew = <3>; 1080 nvidia,hssquelch-level = <2>; 1081 nvidia,hsdiscon-level = <5>; 1082 nvidia,xcvr-hsslew = <12>; 1083 status = "disabled"; 1084 }; 1085 1086 cpus { 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 1090 cpu@0 { 1091 device_type = "cpu"; 1092 compatible = "nvidia,denver"; 1093 reg = <0>; 1094 }; 1095 1096 cpu@1 { 1097 device_type = "cpu"; 1098 compatible = "nvidia,denver"; 1099 reg = <1>; 1100 }; 1101 }; 1102 1103 timer { 1104 compatible = "arm,armv7-timer"; 1105 interrupts = <GIC_PPI 13 1106 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1107 <GIC_PPI 14 1108 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1109 <GIC_PPI 11 1110 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1111 <GIC_PPI 10 1112 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1113 interrupt-parent = <&gic>; 1114 }; 1115}; 1116