1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11/ { 12 compatible = "nvidia,tegra132", "nvidia,tegra124"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 pcie@1003000 { 18 compatible = "nvidia,tegra124-pcie"; 19 device_type = "pci"; 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 43 <&tegra_car TEGRA124_CLK_AFI>, 44 <&tegra_car TEGRA124_CLK_PLL_E>, 45 <&tegra_car TEGRA124_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 54 phy-names = "pcie"; 55 56 pci@1,0 { 57 device_type = "pci"; 58 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 59 reg = <0x000800 0 0 0 0>; 60 bus-range = <0x00 0xff>; 61 status = "disabled"; 62 63 #address-cells = <3>; 64 #size-cells = <2>; 65 ranges; 66 67 nvidia,num-lanes = <2>; 68 }; 69 70 pci@2,0 { 71 device_type = "pci"; 72 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 73 reg = <0x001000 0 0 0 0>; 74 bus-range = <0x00 0xff>; 75 status = "disabled"; 76 77 #address-cells = <3>; 78 #size-cells = <2>; 79 ranges; 80 81 nvidia,num-lanes = <1>; 82 }; 83 }; 84 85 host1x@50000000 { 86 compatible = "nvidia,tegra132-host1x", 87 "nvidia,tegra124-host1x", 88 "simple-bus"; 89 reg = <0x0 0x50000000 0x0 0x00034000>; 90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 91 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 92 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 93 clock-names = "host1x"; 94 resets = <&tegra_car 28>; 95 reset-names = "host1x"; 96 97 #address-cells = <2>; 98 #size-cells = <2>; 99 100 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 101 102 dc@54200000 { 103 compatible = "nvidia,tegra124-dc"; 104 reg = <0x0 0x54200000 0x0 0x00040000>; 105 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 106 clocks = <&tegra_car TEGRA124_CLK_DISP1>, 107 <&tegra_car TEGRA124_CLK_PLL_P>; 108 clock-names = "dc", "parent"; 109 resets = <&tegra_car 27>; 110 reset-names = "dc"; 111 112 iommus = <&mc TEGRA_SWGROUP_DC>; 113 114 nvidia,head = <0>; 115 }; 116 117 dc@54240000 { 118 compatible = "nvidia,tegra124-dc"; 119 reg = <0x0 0x54240000 0x0 0x00040000>; 120 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&tegra_car TEGRA124_CLK_DISP2>, 122 <&tegra_car TEGRA124_CLK_PLL_P>; 123 clock-names = "dc", "parent"; 124 resets = <&tegra_car 26>; 125 reset-names = "dc"; 126 127 iommus = <&mc TEGRA_SWGROUP_DCB>; 128 129 nvidia,head = <1>; 130 }; 131 132 hdmi@54280000 { 133 compatible = "nvidia,tegra124-hdmi"; 134 reg = <0x0 0x54280000 0x0 0x00040000>; 135 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 136 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 137 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 138 clock-names = "hdmi", "parent"; 139 resets = <&tegra_car 51>; 140 reset-names = "hdmi"; 141 status = "disabled"; 142 }; 143 144 sor@54540000 { 145 compatible = "nvidia,tegra124-sor"; 146 reg = <0x0 0x54540000 0x0 0x00040000>; 147 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 149 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 150 <&tegra_car TEGRA124_CLK_PLL_DP>, 151 <&tegra_car TEGRA124_CLK_CLK_M>; 152 clock-names = "sor", "parent", "dp", "safe"; 153 resets = <&tegra_car 182>; 154 reset-names = "sor"; 155 status = "disabled"; 156 }; 157 158 dpaux: dpaux@545c0000 { 159 compatible = "nvidia,tegra124-dpaux"; 160 reg = <0x0 0x545c0000 0x0 0x00040000>; 161 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 163 <&tegra_car TEGRA124_CLK_PLL_DP>; 164 clock-names = "dpaux", "parent"; 165 resets = <&tegra_car 181>; 166 reset-names = "dpaux"; 167 status = "disabled"; 168 }; 169 }; 170 171 gic: interrupt-controller@50041000 { 172 compatible = "arm,cortex-a15-gic"; 173 #interrupt-cells = <3>; 174 interrupt-controller; 175 reg = <0x0 0x50041000 0x0 0x1000>, 176 <0x0 0x50042000 0x0 0x2000>, 177 <0x0 0x50044000 0x0 0x2000>, 178 <0x0 0x50046000 0x0 0x2000>; 179 interrupts = <GIC_PPI 9 180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 181 interrupt-parent = <&gic>; 182 }; 183 184 gpu@57000000 { 185 compatible = "nvidia,gk20a"; 186 reg = <0x0 0x57000000 0x0 0x01000000>, 187 <0x0 0x58000000 0x0 0x01000000>; 188 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 190 interrupt-names = "stall", "nonstall"; 191 clocks = <&tegra_car TEGRA124_CLK_GPU>, 192 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 193 clock-names = "gpu", "pwr"; 194 resets = <&tegra_car 184>; 195 reset-names = "gpu"; 196 status = "disabled"; 197 }; 198 199 lic: interrupt-controller@60004000 { 200 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 201 reg = <0x0 0x60004000 0x0 0x100>, 202 <0x0 0x60004100 0x0 0x100>, 203 <0x0 0x60004200 0x0 0x100>, 204 <0x0 0x60004300 0x0 0x100>, 205 <0x0 0x60004400 0x0 0x100>; 206 interrupt-controller; 207 #interrupt-cells = <3>; 208 interrupt-parent = <&gic>; 209 }; 210 211 timer@60005000 { 212 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 213 reg = <0x0 0x60005000 0x0 0x400>; 214 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 221 clock-names = "timer"; 222 }; 223 224 tegra_car: clock@60006000 { 225 compatible = "nvidia,tegra132-car"; 226 reg = <0x0 0x60006000 0x0 0x1000>; 227 #clock-cells = <1>; 228 #reset-cells = <1>; 229 nvidia,external-memory-controller = <&emc>; 230 }; 231 232 flow-controller@60007000 { 233 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 234 reg = <0x0 0x60007000 0x0 0x1000>; 235 }; 236 237 actmon@6000c800 { 238 compatible = "nvidia,tegra124-actmon"; 239 reg = <0x0 0x6000c800 0x0 0x400>; 240 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 242 <&tegra_car TEGRA124_CLK_EMC>; 243 clock-names = "actmon", "emc"; 244 resets = <&tegra_car 119>; 245 reset-names = "actmon"; 246 }; 247 248 gpio: gpio@6000d000 { 249 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 250 reg = <0x0 0x6000d000 0x0 0x1000>; 251 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 259 #gpio-cells = <2>; 260 gpio-controller; 261 #interrupt-cells = <2>; 262 interrupt-controller; 263 }; 264 265 apbdma: dma@60020000 { 266 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 267 reg = <0x0 0x60020000 0x0 0x1400>; 268 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 301 clock-names = "dma"; 302 resets = <&tegra_car 34>; 303 reset-names = "dma"; 304 #dma-cells = <1>; 305 }; 306 307 apbmisc@70000800 { 308 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 309 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 310 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 311 }; 312 313 pinmux: pinmux@70000868 { 314 compatible = "nvidia,tegra124-pinmux"; 315 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 316 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 317 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 318 }; 319 320 /* 321 * There are two serial driver i.e. 8250 based simple serial 322 * driver and APB DMA based serial driver for higher baudrate 323 * and performance. To enable the 8250 based driver, the compatible 324 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 325 * the APB DMA based serial driver, the compatible is 326 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 327 */ 328 uarta: serial@70006000 { 329 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 330 reg = <0x0 0x70006000 0x0 0x40>; 331 reg-shift = <2>; 332 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 334 clock-names = "serial"; 335 resets = <&tegra_car 6>; 336 reset-names = "serial"; 337 dmas = <&apbdma 8>, <&apbdma 8>; 338 dma-names = "rx", "tx"; 339 status = "disabled"; 340 }; 341 342 uartb: serial@70006040 { 343 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 344 reg = <0x0 0x70006040 0x0 0x40>; 345 reg-shift = <2>; 346 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 348 clock-names = "serial"; 349 resets = <&tegra_car 7>; 350 reset-names = "serial"; 351 dmas = <&apbdma 9>, <&apbdma 9>; 352 dma-names = "rx", "tx"; 353 status = "disabled"; 354 }; 355 356 uartc: serial@70006200 { 357 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 358 reg = <0x0 0x70006200 0x0 0x40>; 359 reg-shift = <2>; 360 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 362 clock-names = "serial"; 363 resets = <&tegra_car 55>; 364 reset-names = "serial"; 365 dmas = <&apbdma 10>, <&apbdma 10>; 366 dma-names = "rx", "tx"; 367 status = "disabled"; 368 }; 369 370 uartd: serial@70006300 { 371 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 372 reg = <0x0 0x70006300 0x0 0x40>; 373 reg-shift = <2>; 374 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 376 clock-names = "serial"; 377 resets = <&tegra_car 65>; 378 reset-names = "serial"; 379 dmas = <&apbdma 19>, <&apbdma 19>; 380 dma-names = "rx", "tx"; 381 status = "disabled"; 382 }; 383 384 pwm: pwm@7000a000 { 385 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 386 reg = <0x0 0x7000a000 0x0 0x100>; 387 #pwm-cells = <2>; 388 clocks = <&tegra_car TEGRA124_CLK_PWM>; 389 clock-names = "pwm"; 390 resets = <&tegra_car 17>; 391 reset-names = "pwm"; 392 status = "disabled"; 393 }; 394 395 i2c@7000c000 { 396 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 397 reg = <0x0 0x7000c000 0x0 0x100>; 398 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 402 clock-names = "div-clk"; 403 resets = <&tegra_car 12>; 404 reset-names = "i2c"; 405 dmas = <&apbdma 21>, <&apbdma 21>; 406 dma-names = "rx", "tx"; 407 status = "disabled"; 408 }; 409 410 i2c@7000c400 { 411 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 412 reg = <0x0 0x7000c400 0x0 0x100>; 413 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 417 clock-names = "div-clk"; 418 resets = <&tegra_car 54>; 419 reset-names = "i2c"; 420 dmas = <&apbdma 22>, <&apbdma 22>; 421 dma-names = "rx", "tx"; 422 status = "disabled"; 423 }; 424 425 i2c@7000c500 { 426 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 427 reg = <0x0 0x7000c500 0x0 0x100>; 428 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 432 clock-names = "div-clk"; 433 resets = <&tegra_car 67>; 434 reset-names = "i2c"; 435 dmas = <&apbdma 23>, <&apbdma 23>; 436 dma-names = "rx", "tx"; 437 status = "disabled"; 438 }; 439 440 i2c@7000c700 { 441 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 442 reg = <0x0 0x7000c700 0x0 0x100>; 443 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 447 clock-names = "div-clk"; 448 resets = <&tegra_car 103>; 449 reset-names = "i2c"; 450 dmas = <&apbdma 26>, <&apbdma 26>; 451 dma-names = "rx", "tx"; 452 status = "disabled"; 453 }; 454 455 i2c@7000d000 { 456 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 457 reg = <0x0 0x7000d000 0x0 0x100>; 458 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 462 clock-names = "div-clk"; 463 resets = <&tegra_car 47>; 464 reset-names = "i2c"; 465 dmas = <&apbdma 24>, <&apbdma 24>; 466 dma-names = "rx", "tx"; 467 status = "disabled"; 468 }; 469 470 i2c@7000d100 { 471 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 472 reg = <0x0 0x7000d100 0x0 0x100>; 473 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 477 clock-names = "div-clk"; 478 resets = <&tegra_car 166>; 479 reset-names = "i2c"; 480 dmas = <&apbdma 30>, <&apbdma 30>; 481 dma-names = "rx", "tx"; 482 status = "disabled"; 483 }; 484 485 spi@7000d400 { 486 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 487 reg = <0x0 0x7000d400 0x0 0x200>; 488 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 492 clock-names = "spi"; 493 resets = <&tegra_car 41>; 494 reset-names = "spi"; 495 dmas = <&apbdma 15>, <&apbdma 15>; 496 dma-names = "rx", "tx"; 497 status = "disabled"; 498 }; 499 500 spi@7000d600 { 501 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 502 reg = <0x0 0x7000d600 0x0 0x200>; 503 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 507 clock-names = "spi"; 508 resets = <&tegra_car 44>; 509 reset-names = "spi"; 510 dmas = <&apbdma 16>, <&apbdma 16>; 511 dma-names = "rx", "tx"; 512 status = "disabled"; 513 }; 514 515 spi@7000d800 { 516 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 517 reg = <0x0 0x7000d800 0x0 0x200>; 518 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 522 clock-names = "spi"; 523 resets = <&tegra_car 46>; 524 reset-names = "spi"; 525 dmas = <&apbdma 17>, <&apbdma 17>; 526 dma-names = "rx", "tx"; 527 status = "disabled"; 528 }; 529 530 spi@7000da00 { 531 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 532 reg = <0x0 0x7000da00 0x0 0x200>; 533 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 537 clock-names = "spi"; 538 resets = <&tegra_car 68>; 539 reset-names = "spi"; 540 dmas = <&apbdma 18>, <&apbdma 18>; 541 dma-names = "rx", "tx"; 542 status = "disabled"; 543 }; 544 545 spi@7000dc00 { 546 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 547 reg = <0x0 0x7000dc00 0x0 0x200>; 548 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 552 clock-names = "spi"; 553 resets = <&tegra_car 104>; 554 reset-names = "spi"; 555 dmas = <&apbdma 27>, <&apbdma 27>; 556 dma-names = "rx", "tx"; 557 status = "disabled"; 558 }; 559 560 spi@7000de00 { 561 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 562 reg = <0x0 0x7000de00 0x0 0x200>; 563 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 567 clock-names = "spi"; 568 resets = <&tegra_car 105>; 569 reset-names = "spi"; 570 dmas = <&apbdma 28>, <&apbdma 28>; 571 dma-names = "rx", "tx"; 572 status = "disabled"; 573 }; 574 575 rtc@7000e000 { 576 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 577 reg = <0x0 0x7000e000 0x0 0x100>; 578 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&tegra_car TEGRA124_CLK_RTC>; 580 clock-names = "rtc"; 581 }; 582 583 tegra_pmc: pmc@7000e400 { 584 compatible = "nvidia,tegra124-pmc"; 585 reg = <0x0 0x7000e400 0x0 0x400>; 586 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 587 clock-names = "pclk", "clk32k_in"; 588 #clock-cells = <1>; 589 }; 590 591 fuse@7000f800 { 592 compatible = "nvidia,tegra124-efuse"; 593 reg = <0x0 0x7000f800 0x0 0x400>; 594 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 595 clock-names = "fuse"; 596 resets = <&tegra_car 39>; 597 reset-names = "fuse"; 598 }; 599 600 mc: memory-controller@70019000 { 601 compatible = "nvidia,tegra132-mc"; 602 reg = <0x0 0x70019000 0x0 0x1000>; 603 clocks = <&tegra_car TEGRA124_CLK_MC>; 604 clock-names = "mc"; 605 606 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 607 608 #iommu-cells = <1>; 609 }; 610 611 emc: external-memory-controller@7001b000 { 612 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 613 reg = <0x0 0x7001b000 0x0 0x1000>; 614 clocks = <&tegra_car TEGRA124_CLK_EMC>; 615 clock-names = "emc"; 616 617 nvidia,memory-controller = <&mc>; 618 }; 619 620 sata@70020000 { 621 compatible = "nvidia,tegra124-ahci"; 622 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 623 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 624 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&tegra_car TEGRA124_CLK_SATA>, 626 <&tegra_car TEGRA124_CLK_SATA_OOB>, 627 <&tegra_car TEGRA124_CLK_CML1>, 628 <&tegra_car TEGRA124_CLK_PLL_E>; 629 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 630 resets = <&tegra_car 124>, 631 <&tegra_car 123>, 632 <&tegra_car 129>; 633 reset-names = "sata", "sata-oob", "sata-cold"; 634 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 635 phy-names = "sata-phy"; 636 status = "disabled"; 637 }; 638 639 hda@70030000 { 640 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 641 "nvidia,tegra30-hda"; 642 reg = <0x0 0x70030000 0x0 0x10000>; 643 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&tegra_car TEGRA124_CLK_HDA>, 645 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 646 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 647 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 648 resets = <&tegra_car 125>, /* hda */ 649 <&tegra_car 128>, /* hda2hdmi */ 650 <&tegra_car 111>; /* hda2codec_2x */ 651 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 652 status = "disabled"; 653 }; 654 655 padctl: padctl@7009f000 { 656 compatible = "nvidia,tegra132-xusb-padctl", 657 "nvidia,tegra124-xusb-padctl"; 658 reg = <0x0 0x7009f000 0x0 0x1000>; 659 resets = <&tegra_car 142>; 660 reset-names = "padctl"; 661 662 #phy-cells = <1>; 663 664 phys { 665 pcie-0 { 666 status = "disabled"; 667 }; 668 669 sata-0 { 670 status = "disabled"; 671 }; 672 673 usb3-0 { 674 status = "disabled"; 675 }; 676 677 usb3-1 { 678 status = "disabled"; 679 }; 680 681 utmi-0 { 682 status = "disabled"; 683 }; 684 685 utmi-1 { 686 status = "disabled"; 687 }; 688 689 utmi-2 { 690 status = "disabled"; 691 }; 692 }; 693 }; 694 695 sdhci@700b0000 { 696 compatible = "nvidia,tegra124-sdhci"; 697 reg = <0x0 0x700b0000 0x0 0x200>; 698 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 700 clock-names = "sdhci"; 701 resets = <&tegra_car 14>; 702 reset-names = "sdhci"; 703 status = "disabled"; 704 }; 705 706 sdhci@700b0200 { 707 compatible = "nvidia,tegra124-sdhci"; 708 reg = <0x0 0x700b0200 0x0 0x200>; 709 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 711 clock-names = "sdhci"; 712 resets = <&tegra_car 9>; 713 reset-names = "sdhci"; 714 status = "disabled"; 715 }; 716 717 sdhci@700b0400 { 718 compatible = "nvidia,tegra124-sdhci"; 719 reg = <0x0 0x700b0400 0x0 0x200>; 720 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 722 clock-names = "sdhci"; 723 resets = <&tegra_car 69>; 724 reset-names = "sdhci"; 725 status = "disabled"; 726 }; 727 728 sdhci@700b0600 { 729 compatible = "nvidia,tegra124-sdhci"; 730 reg = <0x0 0x700b0600 0x0 0x200>; 731 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 733 clock-names = "sdhci"; 734 resets = <&tegra_car 15>; 735 reset-names = "sdhci"; 736 status = "disabled"; 737 }; 738 739 soctherm: thermal-sensor@700e2000 { 740 compatible = "nvidia,tegra132-soctherm"; 741 reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */ 742 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 743 reg-names = "soctherm-reg", "ccroc-reg"; 744 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 746 <&tegra_car TEGRA124_CLK_SOC_THERM>; 747 clock-names = "tsensor", "soctherm"; 748 resets = <&tegra_car 78>; 749 reset-names = "soctherm"; 750 #thermal-sensor-cells = <1>; 751 752 throttle-cfgs { 753 throttle_heavy: heavy { 754 nvidia,priority = <100>; 755 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 756 757 #cooling-cells = <2>; 758 }; 759 }; 760 }; 761 762 thermal-zones { 763 cpu { 764 polling-delay-passive = <1000>; 765 polling-delay = <0>; 766 767 thermal-sensors = 768 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 769 770 trips { 771 cpu_shutdown_trip { 772 temperature = <105000>; 773 hysteresis = <1000>; 774 type = "critical"; 775 }; 776 777 cpu_throttle_trip: throttle-trip { 778 temperature = <102000>; 779 hysteresis = <1000>; 780 type = "hot"; 781 }; 782 }; 783 784 cooling-maps { 785 map0 { 786 trip = <&cpu_throttle_trip>; 787 cooling-device = <&throttle_heavy 1 1>; 788 }; 789 }; 790 }; 791 mem { 792 polling-delay-passive = <0>; 793 polling-delay = <0>; 794 795 thermal-sensors = 796 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 797 798 trips { 799 mem_shutdown_trip { 800 temperature = <101000>; 801 hysteresis = <1000>; 802 type = "critical"; 803 }; 804 }; 805 806 cooling-maps { 807 /* 808 * There are currently no cooling maps, 809 * because there are no cooling devices. 810 */ 811 }; 812 }; 813 gpu { 814 polling-delay-passive = <1000>; 815 polling-delay = <0>; 816 817 thermal-sensors = 818 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 819 820 trips { 821 gpu_shutdown_trip { 822 temperature = <101000>; 823 hysteresis = <1000>; 824 type = "critical"; 825 }; 826 827 gpu_throttle_trip: throttle-trip { 828 temperature = <99000>; 829 hysteresis = <1000>; 830 type = "hot"; 831 }; 832 }; 833 834 cooling-maps { 835 map0 { 836 trip = <&gpu_throttle_trip>; 837 cooling-device = <&throttle_heavy 1 1>; 838 }; 839 }; 840 }; 841 pllx { 842 polling-delay-passive = <0>; 843 polling-delay = <0>; 844 845 thermal-sensors = 846 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 847 848 trips { 849 pllx_shutdown_trip { 850 temperature = <105000>; 851 hysteresis = <1000>; 852 type = "critical"; 853 }; 854 }; 855 856 cooling-maps { 857 /* 858 * There are currently no cooling maps, 859 * because there are no cooling devices. 860 */ 861 }; 862 }; 863 }; 864 865 ahub@70300000 { 866 compatible = "nvidia,tegra124-ahub"; 867 reg = <0x0 0x70300000 0x0 0x200>, 868 <0x0 0x70300800 0x0 0x800>, 869 <0x0 0x70300200 0x0 0x600>; 870 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 872 <&tegra_car TEGRA124_CLK_APBIF>; 873 clock-names = "d_audio", "apbif"; 874 resets = <&tegra_car 106>, /* d_audio */ 875 <&tegra_car 107>, /* apbif */ 876 <&tegra_car 30>, /* i2s0 */ 877 <&tegra_car 11>, /* i2s1 */ 878 <&tegra_car 18>, /* i2s2 */ 879 <&tegra_car 101>, /* i2s3 */ 880 <&tegra_car 102>, /* i2s4 */ 881 <&tegra_car 108>, /* dam0 */ 882 <&tegra_car 109>, /* dam1 */ 883 <&tegra_car 110>, /* dam2 */ 884 <&tegra_car 10>, /* spdif */ 885 <&tegra_car 153>, /* amx */ 886 <&tegra_car 185>, /* amx1 */ 887 <&tegra_car 154>, /* adx */ 888 <&tegra_car 180>, /* adx1 */ 889 <&tegra_car 186>, /* afc0 */ 890 <&tegra_car 187>, /* afc1 */ 891 <&tegra_car 188>, /* afc2 */ 892 <&tegra_car 189>, /* afc3 */ 893 <&tegra_car 190>, /* afc4 */ 894 <&tegra_car 191>; /* afc5 */ 895 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 896 "i2s3", "i2s4", "dam0", "dam1", "dam2", 897 "spdif", "amx", "amx1", "adx", "adx1", 898 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 899 dmas = <&apbdma 1>, <&apbdma 1>, 900 <&apbdma 2>, <&apbdma 2>, 901 <&apbdma 3>, <&apbdma 3>, 902 <&apbdma 4>, <&apbdma 4>, 903 <&apbdma 6>, <&apbdma 6>, 904 <&apbdma 7>, <&apbdma 7>, 905 <&apbdma 12>, <&apbdma 12>, 906 <&apbdma 13>, <&apbdma 13>, 907 <&apbdma 14>, <&apbdma 14>, 908 <&apbdma 29>, <&apbdma 29>; 909 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 910 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 911 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 912 "rx9", "tx9"; 913 ranges; 914 #address-cells = <2>; 915 #size-cells = <2>; 916 917 tegra_i2s0: i2s@70301000 { 918 compatible = "nvidia,tegra124-i2s"; 919 reg = <0x0 0x70301000 0x0 0x100>; 920 nvidia,ahub-cif-ids = <4 4>; 921 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 922 clock-names = "i2s"; 923 resets = <&tegra_car 30>; 924 reset-names = "i2s"; 925 status = "disabled"; 926 }; 927 928 tegra_i2s1: i2s@70301100 { 929 compatible = "nvidia,tegra124-i2s"; 930 reg = <0x0 0x70301100 0x0 0x100>; 931 nvidia,ahub-cif-ids = <5 5>; 932 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 933 clock-names = "i2s"; 934 resets = <&tegra_car 11>; 935 reset-names = "i2s"; 936 status = "disabled"; 937 }; 938 939 tegra_i2s2: i2s@70301200 { 940 compatible = "nvidia,tegra124-i2s"; 941 reg = <0x0 0x70301200 0x0 0x100>; 942 nvidia,ahub-cif-ids = <6 6>; 943 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 944 clock-names = "i2s"; 945 resets = <&tegra_car 18>; 946 reset-names = "i2s"; 947 status = "disabled"; 948 }; 949 950 tegra_i2s3: i2s@70301300 { 951 compatible = "nvidia,tegra124-i2s"; 952 reg = <0x0 0x70301300 0x0 0x100>; 953 nvidia,ahub-cif-ids = <7 7>; 954 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 955 clock-names = "i2s"; 956 resets = <&tegra_car 101>; 957 reset-names = "i2s"; 958 status = "disabled"; 959 }; 960 961 tegra_i2s4: i2s@70301400 { 962 compatible = "nvidia,tegra124-i2s"; 963 reg = <0x0 0x70301400 0x0 0x100>; 964 nvidia,ahub-cif-ids = <8 8>; 965 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 966 clock-names = "i2s"; 967 resets = <&tegra_car 102>; 968 reset-names = "i2s"; 969 status = "disabled"; 970 }; 971 }; 972 973 usb@7d000000 { 974 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 975 reg = <0x0 0x7d000000 0x0 0x4000>; 976 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 977 phy_type = "utmi"; 978 clocks = <&tegra_car TEGRA124_CLK_USBD>; 979 clock-names = "usb"; 980 resets = <&tegra_car 22>; 981 reset-names = "usb"; 982 nvidia,phy = <&phy1>; 983 status = "disabled"; 984 }; 985 986 phy1: usb-phy@7d000000 { 987 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 988 reg = <0x0 0x7d000000 0x0 0x4000>, 989 <0x0 0x7d000000 0x0 0x4000>; 990 phy_type = "utmi"; 991 clocks = <&tegra_car TEGRA124_CLK_USBD>, 992 <&tegra_car TEGRA124_CLK_PLL_U>, 993 <&tegra_car TEGRA124_CLK_USBD>; 994 clock-names = "reg", "pll_u", "utmi-pads"; 995 resets = <&tegra_car 22>, <&tegra_car 22>; 996 reset-names = "usb", "utmi-pads"; 997 nvidia,hssync-start-delay = <0>; 998 nvidia,idle-wait-delay = <17>; 999 nvidia,elastic-limit = <16>; 1000 nvidia,term-range-adj = <6>; 1001 nvidia,xcvr-setup = <9>; 1002 nvidia,xcvr-lsfslew = <0>; 1003 nvidia,xcvr-lsrslew = <3>; 1004 nvidia,hssquelch-level = <2>; 1005 nvidia,hsdiscon-level = <5>; 1006 nvidia,xcvr-hsslew = <12>; 1007 nvidia,has-utmi-pad-registers; 1008 status = "disabled"; 1009 }; 1010 1011 usb@7d004000 { 1012 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1013 reg = <0x0 0x7d004000 0x0 0x4000>; 1014 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1015 phy_type = "utmi"; 1016 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1017 clock-names = "usb"; 1018 resets = <&tegra_car 58>; 1019 reset-names = "usb"; 1020 nvidia,phy = <&phy2>; 1021 status = "disabled"; 1022 }; 1023 1024 phy2: usb-phy@7d004000 { 1025 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1026 reg = <0x0 0x7d004000 0x0 0x4000>, 1027 <0x0 0x7d000000 0x0 0x4000>; 1028 phy_type = "utmi"; 1029 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1030 <&tegra_car TEGRA124_CLK_PLL_U>, 1031 <&tegra_car TEGRA124_CLK_USBD>; 1032 clock-names = "reg", "pll_u", "utmi-pads"; 1033 resets = <&tegra_car 58>, <&tegra_car 22>; 1034 reset-names = "usb", "utmi-pads"; 1035 nvidia,hssync-start-delay = <0>; 1036 nvidia,idle-wait-delay = <17>; 1037 nvidia,elastic-limit = <16>; 1038 nvidia,term-range-adj = <6>; 1039 nvidia,xcvr-setup = <9>; 1040 nvidia,xcvr-lsfslew = <0>; 1041 nvidia,xcvr-lsrslew = <3>; 1042 nvidia,hssquelch-level = <2>; 1043 nvidia,hsdiscon-level = <5>; 1044 nvidia,xcvr-hsslew = <12>; 1045 status = "disabled"; 1046 }; 1047 1048 usb@7d008000 { 1049 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1050 reg = <0x0 0x7d008000 0x0 0x4000>; 1051 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1052 phy_type = "utmi"; 1053 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1054 clock-names = "usb"; 1055 resets = <&tegra_car 59>; 1056 reset-names = "usb"; 1057 nvidia,phy = <&phy3>; 1058 status = "disabled"; 1059 }; 1060 1061 phy3: usb-phy@7d008000 { 1062 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1063 reg = <0x0 0x7d008000 0x0 0x4000>, 1064 <0x0 0x7d000000 0x0 0x4000>; 1065 phy_type = "utmi"; 1066 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1067 <&tegra_car TEGRA124_CLK_PLL_U>, 1068 <&tegra_car TEGRA124_CLK_USBD>; 1069 clock-names = "reg", "pll_u", "utmi-pads"; 1070 resets = <&tegra_car 59>, <&tegra_car 22>; 1071 reset-names = "usb", "utmi-pads"; 1072 nvidia,hssync-start-delay = <0>; 1073 nvidia,idle-wait-delay = <17>; 1074 nvidia,elastic-limit = <16>; 1075 nvidia,term-range-adj = <6>; 1076 nvidia,xcvr-setup = <9>; 1077 nvidia,xcvr-lsfslew = <0>; 1078 nvidia,xcvr-lsrslew = <3>; 1079 nvidia,hssquelch-level = <2>; 1080 nvidia,hsdiscon-level = <5>; 1081 nvidia,xcvr-hsslew = <12>; 1082 status = "disabled"; 1083 }; 1084 1085 cpus { 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 1089 cpu@0 { 1090 device_type = "cpu"; 1091 compatible = "nvidia,denver"; 1092 reg = <0>; 1093 }; 1094 1095 cpu@1 { 1096 device_type = "cpu"; 1097 compatible = "nvidia,denver"; 1098 reg = <1>; 1099 }; 1100 }; 1101 1102 timer { 1103 compatible = "arm,armv7-timer"; 1104 interrupts = <GIC_PPI 13 1105 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1106 <GIC_PPI 14 1107 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1108 <GIC_PPI 11 1109 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1110 <GIC_PPI 10 1111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1112 interrupt-parent = <&gic>; 1113 }; 1114}; 1115