1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 234b4f6d0SThierry Reding#include <dt-bindings/clock/tegra124-car.h> 334b4f6d0SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 434b4f6d0SThierry Reding#include <dt-bindings/memory/tegra124-mc.h> 534b4f6d0SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 634b4f6d0SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 734b4f6d0SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 80fa2bfcdSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 9359ae651SSowjanya Komatineni#include <dt-bindings/soc/tegra-pmc.h> 1034b4f6d0SThierry Reding 11ed9e9a6eSThierry Reding#include "tegra132-peripherals-opp.dtsi" 12ed9e9a6eSThierry Reding 1334b4f6d0SThierry Reding/ { 1434b4f6d0SThierry Reding compatible = "nvidia,tegra132", "nvidia,tegra124"; 1534b4f6d0SThierry Reding interrupt-parent = <&lic>; 1634b4f6d0SThierry Reding #address-cells = <2>; 1734b4f6d0SThierry Reding #size-cells = <2>; 1834b4f6d0SThierry Reding 19475d99fcSRob Herring pcie@1003000 { 2034b4f6d0SThierry Reding compatible = "nvidia,tegra124-pcie"; 2134b4f6d0SThierry Reding device_type = "pci"; 22644c569dSThierry Reding reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 23644c569dSThierry Reding <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 24644c569dSThierry Reding <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 2534b4f6d0SThierry Reding reg-names = "pads", "afi", "cs"; 2634b4f6d0SThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2734b4f6d0SThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2834b4f6d0SThierry Reding interrupt-names = "intr", "msi"; 2934b4f6d0SThierry Reding 3034b4f6d0SThierry Reding #interrupt-cells = <1>; 3134b4f6d0SThierry Reding interrupt-map-mask = <0 0 0 0>; 3234b4f6d0SThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 3334b4f6d0SThierry Reding 3434b4f6d0SThierry Reding bus-range = <0x00 0xff>; 3534b4f6d0SThierry Reding #address-cells = <3>; 3634b4f6d0SThierry Reding #size-cells = <2>; 3734b4f6d0SThierry Reding 38644c569dSThierry Reding ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 39644c569dSThierry Reding <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 40644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 41644c569dSThierry Reding <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 42644c569dSThierry Reding <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 4334b4f6d0SThierry Reding 4434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PCIE>, 4534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_AFI>, 4634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_E>, 4734b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CML0>; 4834b4f6d0SThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 4934b4f6d0SThierry Reding resets = <&tegra_car 70>, 5034b4f6d0SThierry Reding <&tegra_car 72>, 5134b4f6d0SThierry Reding <&tegra_car 74>; 5234b4f6d0SThierry Reding reset-names = "pex", "afi", "pcie_x"; 5334b4f6d0SThierry Reding status = "disabled"; 5434b4f6d0SThierry Reding 5534b4f6d0SThierry Reding pci@1,0 { 5634b4f6d0SThierry Reding device_type = "pci"; 5734b4f6d0SThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 5834b4f6d0SThierry Reding reg = <0x000800 0 0 0 0>; 59475d99fcSRob Herring bus-range = <0x00 0xff>; 6034b4f6d0SThierry Reding status = "disabled"; 6134b4f6d0SThierry Reding 6234b4f6d0SThierry Reding #address-cells = <3>; 6334b4f6d0SThierry Reding #size-cells = <2>; 6434b4f6d0SThierry Reding ranges; 6534b4f6d0SThierry Reding 6634b4f6d0SThierry Reding nvidia,num-lanes = <2>; 6734b4f6d0SThierry Reding }; 6834b4f6d0SThierry Reding 6934b4f6d0SThierry Reding pci@2,0 { 7034b4f6d0SThierry Reding device_type = "pci"; 7134b4f6d0SThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 7234b4f6d0SThierry Reding reg = <0x001000 0 0 0 0>; 73475d99fcSRob Herring bus-range = <0x00 0xff>; 7434b4f6d0SThierry Reding status = "disabled"; 7534b4f6d0SThierry Reding 7634b4f6d0SThierry Reding #address-cells = <3>; 7734b4f6d0SThierry Reding #size-cells = <2>; 7834b4f6d0SThierry Reding ranges; 7934b4f6d0SThierry Reding 8034b4f6d0SThierry Reding nvidia,num-lanes = <1>; 8134b4f6d0SThierry Reding }; 8234b4f6d0SThierry Reding }; 8334b4f6d0SThierry Reding 84be70771dSThierry Reding host1x@50000000 { 8501a9d523SThierry Reding compatible = "nvidia,tegra132-host1x", 86ef126bc4SThierry Reding "nvidia,tegra124-host1x"; 8734b4f6d0SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 8834b4f6d0SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 8934b4f6d0SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 90052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 9134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 9234b4f6d0SThierry Reding clock-names = "host1x"; 9334b4f6d0SThierry Reding resets = <&tegra_car 28>; 9434b4f6d0SThierry Reding reset-names = "host1x"; 9534b4f6d0SThierry Reding 9634b4f6d0SThierry Reding #address-cells = <2>; 9734b4f6d0SThierry Reding #size-cells = <2>; 9834b4f6d0SThierry Reding 9934b4f6d0SThierry Reding ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 10034b4f6d0SThierry Reding 101be70771dSThierry Reding dc@54200000 { 10234b4f6d0SThierry Reding compatible = "nvidia,tegra124-dc"; 10334b4f6d0SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 10434b4f6d0SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 105352092b0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DISP1>; 106352092b0SThierry Reding clock-names = "dc"; 10734b4f6d0SThierry Reding resets = <&tegra_car 27>; 10834b4f6d0SThierry Reding reset-names = "dc"; 10934b4f6d0SThierry Reding 11034b4f6d0SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 11134b4f6d0SThierry Reding 11234b4f6d0SThierry Reding nvidia,head = <0>; 11334b4f6d0SThierry Reding }; 11434b4f6d0SThierry Reding 115be70771dSThierry Reding dc@54240000 { 11634b4f6d0SThierry Reding compatible = "nvidia,tegra124-dc"; 11734b4f6d0SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 11834b4f6d0SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 119352092b0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DISP2>; 120352092b0SThierry Reding clock-names = "dc"; 12134b4f6d0SThierry Reding resets = <&tegra_car 26>; 12234b4f6d0SThierry Reding reset-names = "dc"; 12334b4f6d0SThierry Reding 12434b4f6d0SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 12534b4f6d0SThierry Reding 12634b4f6d0SThierry Reding nvidia,head = <1>; 12734b4f6d0SThierry Reding }; 12834b4f6d0SThierry Reding 129be70771dSThierry Reding hdmi@54280000 { 13034b4f6d0SThierry Reding compatible = "nvidia,tegra124-hdmi"; 13134b4f6d0SThierry Reding reg = <0x0 0x54280000 0x0 0x00040000>; 13234b4f6d0SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 13334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HDMI>, 13434b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 13534b4f6d0SThierry Reding clock-names = "hdmi", "parent"; 13634b4f6d0SThierry Reding resets = <&tegra_car 51>; 13734b4f6d0SThierry Reding reset-names = "hdmi"; 13834b4f6d0SThierry Reding status = "disabled"; 13934b4f6d0SThierry Reding }; 14034b4f6d0SThierry Reding 141be70771dSThierry Reding sor@54540000 { 14234b4f6d0SThierry Reding compatible = "nvidia,tegra124-sor"; 14334b4f6d0SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 14434b4f6d0SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 14534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SOR0>, 146abc9c8a5SThierry Reding <&tegra_car TEGRA124_CLK_SOR0_OUT>, 14734b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 14834b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_DP>, 14934b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CLK_M>; 150abc9c8a5SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 15134b4f6d0SThierry Reding resets = <&tegra_car 182>; 15234b4f6d0SThierry Reding reset-names = "sor"; 15334b4f6d0SThierry Reding status = "disabled"; 15434b4f6d0SThierry Reding }; 15534b4f6d0SThierry Reding 156be70771dSThierry Reding dpaux: dpaux@545c0000 { 15734b4f6d0SThierry Reding compatible = "nvidia,tegra124-dpaux"; 15834b4f6d0SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 15934b4f6d0SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 16034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 16134b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_DP>; 16234b4f6d0SThierry Reding clock-names = "dpaux", "parent"; 16334b4f6d0SThierry Reding resets = <&tegra_car 181>; 16434b4f6d0SThierry Reding reset-names = "dpaux"; 16534b4f6d0SThierry Reding status = "disabled"; 166997a3b73SThierry Reding 167997a3b73SThierry Reding i2c-bus { 168997a3b73SThierry Reding #address-cells = <1>; 169997a3b73SThierry Reding #size-cells = <0>; 170997a3b73SThierry Reding }; 17134b4f6d0SThierry Reding }; 17234b4f6d0SThierry Reding }; 17334b4f6d0SThierry Reding 174be70771dSThierry Reding gic: interrupt-controller@50041000 { 17534b4f6d0SThierry Reding compatible = "arm,cortex-a15-gic"; 17634b4f6d0SThierry Reding #interrupt-cells = <3>; 17734b4f6d0SThierry Reding interrupt-controller; 17834b4f6d0SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 17934b4f6d0SThierry Reding <0x0 0x50042000 0x0 0x2000>, 18034b4f6d0SThierry Reding <0x0 0x50044000 0x0 0x2000>, 18134b4f6d0SThierry Reding <0x0 0x50046000 0x0 0x2000>; 18234b4f6d0SThierry Reding interrupts = <GIC_PPI 9 18334b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 18434b4f6d0SThierry Reding interrupt-parent = <&gic>; 18534b4f6d0SThierry Reding }; 18634b4f6d0SThierry Reding 187be70771dSThierry Reding gpu@57000000 { 18834b4f6d0SThierry Reding compatible = "nvidia,gk20a"; 18934b4f6d0SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 19034b4f6d0SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 19134b4f6d0SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 19234b4f6d0SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 19334b4f6d0SThierry Reding interrupt-names = "stall", "nonstall"; 19434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_GPU>, 19534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 19634b4f6d0SThierry Reding clock-names = "gpu", "pwr"; 19734b4f6d0SThierry Reding resets = <&tegra_car 184>; 19834b4f6d0SThierry Reding reset-names = "gpu"; 19934b4f6d0SThierry Reding status = "disabled"; 20034b4f6d0SThierry Reding }; 20134b4f6d0SThierry Reding 20234b4f6d0SThierry Reding lic: interrupt-controller@60004000 { 20334b4f6d0SThierry Reding compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 20434b4f6d0SThierry Reding reg = <0x0 0x60004000 0x0 0x100>, 20534b4f6d0SThierry Reding <0x0 0x60004100 0x0 0x100>, 20634b4f6d0SThierry Reding <0x0 0x60004200 0x0 0x100>, 20734b4f6d0SThierry Reding <0x0 0x60004300 0x0 0x100>, 20834b4f6d0SThierry Reding <0x0 0x60004400 0x0 0x100>; 20934b4f6d0SThierry Reding interrupt-controller; 21034b4f6d0SThierry Reding #interrupt-cells = <3>; 21134b4f6d0SThierry Reding interrupt-parent = <&gic>; 21234b4f6d0SThierry Reding }; 21334b4f6d0SThierry Reding 214be70771dSThierry Reding timer@60005000 { 215bb43b219SThierry Reding compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; 21634b4f6d0SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 21734b4f6d0SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 21834b4f6d0SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 21934b4f6d0SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 22034b4f6d0SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 22134b4f6d0SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 22234b4f6d0SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 22334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_TIMER>; 22434b4f6d0SThierry Reding clock-names = "timer"; 22534b4f6d0SThierry Reding }; 22634b4f6d0SThierry Reding 227be70771dSThierry Reding tegra_car: clock@60006000 { 22834b4f6d0SThierry Reding compatible = "nvidia,tegra132-car"; 22934b4f6d0SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 23034b4f6d0SThierry Reding #clock-cells = <1>; 23134b4f6d0SThierry Reding #reset-cells = <1>; 23234b4f6d0SThierry Reding nvidia,external-memory-controller = <&emc>; 23334b4f6d0SThierry Reding }; 23434b4f6d0SThierry Reding 235be70771dSThierry Reding flow-controller@60007000 { 23618236a14SJon Hunter compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 23734b4f6d0SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 23834b4f6d0SThierry Reding }; 23934b4f6d0SThierry Reding 240be70771dSThierry Reding actmon@6000c800 { 24134b4f6d0SThierry Reding compatible = "nvidia,tegra124-actmon"; 24234b4f6d0SThierry Reding reg = <0x0 0x6000c800 0x0 0x400>; 24334b4f6d0SThierry Reding interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 24434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 24534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_EMC>; 24634b4f6d0SThierry Reding clock-names = "actmon", "emc"; 24734b4f6d0SThierry Reding resets = <&tegra_car 119>; 24834b4f6d0SThierry Reding reset-names = "actmon"; 249ed9e9a6eSThierry Reding operating-points-v2 = <&emc_bw_dfs_opp_table>; 250ed9e9a6eSThierry Reding interconnects = <&mc TEGRA124_MC_MPCORER &emc>; 251ed9e9a6eSThierry Reding interconnect-names = "cpu-read"; 252ed9e9a6eSThierry Reding #cooling-cells = <2>; 25334b4f6d0SThierry Reding }; 25434b4f6d0SThierry Reding 255be70771dSThierry Reding gpio: gpio@6000d000 { 25634b4f6d0SThierry Reding compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 25734b4f6d0SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 25834b4f6d0SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 25934b4f6d0SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 26034b4f6d0SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 26134b4f6d0SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 26234b4f6d0SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 26334b4f6d0SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 26434b4f6d0SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 26534b4f6d0SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 26634b4f6d0SThierry Reding #gpio-cells = <2>; 26734b4f6d0SThierry Reding gpio-controller; 26834b4f6d0SThierry Reding #interrupt-cells = <2>; 26934b4f6d0SThierry Reding interrupt-controller; 27034b4f6d0SThierry Reding }; 27134b4f6d0SThierry Reding 272be70771dSThierry Reding apbdma: dma@60020000 { 27334b4f6d0SThierry Reding compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 27434b4f6d0SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 27534b4f6d0SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 27634b4f6d0SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 27734b4f6d0SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 27834b4f6d0SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 27934b4f6d0SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 28034b4f6d0SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 28134b4f6d0SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 28234b4f6d0SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 28334b4f6d0SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 28434b4f6d0SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 28534b4f6d0SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 28634b4f6d0SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 28734b4f6d0SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 28834b4f6d0SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 28934b4f6d0SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 29034b4f6d0SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 29134b4f6d0SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 29234b4f6d0SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 29334b4f6d0SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 29434b4f6d0SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 29534b4f6d0SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 29634b4f6d0SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 29734b4f6d0SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 29834b4f6d0SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 29934b4f6d0SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 30034b4f6d0SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 30134b4f6d0SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 30234b4f6d0SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 30334b4f6d0SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 30434b4f6d0SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 30534b4f6d0SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 30634b4f6d0SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 30734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 30834b4f6d0SThierry Reding clock-names = "dma"; 30934b4f6d0SThierry Reding resets = <&tegra_car 34>; 31034b4f6d0SThierry Reding reset-names = "dma"; 31134b4f6d0SThierry Reding #dma-cells = <1>; 31234b4f6d0SThierry Reding }; 31334b4f6d0SThierry Reding 314be70771dSThierry Reding apbmisc@70000800 { 31534b4f6d0SThierry Reding compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 31634b4f6d0SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 31734b4f6d0SThierry Reding <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 31834b4f6d0SThierry Reding }; 31934b4f6d0SThierry Reding 320be70771dSThierry Reding pinmux: pinmux@70000868 { 32134b4f6d0SThierry Reding compatible = "nvidia,tegra124-pinmux"; 32234b4f6d0SThierry Reding reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 32334b4f6d0SThierry Reding <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 32434b4f6d0SThierry Reding <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 32534b4f6d0SThierry Reding }; 32634b4f6d0SThierry Reding 32734b4f6d0SThierry Reding /* 32834b4f6d0SThierry Reding * There are two serial driver i.e. 8250 based simple serial 32934b4f6d0SThierry Reding * driver and APB DMA based serial driver for higher baudrate 330ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 33134b4f6d0SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 33268cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 33334b4f6d0SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 33434b4f6d0SThierry Reding */ 335be70771dSThierry Reding uarta: serial@70006000 { 33634b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 33734b4f6d0SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 33834b4f6d0SThierry Reding reg-shift = <2>; 33934b4f6d0SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 34034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTA>; 34134b4f6d0SThierry Reding clock-names = "serial"; 34234b4f6d0SThierry Reding resets = <&tegra_car 6>; 34334b4f6d0SThierry Reding reset-names = "serial"; 34434b4f6d0SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 34534b4f6d0SThierry Reding dma-names = "rx", "tx"; 34634b4f6d0SThierry Reding status = "disabled"; 34734b4f6d0SThierry Reding }; 34834b4f6d0SThierry Reding 349be70771dSThierry Reding uartb: serial@70006040 { 35034b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 35134b4f6d0SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 35234b4f6d0SThierry Reding reg-shift = <2>; 35334b4f6d0SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 35434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTB>; 35534b4f6d0SThierry Reding clock-names = "serial"; 35634b4f6d0SThierry Reding resets = <&tegra_car 7>; 35734b4f6d0SThierry Reding reset-names = "serial"; 35834b4f6d0SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 35934b4f6d0SThierry Reding dma-names = "rx", "tx"; 36034b4f6d0SThierry Reding status = "disabled"; 36134b4f6d0SThierry Reding }; 36234b4f6d0SThierry Reding 363be70771dSThierry Reding uartc: serial@70006200 { 36434b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 36534b4f6d0SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 36634b4f6d0SThierry Reding reg-shift = <2>; 36734b4f6d0SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 36834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTC>; 36934b4f6d0SThierry Reding clock-names = "serial"; 37034b4f6d0SThierry Reding resets = <&tegra_car 55>; 37134b4f6d0SThierry Reding reset-names = "serial"; 37234b4f6d0SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 37334b4f6d0SThierry Reding dma-names = "rx", "tx"; 37434b4f6d0SThierry Reding status = "disabled"; 37534b4f6d0SThierry Reding }; 37634b4f6d0SThierry Reding 377be70771dSThierry Reding uartd: serial@70006300 { 37834b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 37934b4f6d0SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 38034b4f6d0SThierry Reding reg-shift = <2>; 38134b4f6d0SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 38234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTD>; 38334b4f6d0SThierry Reding clock-names = "serial"; 38434b4f6d0SThierry Reding resets = <&tegra_car 65>; 38534b4f6d0SThierry Reding reset-names = "serial"; 38634b4f6d0SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 38734b4f6d0SThierry Reding dma-names = "rx", "tx"; 38834b4f6d0SThierry Reding status = "disabled"; 38934b4f6d0SThierry Reding }; 39034b4f6d0SThierry Reding 391be70771dSThierry Reding pwm: pwm@7000a000 { 39234b4f6d0SThierry Reding compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 39334b4f6d0SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 39434b4f6d0SThierry Reding #pwm-cells = <2>; 39534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PWM>; 39634b4f6d0SThierry Reding resets = <&tegra_car 17>; 39734b4f6d0SThierry Reding reset-names = "pwm"; 39834b4f6d0SThierry Reding status = "disabled"; 39934b4f6d0SThierry Reding }; 40034b4f6d0SThierry Reding 401be70771dSThierry Reding i2c@7000c000 { 40292564257SThierry Reding compatible = "nvidia,tegra124-i2c"; 40334b4f6d0SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 40434b4f6d0SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 40534b4f6d0SThierry Reding #address-cells = <1>; 40634b4f6d0SThierry Reding #size-cells = <0>; 40734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C1>; 40834b4f6d0SThierry Reding clock-names = "div-clk"; 40934b4f6d0SThierry Reding resets = <&tegra_car 12>; 41034b4f6d0SThierry Reding reset-names = "i2c"; 41134b4f6d0SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 41234b4f6d0SThierry Reding dma-names = "rx", "tx"; 41334b4f6d0SThierry Reding status = "disabled"; 41434b4f6d0SThierry Reding }; 41534b4f6d0SThierry Reding 416be70771dSThierry Reding i2c@7000c400 { 41792564257SThierry Reding compatible = "nvidia,tegra124-i2c"; 41834b4f6d0SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 41934b4f6d0SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 42034b4f6d0SThierry Reding #address-cells = <1>; 42134b4f6d0SThierry Reding #size-cells = <0>; 42234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C2>; 42334b4f6d0SThierry Reding clock-names = "div-clk"; 42434b4f6d0SThierry Reding resets = <&tegra_car 54>; 42534b4f6d0SThierry Reding reset-names = "i2c"; 42634b4f6d0SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 42734b4f6d0SThierry Reding dma-names = "rx", "tx"; 42834b4f6d0SThierry Reding status = "disabled"; 42934b4f6d0SThierry Reding }; 43034b4f6d0SThierry Reding 431be70771dSThierry Reding i2c@7000c500 { 43292564257SThierry Reding compatible = "nvidia,tegra124-i2c"; 43334b4f6d0SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 43434b4f6d0SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 43534b4f6d0SThierry Reding #address-cells = <1>; 43634b4f6d0SThierry Reding #size-cells = <0>; 43734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C3>; 43834b4f6d0SThierry Reding clock-names = "div-clk"; 43934b4f6d0SThierry Reding resets = <&tegra_car 67>; 44034b4f6d0SThierry Reding reset-names = "i2c"; 44134b4f6d0SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 44234b4f6d0SThierry Reding dma-names = "rx", "tx"; 44334b4f6d0SThierry Reding status = "disabled"; 44434b4f6d0SThierry Reding }; 44534b4f6d0SThierry Reding 446be70771dSThierry Reding i2c@7000c700 { 44792564257SThierry Reding compatible = "nvidia,tegra124-i2c"; 44834b4f6d0SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 44934b4f6d0SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 45034b4f6d0SThierry Reding #address-cells = <1>; 45134b4f6d0SThierry Reding #size-cells = <0>; 45234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C4>; 45334b4f6d0SThierry Reding clock-names = "div-clk"; 45434b4f6d0SThierry Reding resets = <&tegra_car 103>; 45534b4f6d0SThierry Reding reset-names = "i2c"; 45634b4f6d0SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 45734b4f6d0SThierry Reding dma-names = "rx", "tx"; 45834b4f6d0SThierry Reding status = "disabled"; 45934b4f6d0SThierry Reding }; 46034b4f6d0SThierry Reding 461be70771dSThierry Reding i2c@7000d000 { 46292564257SThierry Reding compatible = "nvidia,tegra124-i2c"; 46334b4f6d0SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 46434b4f6d0SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 46534b4f6d0SThierry Reding #address-cells = <1>; 46634b4f6d0SThierry Reding #size-cells = <0>; 46734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C5>; 46834b4f6d0SThierry Reding clock-names = "div-clk"; 46934b4f6d0SThierry Reding resets = <&tegra_car 47>; 47034b4f6d0SThierry Reding reset-names = "i2c"; 47134b4f6d0SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 47234b4f6d0SThierry Reding dma-names = "rx", "tx"; 47334b4f6d0SThierry Reding status = "disabled"; 47434b4f6d0SThierry Reding }; 47534b4f6d0SThierry Reding 476be70771dSThierry Reding i2c@7000d100 { 47792564257SThierry Reding compatible = "nvidia,tegra124-i2c"; 47834b4f6d0SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 47934b4f6d0SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 48034b4f6d0SThierry Reding #address-cells = <1>; 48134b4f6d0SThierry Reding #size-cells = <0>; 48234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C6>; 48334b4f6d0SThierry Reding clock-names = "div-clk"; 48434b4f6d0SThierry Reding resets = <&tegra_car 166>; 48534b4f6d0SThierry Reding reset-names = "i2c"; 48634b4f6d0SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 48734b4f6d0SThierry Reding dma-names = "rx", "tx"; 48834b4f6d0SThierry Reding status = "disabled"; 48934b4f6d0SThierry Reding }; 49034b4f6d0SThierry Reding 491be70771dSThierry Reding spi@7000d400 { 49234b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 49334b4f6d0SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 49434b4f6d0SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 49534b4f6d0SThierry Reding #address-cells = <1>; 49634b4f6d0SThierry Reding #size-cells = <0>; 49734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC1>; 49834b4f6d0SThierry Reding clock-names = "spi"; 49934b4f6d0SThierry Reding resets = <&tegra_car 41>; 50034b4f6d0SThierry Reding reset-names = "spi"; 50134b4f6d0SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 50234b4f6d0SThierry Reding dma-names = "rx", "tx"; 50334b4f6d0SThierry Reding status = "disabled"; 50434b4f6d0SThierry Reding }; 50534b4f6d0SThierry Reding 506be70771dSThierry Reding spi@7000d600 { 50734b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 50834b4f6d0SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 50934b4f6d0SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 51034b4f6d0SThierry Reding #address-cells = <1>; 51134b4f6d0SThierry Reding #size-cells = <0>; 51234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC2>; 51334b4f6d0SThierry Reding clock-names = "spi"; 51434b4f6d0SThierry Reding resets = <&tegra_car 44>; 51534b4f6d0SThierry Reding reset-names = "spi"; 51634b4f6d0SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 51734b4f6d0SThierry Reding dma-names = "rx", "tx"; 51834b4f6d0SThierry Reding status = "disabled"; 51934b4f6d0SThierry Reding }; 52034b4f6d0SThierry Reding 521be70771dSThierry Reding spi@7000d800 { 52234b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 52334b4f6d0SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 52434b4f6d0SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 52534b4f6d0SThierry Reding #address-cells = <1>; 52634b4f6d0SThierry Reding #size-cells = <0>; 52734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC3>; 52834b4f6d0SThierry Reding clock-names = "spi"; 52934b4f6d0SThierry Reding resets = <&tegra_car 46>; 53034b4f6d0SThierry Reding reset-names = "spi"; 53134b4f6d0SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 53234b4f6d0SThierry Reding dma-names = "rx", "tx"; 53334b4f6d0SThierry Reding status = "disabled"; 53434b4f6d0SThierry Reding }; 53534b4f6d0SThierry Reding 536be70771dSThierry Reding spi@7000da00 { 53734b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 53834b4f6d0SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 53934b4f6d0SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 54034b4f6d0SThierry Reding #address-cells = <1>; 54134b4f6d0SThierry Reding #size-cells = <0>; 54234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC4>; 54334b4f6d0SThierry Reding clock-names = "spi"; 54434b4f6d0SThierry Reding resets = <&tegra_car 68>; 54534b4f6d0SThierry Reding reset-names = "spi"; 54634b4f6d0SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 54734b4f6d0SThierry Reding dma-names = "rx", "tx"; 54834b4f6d0SThierry Reding status = "disabled"; 54934b4f6d0SThierry Reding }; 55034b4f6d0SThierry Reding 551be70771dSThierry Reding spi@7000dc00 { 55234b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 55334b4f6d0SThierry Reding reg = <0x0 0x7000dc00 0x0 0x200>; 55434b4f6d0SThierry Reding interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 55534b4f6d0SThierry Reding #address-cells = <1>; 55634b4f6d0SThierry Reding #size-cells = <0>; 55734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC5>; 55834b4f6d0SThierry Reding clock-names = "spi"; 55934b4f6d0SThierry Reding resets = <&tegra_car 104>; 56034b4f6d0SThierry Reding reset-names = "spi"; 56134b4f6d0SThierry Reding dmas = <&apbdma 27>, <&apbdma 27>; 56234b4f6d0SThierry Reding dma-names = "rx", "tx"; 56334b4f6d0SThierry Reding status = "disabled"; 56434b4f6d0SThierry Reding }; 56534b4f6d0SThierry Reding 566be70771dSThierry Reding spi@7000de00 { 56734b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 56834b4f6d0SThierry Reding reg = <0x0 0x7000de00 0x0 0x200>; 56934b4f6d0SThierry Reding interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 57034b4f6d0SThierry Reding #address-cells = <1>; 57134b4f6d0SThierry Reding #size-cells = <0>; 57234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC6>; 57334b4f6d0SThierry Reding clock-names = "spi"; 57434b4f6d0SThierry Reding resets = <&tegra_car 105>; 57534b4f6d0SThierry Reding reset-names = "spi"; 57634b4f6d0SThierry Reding dmas = <&apbdma 28>, <&apbdma 28>; 57734b4f6d0SThierry Reding dma-names = "rx", "tx"; 57834b4f6d0SThierry Reding status = "disabled"; 57934b4f6d0SThierry Reding }; 58034b4f6d0SThierry Reding 581be70771dSThierry Reding rtc@7000e000 { 58234b4f6d0SThierry Reding compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 58334b4f6d0SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 58434b4f6d0SThierry Reding interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 58534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_RTC>; 58634b4f6d0SThierry Reding clock-names = "rtc"; 58734b4f6d0SThierry Reding }; 58834b4f6d0SThierry Reding 589359ae651SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 59034b4f6d0SThierry Reding compatible = "nvidia,tegra124-pmc"; 59134b4f6d0SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 59234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 59334b4f6d0SThierry Reding clock-names = "pclk", "clk32k_in"; 594359ae651SSowjanya Komatineni #clock-cells = <1>; 59534b4f6d0SThierry Reding }; 59634b4f6d0SThierry Reding 597be70771dSThierry Reding fuse@7000f800 { 59834b4f6d0SThierry Reding compatible = "nvidia,tegra124-efuse"; 59934b4f6d0SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 60034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_FUSE>; 60134b4f6d0SThierry Reding clock-names = "fuse"; 60234b4f6d0SThierry Reding resets = <&tegra_car 39>; 60334b4f6d0SThierry Reding reset-names = "fuse"; 60434b4f6d0SThierry Reding }; 60534b4f6d0SThierry Reding 606be70771dSThierry Reding mc: memory-controller@70019000 { 60734b4f6d0SThierry Reding compatible = "nvidia,tegra132-mc"; 60834b4f6d0SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 60934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_MC>; 61034b4f6d0SThierry Reding clock-names = "mc"; 61134b4f6d0SThierry Reding 61234b4f6d0SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 61334b4f6d0SThierry Reding 61434b4f6d0SThierry Reding #iommu-cells = <1>; 615ed9e9a6eSThierry Reding #reset-cells = <1>; 616ed9e9a6eSThierry Reding #interconnect-cells = <1>; 61734b4f6d0SThierry Reding }; 61834b4f6d0SThierry Reding 61947cd385eSThierry Reding emc: external-memory-controller@7001b000 { 620ed9e9a6eSThierry Reding compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 62134b4f6d0SThierry Reding reg = <0x0 0x7001b000 0x0 0x1000>; 6220bab86abSThierry Reding clocks = <&tegra_car TEGRA124_CLK_EMC>; 6230bab86abSThierry Reding clock-names = "emc"; 62434b4f6d0SThierry Reding 62534b4f6d0SThierry Reding nvidia,memory-controller = <&mc>; 626ed9e9a6eSThierry Reding operating-points-v2 = <&emc_icc_dvfs_opp_table>; 627ed9e9a6eSThierry Reding 628ed9e9a6eSThierry Reding #interconnect-cells = <0>; 62934b4f6d0SThierry Reding }; 63034b4f6d0SThierry Reding 631be70771dSThierry Reding sata@70020000 { 63234b4f6d0SThierry Reding compatible = "nvidia,tegra124-ahci"; 63334b4f6d0SThierry Reding reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 63434b4f6d0SThierry Reding <0x0 0x70020000 0x0 0x7000>; /* SATA */ 63534b4f6d0SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 63634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SATA>, 6379f27a6c4SThierry Reding <&tegra_car TEGRA124_CLK_SATA_OOB>; 6389f27a6c4SThierry Reding clock-names = "sata", "sata-oob"; 63934b4f6d0SThierry Reding resets = <&tegra_car 124>, 640c84ebdfdSSowjanya Komatineni <&tegra_car 129>, 641c84ebdfdSSowjanya Komatineni <&tegra_car 123>; 642c84ebdfdSSowjanya Komatineni reset-names = "sata", "sata-cold", "sata-oob"; 64334b4f6d0SThierry Reding status = "disabled"; 64434b4f6d0SThierry Reding }; 64534b4f6d0SThierry Reding 646be70771dSThierry Reding hda@70030000 { 64734b4f6d0SThierry Reding compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 64834b4f6d0SThierry Reding "nvidia,tegra30-hda"; 64934b4f6d0SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 65034b4f6d0SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 65134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HDA>, 65234b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_HDA2HDMI>, 65334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 65434b4f6d0SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 65534b4f6d0SThierry Reding resets = <&tegra_car 125>, /* hda */ 65634b4f6d0SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 65734b4f6d0SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 65834b4f6d0SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 65934b4f6d0SThierry Reding status = "disabled"; 66034b4f6d0SThierry Reding }; 66134b4f6d0SThierry Reding 662574d9cffSThierry Reding usb@70090000 { 663574d9cffSThierry Reding compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; 664574d9cffSThierry Reding reg = <0x0 0x70090000 0x0 0x8000>, 665574d9cffSThierry Reding <0x0 0x70098000 0x0 0x1000>, 666574d9cffSThierry Reding <0x0 0x70099000 0x0 0x1000>; 667574d9cffSThierry Reding reg-names = "hcd", "fpci", "ipfs"; 668574d9cffSThierry Reding 669574d9cffSThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 670574d9cffSThierry Reding <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 671574d9cffSThierry Reding 672574d9cffSThierry Reding clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 673574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 674574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 675574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_SS>, 676574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 677fce5d073SThierry Reding <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 678574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 679574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 680574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_PLL_U_480M>, 681574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_CLK_M>, 682574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_PLL_E>; 683574d9cffSThierry Reding clock-names = "xusb_host", "xusb_host_src", 684574d9cffSThierry Reding "xusb_falcon_src", "xusb_ss", 685fce5d073SThierry Reding "xusb_ss_div2", "xusb_ss_src", 686574d9cffSThierry Reding "xusb_hs_src", "xusb_fs_src", 687574d9cffSThierry Reding "pll_u_480m", "clk_m", "pll_e"; 688574d9cffSThierry Reding resets = <&tegra_car 89>, <&tegra_car 156>, 689574d9cffSThierry Reding <&tegra_car 143>; 690574d9cffSThierry Reding reset-names = "xusb_host", "xusb_ss", "xusb_src"; 691574d9cffSThierry Reding 692574d9cffSThierry Reding nvidia,xusb-padctl = <&padctl>; 693574d9cffSThierry Reding 694574d9cffSThierry Reding status = "disabled"; 695574d9cffSThierry Reding }; 696574d9cffSThierry Reding 697be70771dSThierry Reding padctl: padctl@7009f000 { 69834b4f6d0SThierry Reding compatible = "nvidia,tegra132-xusb-padctl", 69934b4f6d0SThierry Reding "nvidia,tegra124-xusb-padctl"; 70034b4f6d0SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 70134b4f6d0SThierry Reding resets = <&tegra_car 142>; 70234b4f6d0SThierry Reding reset-names = "padctl"; 70334b4f6d0SThierry Reding 704574d9cffSThierry Reding pads { 705574d9cffSThierry Reding usb2 { 706574d9cffSThierry Reding status = "disabled"; 70734b4f6d0SThierry Reding 708574d9cffSThierry Reding lanes { 709574d9cffSThierry Reding usb2-0 { 710574d9cffSThierry Reding status = "disabled"; 711574d9cffSThierry Reding #phy-cells = <0>; 712574d9cffSThierry Reding }; 713574d9cffSThierry Reding 714574d9cffSThierry Reding usb2-1 { 715574d9cffSThierry Reding status = "disabled"; 716574d9cffSThierry Reding #phy-cells = <0>; 717574d9cffSThierry Reding }; 718574d9cffSThierry Reding 719574d9cffSThierry Reding usb2-2 { 720574d9cffSThierry Reding status = "disabled"; 721574d9cffSThierry Reding #phy-cells = <0>; 722574d9cffSThierry Reding }; 723574d9cffSThierry Reding }; 724574d9cffSThierry Reding }; 725574d9cffSThierry Reding 726574d9cffSThierry Reding ulpi { 727574d9cffSThierry Reding status = "disabled"; 728574d9cffSThierry Reding 729574d9cffSThierry Reding lanes { 730574d9cffSThierry Reding ulpi-0 { 731574d9cffSThierry Reding status = "disabled"; 732574d9cffSThierry Reding #phy-cells = <0>; 733574d9cffSThierry Reding }; 734574d9cffSThierry Reding }; 735574d9cffSThierry Reding }; 736574d9cffSThierry Reding 737574d9cffSThierry Reding hsic { 738574d9cffSThierry Reding status = "disabled"; 739574d9cffSThierry Reding 740574d9cffSThierry Reding lanes { 741574d9cffSThierry Reding hsic-0 { 742574d9cffSThierry Reding status = "disabled"; 743574d9cffSThierry Reding #phy-cells = <0>; 744574d9cffSThierry Reding }; 745574d9cffSThierry Reding 746574d9cffSThierry Reding hsic-1 { 747574d9cffSThierry Reding status = "disabled"; 748574d9cffSThierry Reding #phy-cells = <0>; 749574d9cffSThierry Reding }; 750574d9cffSThierry Reding }; 751574d9cffSThierry Reding }; 752574d9cffSThierry Reding 753574d9cffSThierry Reding pcie { 754574d9cffSThierry Reding status = "disabled"; 755574d9cffSThierry Reding 756574d9cffSThierry Reding lanes { 75734b4f6d0SThierry Reding pcie-0 { 75834b4f6d0SThierry Reding status = "disabled"; 759574d9cffSThierry Reding #phy-cells = <0>; 760574d9cffSThierry Reding }; 761574d9cffSThierry Reding 762574d9cffSThierry Reding pcie-1 { 763574d9cffSThierry Reding status = "disabled"; 764574d9cffSThierry Reding #phy-cells = <0>; 765574d9cffSThierry Reding }; 766574d9cffSThierry Reding 767574d9cffSThierry Reding pcie-2 { 768574d9cffSThierry Reding status = "disabled"; 769574d9cffSThierry Reding #phy-cells = <0>; 770574d9cffSThierry Reding }; 771574d9cffSThierry Reding 772574d9cffSThierry Reding pcie-3 { 773574d9cffSThierry Reding status = "disabled"; 774574d9cffSThierry Reding #phy-cells = <0>; 775574d9cffSThierry Reding }; 776574d9cffSThierry Reding 777574d9cffSThierry Reding pcie-4 { 778574d9cffSThierry Reding status = "disabled"; 779574d9cffSThierry Reding #phy-cells = <0>; 780574d9cffSThierry Reding }; 781574d9cffSThierry Reding }; 782574d9cffSThierry Reding }; 783574d9cffSThierry Reding 784574d9cffSThierry Reding sata { 785574d9cffSThierry Reding status = "disabled"; 786574d9cffSThierry Reding 787574d9cffSThierry Reding lanes { 788574d9cffSThierry Reding sata-0 { 789574d9cffSThierry Reding status = "disabled"; 790574d9cffSThierry Reding #phy-cells = <0>; 791574d9cffSThierry Reding }; 792574d9cffSThierry Reding }; 793574d9cffSThierry Reding }; 794574d9cffSThierry Reding }; 795574d9cffSThierry Reding 796574d9cffSThierry Reding ports { 797574d9cffSThierry Reding usb2-0 { 798574d9cffSThierry Reding status = "disabled"; 79934b4f6d0SThierry Reding }; 80034b4f6d0SThierry Reding 801574d9cffSThierry Reding usb2-1 { 802574d9cffSThierry Reding status = "disabled"; 803574d9cffSThierry Reding }; 804574d9cffSThierry Reding 805574d9cffSThierry Reding usb2-2 { 806574d9cffSThierry Reding status = "disabled"; 807574d9cffSThierry Reding }; 808574d9cffSThierry Reding 809574d9cffSThierry Reding hsic-0 { 810574d9cffSThierry Reding status = "disabled"; 811574d9cffSThierry Reding }; 812574d9cffSThierry Reding 813574d9cffSThierry Reding hsic-1 { 81434b4f6d0SThierry Reding status = "disabled"; 81534b4f6d0SThierry Reding }; 81634b4f6d0SThierry Reding 81734b4f6d0SThierry Reding usb3-0 { 81834b4f6d0SThierry Reding status = "disabled"; 81934b4f6d0SThierry Reding }; 82034b4f6d0SThierry Reding 82134b4f6d0SThierry Reding usb3-1 { 82234b4f6d0SThierry Reding status = "disabled"; 82334b4f6d0SThierry Reding }; 82434b4f6d0SThierry Reding }; 82534b4f6d0SThierry Reding }; 82634b4f6d0SThierry Reding 82767bb17f6SThierry Reding mmc@700b0000 { 82834b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 82934b4f6d0SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 83034b4f6d0SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 83134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 83234b4f6d0SThierry Reding clock-names = "sdhci"; 83334b4f6d0SThierry Reding resets = <&tegra_car 14>; 83434b4f6d0SThierry Reding reset-names = "sdhci"; 83534b4f6d0SThierry Reding status = "disabled"; 83634b4f6d0SThierry Reding }; 83734b4f6d0SThierry Reding 83867bb17f6SThierry Reding mmc@700b0200 { 83934b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 84034b4f6d0SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 84134b4f6d0SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 84234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 84334b4f6d0SThierry Reding clock-names = "sdhci"; 84434b4f6d0SThierry Reding resets = <&tegra_car 9>; 84534b4f6d0SThierry Reding reset-names = "sdhci"; 84634b4f6d0SThierry Reding status = "disabled"; 84734b4f6d0SThierry Reding }; 84834b4f6d0SThierry Reding 84967bb17f6SThierry Reding mmc@700b0400 { 85034b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 85134b4f6d0SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 85234b4f6d0SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 85334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 85434b4f6d0SThierry Reding clock-names = "sdhci"; 85534b4f6d0SThierry Reding resets = <&tegra_car 69>; 85634b4f6d0SThierry Reding reset-names = "sdhci"; 85734b4f6d0SThierry Reding status = "disabled"; 85834b4f6d0SThierry Reding }; 85934b4f6d0SThierry Reding 86067bb17f6SThierry Reding mmc@700b0600 { 86134b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 86234b4f6d0SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 86334b4f6d0SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 86434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 86534b4f6d0SThierry Reding clock-names = "sdhci"; 86634b4f6d0SThierry Reding resets = <&tegra_car 15>; 86734b4f6d0SThierry Reding reset-names = "sdhci"; 86834b4f6d0SThierry Reding status = "disabled"; 86934b4f6d0SThierry Reding }; 87034b4f6d0SThierry Reding 871be70771dSThierry Reding soctherm: thermal-sensor@700e2000 { 8720fa2bfcdSWei Ni compatible = "nvidia,tegra132-soctherm"; 873644c569dSThierry Reding reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ 874644c569dSThierry Reding <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 875f4357938SWei Ni reg-names = "soctherm-reg", "ccroc-reg"; 8761289bd9fSThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 8771289bd9fSThierry Reding <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 8781289bd9fSThierry Reding interrupt-names = "thermal", "edp"; 87934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 88034b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_SOC_THERM>; 88134b4f6d0SThierry Reding clock-names = "tsensor", "soctherm"; 88234b4f6d0SThierry Reding resets = <&tegra_car 78>; 88334b4f6d0SThierry Reding reset-names = "soctherm"; 88434b4f6d0SThierry Reding #thermal-sensor-cells = <1>; 885f4357938SWei Ni 886f4357938SWei Ni throttle-cfgs { 887f4357938SWei Ni throttle_heavy: heavy { 888f4357938SWei Ni nvidia,priority = <100>; 889f4357938SWei Ni nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 890f4357938SWei Ni 891f4357938SWei Ni #cooling-cells = <2>; 892f4357938SWei Ni }; 893f4357938SWei Ni }; 89434b4f6d0SThierry Reding }; 89534b4f6d0SThierry Reding 896be70771dSThierry Reding ahub@70300000 { 89734b4f6d0SThierry Reding compatible = "nvidia,tegra124-ahub"; 89834b4f6d0SThierry Reding reg = <0x0 0x70300000 0x0 0x200>, 89934b4f6d0SThierry Reding <0x0 0x70300800 0x0 0x800>, 90034b4f6d0SThierry Reding <0x0 0x70300200 0x0 0x600>; 90134b4f6d0SThierry Reding interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 90234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 90334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_APBIF>; 90434b4f6d0SThierry Reding clock-names = "d_audio", "apbif"; 90534b4f6d0SThierry Reding resets = <&tegra_car 106>, /* d_audio */ 90634b4f6d0SThierry Reding <&tegra_car 107>, /* apbif */ 90734b4f6d0SThierry Reding <&tegra_car 30>, /* i2s0 */ 90834b4f6d0SThierry Reding <&tegra_car 11>, /* i2s1 */ 90934b4f6d0SThierry Reding <&tegra_car 18>, /* i2s2 */ 91034b4f6d0SThierry Reding <&tegra_car 101>, /* i2s3 */ 91134b4f6d0SThierry Reding <&tegra_car 102>, /* i2s4 */ 91234b4f6d0SThierry Reding <&tegra_car 108>, /* dam0 */ 91334b4f6d0SThierry Reding <&tegra_car 109>, /* dam1 */ 91434b4f6d0SThierry Reding <&tegra_car 110>, /* dam2 */ 91534b4f6d0SThierry Reding <&tegra_car 10>, /* spdif */ 91634b4f6d0SThierry Reding <&tegra_car 153>, /* amx */ 91734b4f6d0SThierry Reding <&tegra_car 185>, /* amx1 */ 91834b4f6d0SThierry Reding <&tegra_car 154>, /* adx */ 91934b4f6d0SThierry Reding <&tegra_car 180>, /* adx1 */ 92034b4f6d0SThierry Reding <&tegra_car 186>, /* afc0 */ 92134b4f6d0SThierry Reding <&tegra_car 187>, /* afc1 */ 92234b4f6d0SThierry Reding <&tegra_car 188>, /* afc2 */ 92334b4f6d0SThierry Reding <&tegra_car 189>, /* afc3 */ 92434b4f6d0SThierry Reding <&tegra_car 190>, /* afc4 */ 92534b4f6d0SThierry Reding <&tegra_car 191>; /* afc5 */ 92634b4f6d0SThierry Reding reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 92734b4f6d0SThierry Reding "i2s3", "i2s4", "dam0", "dam1", "dam2", 92834b4f6d0SThierry Reding "spdif", "amx", "amx1", "adx", "adx1", 92934b4f6d0SThierry Reding "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 93034b4f6d0SThierry Reding dmas = <&apbdma 1>, <&apbdma 1>, 93134b4f6d0SThierry Reding <&apbdma 2>, <&apbdma 2>, 93234b4f6d0SThierry Reding <&apbdma 3>, <&apbdma 3>, 93334b4f6d0SThierry Reding <&apbdma 4>, <&apbdma 4>, 93434b4f6d0SThierry Reding <&apbdma 6>, <&apbdma 6>, 93534b4f6d0SThierry Reding <&apbdma 7>, <&apbdma 7>, 93634b4f6d0SThierry Reding <&apbdma 12>, <&apbdma 12>, 93734b4f6d0SThierry Reding <&apbdma 13>, <&apbdma 13>, 93834b4f6d0SThierry Reding <&apbdma 14>, <&apbdma 14>, 93934b4f6d0SThierry Reding <&apbdma 29>, <&apbdma 29>; 94034b4f6d0SThierry Reding dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 94134b4f6d0SThierry Reding "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 94234b4f6d0SThierry Reding "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 94334b4f6d0SThierry Reding "rx9", "tx9"; 94434b4f6d0SThierry Reding ranges; 94534b4f6d0SThierry Reding #address-cells = <2>; 94634b4f6d0SThierry Reding #size-cells = <2>; 94734b4f6d0SThierry Reding 948be70771dSThierry Reding tegra_i2s0: i2s@70301000 { 94934b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 95034b4f6d0SThierry Reding reg = <0x0 0x70301000 0x0 0x100>; 95134b4f6d0SThierry Reding nvidia,ahub-cif-ids = <4 4>; 95234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S0>; 95334b4f6d0SThierry Reding clock-names = "i2s"; 95434b4f6d0SThierry Reding resets = <&tegra_car 30>; 95534b4f6d0SThierry Reding reset-names = "i2s"; 95634b4f6d0SThierry Reding status = "disabled"; 95734b4f6d0SThierry Reding }; 95834b4f6d0SThierry Reding 959be70771dSThierry Reding tegra_i2s1: i2s@70301100 { 96034b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 96134b4f6d0SThierry Reding reg = <0x0 0x70301100 0x0 0x100>; 96234b4f6d0SThierry Reding nvidia,ahub-cif-ids = <5 5>; 96334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S1>; 96434b4f6d0SThierry Reding clock-names = "i2s"; 96534b4f6d0SThierry Reding resets = <&tegra_car 11>; 96634b4f6d0SThierry Reding reset-names = "i2s"; 96734b4f6d0SThierry Reding status = "disabled"; 96834b4f6d0SThierry Reding }; 96934b4f6d0SThierry Reding 970be70771dSThierry Reding tegra_i2s2: i2s@70301200 { 97134b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 97234b4f6d0SThierry Reding reg = <0x0 0x70301200 0x0 0x100>; 97334b4f6d0SThierry Reding nvidia,ahub-cif-ids = <6 6>; 97434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S2>; 97534b4f6d0SThierry Reding clock-names = "i2s"; 97634b4f6d0SThierry Reding resets = <&tegra_car 18>; 97734b4f6d0SThierry Reding reset-names = "i2s"; 97834b4f6d0SThierry Reding status = "disabled"; 97934b4f6d0SThierry Reding }; 98034b4f6d0SThierry Reding 981be70771dSThierry Reding tegra_i2s3: i2s@70301300 { 98234b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 98334b4f6d0SThierry Reding reg = <0x0 0x70301300 0x0 0x100>; 98434b4f6d0SThierry Reding nvidia,ahub-cif-ids = <7 7>; 98534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S3>; 98634b4f6d0SThierry Reding clock-names = "i2s"; 98734b4f6d0SThierry Reding resets = <&tegra_car 101>; 98834b4f6d0SThierry Reding reset-names = "i2s"; 98934b4f6d0SThierry Reding status = "disabled"; 99034b4f6d0SThierry Reding }; 99134b4f6d0SThierry Reding 992be70771dSThierry Reding tegra_i2s4: i2s@70301400 { 99334b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 99434b4f6d0SThierry Reding reg = <0x0 0x70301400 0x0 0x100>; 99534b4f6d0SThierry Reding nvidia,ahub-cif-ids = <8 8>; 99634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S4>; 99734b4f6d0SThierry Reding clock-names = "i2s"; 99834b4f6d0SThierry Reding resets = <&tegra_car 102>; 99934b4f6d0SThierry Reding reset-names = "i2s"; 100034b4f6d0SThierry Reding status = "disabled"; 100134b4f6d0SThierry Reding }; 100234b4f6d0SThierry Reding }; 100334b4f6d0SThierry Reding 1004be70771dSThierry Reding usb@7d000000 { 100505647401SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 100634b4f6d0SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 100734b4f6d0SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 100834b4f6d0SThierry Reding phy_type = "utmi"; 100934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USBD>; 101034b4f6d0SThierry Reding clock-names = "usb"; 101134b4f6d0SThierry Reding resets = <&tegra_car 22>; 101234b4f6d0SThierry Reding reset-names = "usb"; 101334b4f6d0SThierry Reding nvidia,phy = <&phy1>; 101434b4f6d0SThierry Reding status = "disabled"; 101534b4f6d0SThierry Reding }; 101634b4f6d0SThierry Reding 1017be70771dSThierry Reding phy1: usb-phy@7d000000 { 101834b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 101934b4f6d0SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 102034b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1021212a6aeeSDmitry Osipenko interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 102234b4f6d0SThierry Reding phy_type = "utmi"; 102334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USBD>, 102434b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 102534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 102634b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 102734b4f6d0SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 102834b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 102927e2c657SThierry Reding #phy-cells = <0>; 103034b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 103134b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 103234b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 103334b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 103434b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 103534b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 103634b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 103734b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 103834b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 103934b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 104034b4f6d0SThierry Reding nvidia,has-utmi-pad-registers; 1041212a6aeeSDmitry Osipenko nvidia,pmc = <&tegra_pmc 0>; 104234b4f6d0SThierry Reding status = "disabled"; 104334b4f6d0SThierry Reding }; 104434b4f6d0SThierry Reding 1045be70771dSThierry Reding usb@7d004000 { 104605647401SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 104734b4f6d0SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 104834b4f6d0SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 104934b4f6d0SThierry Reding phy_type = "utmi"; 105034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB2>; 105134b4f6d0SThierry Reding clock-names = "usb"; 105234b4f6d0SThierry Reding resets = <&tegra_car 58>; 105334b4f6d0SThierry Reding reset-names = "usb"; 105434b4f6d0SThierry Reding nvidia,phy = <&phy2>; 105534b4f6d0SThierry Reding status = "disabled"; 105634b4f6d0SThierry Reding }; 105734b4f6d0SThierry Reding 1058be70771dSThierry Reding phy2: usb-phy@7d004000 { 105934b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 106034b4f6d0SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 106134b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1062212a6aeeSDmitry Osipenko interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 106334b4f6d0SThierry Reding phy_type = "utmi"; 106434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB2>, 106534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 106634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 106734b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 106834b4f6d0SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 106934b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 107027e2c657SThierry Reding #phy-cells = <0>; 107134b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 107234b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 107334b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 107434b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 107534b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 107634b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 107734b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 107834b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 107934b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 108034b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 1081212a6aeeSDmitry Osipenko nvidia,pmc = <&tegra_pmc 1>; 108234b4f6d0SThierry Reding status = "disabled"; 108334b4f6d0SThierry Reding }; 108434b4f6d0SThierry Reding 1085be70771dSThierry Reding usb@7d008000 { 108605647401SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 108734b4f6d0SThierry Reding reg = <0x0 0x7d008000 0x0 0x4000>; 108834b4f6d0SThierry Reding interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 108934b4f6d0SThierry Reding phy_type = "utmi"; 109034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB3>; 109134b4f6d0SThierry Reding clock-names = "usb"; 109234b4f6d0SThierry Reding resets = <&tegra_car 59>; 109334b4f6d0SThierry Reding reset-names = "usb"; 109434b4f6d0SThierry Reding nvidia,phy = <&phy3>; 109534b4f6d0SThierry Reding status = "disabled"; 109634b4f6d0SThierry Reding }; 109734b4f6d0SThierry Reding 1098be70771dSThierry Reding phy3: usb-phy@7d008000 { 109934b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 110034b4f6d0SThierry Reding reg = <0x0 0x7d008000 0x0 0x4000>, 110134b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 1102212a6aeeSDmitry Osipenko interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 110334b4f6d0SThierry Reding phy_type = "utmi"; 110434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB3>, 110534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 110634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 110734b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 110834b4f6d0SThierry Reding resets = <&tegra_car 59>, <&tegra_car 22>; 110934b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 111027e2c657SThierry Reding #phy-cells = <0>; 111134b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 111234b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 111334b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 111434b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 111534b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 111634b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 111734b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 111834b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 111934b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 112034b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 1121212a6aeeSDmitry Osipenko nvidia,pmc = <&tegra_pmc 2>; 112234b4f6d0SThierry Reding status = "disabled"; 112334b4f6d0SThierry Reding }; 112434b4f6d0SThierry Reding 112534b4f6d0SThierry Reding cpus { 112634b4f6d0SThierry Reding #address-cells = <1>; 112734b4f6d0SThierry Reding #size-cells = <0>; 112834b4f6d0SThierry Reding 112934b4f6d0SThierry Reding cpu@0 { 113034b4f6d0SThierry Reding device_type = "cpu"; 1131f865d029SThierry Reding compatible = "nvidia,tegra132-denver"; 113234b4f6d0SThierry Reding reg = <0>; 113334b4f6d0SThierry Reding }; 113434b4f6d0SThierry Reding 113534b4f6d0SThierry Reding cpu@1 { 113634b4f6d0SThierry Reding device_type = "cpu"; 1137f865d029SThierry Reding compatible = "nvidia,tegra132-denver"; 113834b4f6d0SThierry Reding reg = <1>; 113934b4f6d0SThierry Reding }; 114034b4f6d0SThierry Reding }; 114134b4f6d0SThierry Reding 1142*79ed18d9SThierry Reding thermal-zones { 1143*79ed18d9SThierry Reding cpu-thermal { 1144*79ed18d9SThierry Reding polling-delay-passive = <1000>; 1145*79ed18d9SThierry Reding polling-delay = <0>; 1146*79ed18d9SThierry Reding 1147*79ed18d9SThierry Reding thermal-sensors = 1148*79ed18d9SThierry Reding <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1149*79ed18d9SThierry Reding 1150*79ed18d9SThierry Reding trips { 1151*79ed18d9SThierry Reding cpu_shutdown_trip { 1152*79ed18d9SThierry Reding temperature = <105000>; 1153*79ed18d9SThierry Reding hysteresis = <1000>; 1154*79ed18d9SThierry Reding type = "critical"; 1155*79ed18d9SThierry Reding }; 1156*79ed18d9SThierry Reding 1157*79ed18d9SThierry Reding cpu_throttle_trip: throttle-trip { 1158*79ed18d9SThierry Reding temperature = <102000>; 1159*79ed18d9SThierry Reding hysteresis = <1000>; 1160*79ed18d9SThierry Reding type = "hot"; 1161*79ed18d9SThierry Reding }; 1162*79ed18d9SThierry Reding }; 1163*79ed18d9SThierry Reding 1164*79ed18d9SThierry Reding cooling-maps { 1165*79ed18d9SThierry Reding map0 { 1166*79ed18d9SThierry Reding trip = <&cpu_throttle_trip>; 1167*79ed18d9SThierry Reding cooling-device = <&throttle_heavy 1 1>; 1168*79ed18d9SThierry Reding }; 1169*79ed18d9SThierry Reding }; 1170*79ed18d9SThierry Reding }; 1171*79ed18d9SThierry Reding 1172*79ed18d9SThierry Reding mem-thermal { 1173*79ed18d9SThierry Reding polling-delay-passive = <0>; 1174*79ed18d9SThierry Reding polling-delay = <0>; 1175*79ed18d9SThierry Reding 1176*79ed18d9SThierry Reding thermal-sensors = 1177*79ed18d9SThierry Reding <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1178*79ed18d9SThierry Reding 1179*79ed18d9SThierry Reding trips { 1180*79ed18d9SThierry Reding mem_shutdown_trip { 1181*79ed18d9SThierry Reding temperature = <101000>; 1182*79ed18d9SThierry Reding hysteresis = <1000>; 1183*79ed18d9SThierry Reding type = "critical"; 1184*79ed18d9SThierry Reding }; 1185*79ed18d9SThierry Reding mem_throttle_trip { 1186*79ed18d9SThierry Reding temperature = <99000>; 1187*79ed18d9SThierry Reding hysteresis = <1000>; 1188*79ed18d9SThierry Reding type = "hot"; 1189*79ed18d9SThierry Reding }; 1190*79ed18d9SThierry Reding }; 1191*79ed18d9SThierry Reding 1192*79ed18d9SThierry Reding cooling-maps { 1193*79ed18d9SThierry Reding /* 1194*79ed18d9SThierry Reding * There are currently no cooling maps, 1195*79ed18d9SThierry Reding * because there are no cooling devices. 1196*79ed18d9SThierry Reding */ 1197*79ed18d9SThierry Reding }; 1198*79ed18d9SThierry Reding }; 1199*79ed18d9SThierry Reding 1200*79ed18d9SThierry Reding gpu-thermal { 1201*79ed18d9SThierry Reding polling-delay-passive = <1000>; 1202*79ed18d9SThierry Reding polling-delay = <0>; 1203*79ed18d9SThierry Reding 1204*79ed18d9SThierry Reding thermal-sensors = 1205*79ed18d9SThierry Reding <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1206*79ed18d9SThierry Reding 1207*79ed18d9SThierry Reding trips { 1208*79ed18d9SThierry Reding gpu_shutdown_trip { 1209*79ed18d9SThierry Reding temperature = <101000>; 1210*79ed18d9SThierry Reding hysteresis = <1000>; 1211*79ed18d9SThierry Reding type = "critical"; 1212*79ed18d9SThierry Reding }; 1213*79ed18d9SThierry Reding 1214*79ed18d9SThierry Reding gpu_throttle_trip: throttle-trip { 1215*79ed18d9SThierry Reding temperature = <99000>; 1216*79ed18d9SThierry Reding hysteresis = <1000>; 1217*79ed18d9SThierry Reding type = "hot"; 1218*79ed18d9SThierry Reding }; 1219*79ed18d9SThierry Reding }; 1220*79ed18d9SThierry Reding 1221*79ed18d9SThierry Reding cooling-maps { 1222*79ed18d9SThierry Reding map0 { 1223*79ed18d9SThierry Reding trip = <&gpu_throttle_trip>; 1224*79ed18d9SThierry Reding cooling-device = <&throttle_heavy 1 1>; 1225*79ed18d9SThierry Reding }; 1226*79ed18d9SThierry Reding }; 1227*79ed18d9SThierry Reding }; 1228*79ed18d9SThierry Reding 1229*79ed18d9SThierry Reding pllx-thermal { 1230*79ed18d9SThierry Reding polling-delay-passive = <0>; 1231*79ed18d9SThierry Reding polling-delay = <0>; 1232*79ed18d9SThierry Reding 1233*79ed18d9SThierry Reding thermal-sensors = 1234*79ed18d9SThierry Reding <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1235*79ed18d9SThierry Reding 1236*79ed18d9SThierry Reding trips { 1237*79ed18d9SThierry Reding pllx_shutdown_trip { 1238*79ed18d9SThierry Reding temperature = <105000>; 1239*79ed18d9SThierry Reding hysteresis = <1000>; 1240*79ed18d9SThierry Reding type = "critical"; 1241*79ed18d9SThierry Reding }; 1242*79ed18d9SThierry Reding pllx_throttle_trip { 1243*79ed18d9SThierry Reding temperature = <99000>; 1244*79ed18d9SThierry Reding hysteresis = <1000>; 1245*79ed18d9SThierry Reding type = "hot"; 1246*79ed18d9SThierry Reding }; 1247*79ed18d9SThierry Reding }; 1248*79ed18d9SThierry Reding 1249*79ed18d9SThierry Reding cooling-maps { 1250*79ed18d9SThierry Reding /* 1251*79ed18d9SThierry Reding * There are currently no cooling maps, 1252*79ed18d9SThierry Reding * because there are no cooling devices. 1253*79ed18d9SThierry Reding */ 1254*79ed18d9SThierry Reding }; 1255*79ed18d9SThierry Reding }; 1256*79ed18d9SThierry Reding }; 1257*79ed18d9SThierry Reding 125834b4f6d0SThierry Reding timer { 125934b4f6d0SThierry Reding compatible = "arm,armv7-timer"; 126034b4f6d0SThierry Reding interrupts = <GIC_PPI 13 126134b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 126234b4f6d0SThierry Reding <GIC_PPI 14 126334b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 126434b4f6d0SThierry Reding <GIC_PPI 11 126534b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 126634b4f6d0SThierry Reding <GIC_PPI 10 126734b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 126834b4f6d0SThierry Reding interrupt-parent = <&gic>; 126934b4f6d0SThierry Reding }; 127034b4f6d0SThierry Reding}; 1271