1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 234b4f6d0SThierry Reding#include <dt-bindings/clock/tegra124-car.h> 334b4f6d0SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 434b4f6d0SThierry Reding#include <dt-bindings/memory/tegra124-mc.h> 534b4f6d0SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 634b4f6d0SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 734b4f6d0SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 80fa2bfcdSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 9359ae651SSowjanya Komatineni#include <dt-bindings/soc/tegra-pmc.h> 1034b4f6d0SThierry Reding 1134b4f6d0SThierry Reding/ { 1234b4f6d0SThierry Reding compatible = "nvidia,tegra132", "nvidia,tegra124"; 1334b4f6d0SThierry Reding interrupt-parent = <&lic>; 1434b4f6d0SThierry Reding #address-cells = <2>; 1534b4f6d0SThierry Reding #size-cells = <2>; 1634b4f6d0SThierry Reding 17475d99fcSRob Herring pcie@1003000 { 1834b4f6d0SThierry Reding compatible = "nvidia,tegra124-pcie"; 1934b4f6d0SThierry Reding device_type = "pci"; 20644c569dSThierry Reding reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 21644c569dSThierry Reding <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 22644c569dSThierry Reding <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 2334b4f6d0SThierry Reding reg-names = "pads", "afi", "cs"; 2434b4f6d0SThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2534b4f6d0SThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2634b4f6d0SThierry Reding interrupt-names = "intr", "msi"; 2734b4f6d0SThierry Reding 2834b4f6d0SThierry Reding #interrupt-cells = <1>; 2934b4f6d0SThierry Reding interrupt-map-mask = <0 0 0 0>; 3034b4f6d0SThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 3134b4f6d0SThierry Reding 3234b4f6d0SThierry Reding bus-range = <0x00 0xff>; 3334b4f6d0SThierry Reding #address-cells = <3>; 3434b4f6d0SThierry Reding #size-cells = <2>; 3534b4f6d0SThierry Reding 36644c569dSThierry Reding ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 37644c569dSThierry Reding <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 38644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 39644c569dSThierry Reding <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 40644c569dSThierry Reding <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 4134b4f6d0SThierry Reding 4234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PCIE>, 4334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_AFI>, 4434b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_E>, 4534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CML0>; 4634b4f6d0SThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 4734b4f6d0SThierry Reding resets = <&tegra_car 70>, 4834b4f6d0SThierry Reding <&tegra_car 72>, 4934b4f6d0SThierry Reding <&tegra_car 74>; 5034b4f6d0SThierry Reding reset-names = "pex", "afi", "pcie_x"; 5134b4f6d0SThierry Reding status = "disabled"; 5234b4f6d0SThierry Reding 5334b4f6d0SThierry Reding pci@1,0 { 5434b4f6d0SThierry Reding device_type = "pci"; 5534b4f6d0SThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 5634b4f6d0SThierry Reding reg = <0x000800 0 0 0 0>; 57475d99fcSRob Herring bus-range = <0x00 0xff>; 5834b4f6d0SThierry Reding status = "disabled"; 5934b4f6d0SThierry Reding 6034b4f6d0SThierry Reding #address-cells = <3>; 6134b4f6d0SThierry Reding #size-cells = <2>; 6234b4f6d0SThierry Reding ranges; 6334b4f6d0SThierry Reding 6434b4f6d0SThierry Reding nvidia,num-lanes = <2>; 6534b4f6d0SThierry Reding }; 6634b4f6d0SThierry Reding 6734b4f6d0SThierry Reding pci@2,0 { 6834b4f6d0SThierry Reding device_type = "pci"; 6934b4f6d0SThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 7034b4f6d0SThierry Reding reg = <0x001000 0 0 0 0>; 71475d99fcSRob Herring bus-range = <0x00 0xff>; 7234b4f6d0SThierry Reding status = "disabled"; 7334b4f6d0SThierry Reding 7434b4f6d0SThierry Reding #address-cells = <3>; 7534b4f6d0SThierry Reding #size-cells = <2>; 7634b4f6d0SThierry Reding ranges; 7734b4f6d0SThierry Reding 7834b4f6d0SThierry Reding nvidia,num-lanes = <1>; 7934b4f6d0SThierry Reding }; 8034b4f6d0SThierry Reding }; 8134b4f6d0SThierry Reding 82be70771dSThierry Reding host1x@50000000 { 8301a9d523SThierry Reding compatible = "nvidia,tegra132-host1x", 84ef126bc4SThierry Reding "nvidia,tegra124-host1x"; 8534b4f6d0SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 8634b4f6d0SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 8734b4f6d0SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 88052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 8934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 9034b4f6d0SThierry Reding clock-names = "host1x"; 9134b4f6d0SThierry Reding resets = <&tegra_car 28>; 9234b4f6d0SThierry Reding reset-names = "host1x"; 9334b4f6d0SThierry Reding 9434b4f6d0SThierry Reding #address-cells = <2>; 9534b4f6d0SThierry Reding #size-cells = <2>; 9634b4f6d0SThierry Reding 9734b4f6d0SThierry Reding ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 9834b4f6d0SThierry Reding 99be70771dSThierry Reding dc@54200000 { 10034b4f6d0SThierry Reding compatible = "nvidia,tegra124-dc"; 10134b4f6d0SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 10234b4f6d0SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 103352092b0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DISP1>; 104352092b0SThierry Reding clock-names = "dc"; 10534b4f6d0SThierry Reding resets = <&tegra_car 27>; 10634b4f6d0SThierry Reding reset-names = "dc"; 10734b4f6d0SThierry Reding 10834b4f6d0SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 10934b4f6d0SThierry Reding 11034b4f6d0SThierry Reding nvidia,head = <0>; 11134b4f6d0SThierry Reding }; 11234b4f6d0SThierry Reding 113be70771dSThierry Reding dc@54240000 { 11434b4f6d0SThierry Reding compatible = "nvidia,tegra124-dc"; 11534b4f6d0SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 11634b4f6d0SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 117352092b0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DISP2>; 118352092b0SThierry Reding clock-names = "dc"; 11934b4f6d0SThierry Reding resets = <&tegra_car 26>; 12034b4f6d0SThierry Reding reset-names = "dc"; 12134b4f6d0SThierry Reding 12234b4f6d0SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 12334b4f6d0SThierry Reding 12434b4f6d0SThierry Reding nvidia,head = <1>; 12534b4f6d0SThierry Reding }; 12634b4f6d0SThierry Reding 127be70771dSThierry Reding hdmi@54280000 { 12834b4f6d0SThierry Reding compatible = "nvidia,tegra124-hdmi"; 12934b4f6d0SThierry Reding reg = <0x0 0x54280000 0x0 0x00040000>; 13034b4f6d0SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 13134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HDMI>, 13234b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 13334b4f6d0SThierry Reding clock-names = "hdmi", "parent"; 13434b4f6d0SThierry Reding resets = <&tegra_car 51>; 13534b4f6d0SThierry Reding reset-names = "hdmi"; 13634b4f6d0SThierry Reding status = "disabled"; 13734b4f6d0SThierry Reding }; 13834b4f6d0SThierry Reding 139be70771dSThierry Reding sor@54540000 { 14034b4f6d0SThierry Reding compatible = "nvidia,tegra124-sor"; 14134b4f6d0SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 14234b4f6d0SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 14334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SOR0>, 144abc9c8a5SThierry Reding <&tegra_car TEGRA124_CLK_SOR0_OUT>, 14534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 14634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_DP>, 14734b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CLK_M>; 148abc9c8a5SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe"; 14934b4f6d0SThierry Reding resets = <&tegra_car 182>; 15034b4f6d0SThierry Reding reset-names = "sor"; 15134b4f6d0SThierry Reding status = "disabled"; 15234b4f6d0SThierry Reding }; 15334b4f6d0SThierry Reding 154be70771dSThierry Reding dpaux: dpaux@545c0000 { 15534b4f6d0SThierry Reding compatible = "nvidia,tegra124-dpaux"; 15634b4f6d0SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 15734b4f6d0SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 15834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 15934b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_DP>; 16034b4f6d0SThierry Reding clock-names = "dpaux", "parent"; 16134b4f6d0SThierry Reding resets = <&tegra_car 181>; 16234b4f6d0SThierry Reding reset-names = "dpaux"; 16334b4f6d0SThierry Reding status = "disabled"; 164997a3b73SThierry Reding 165997a3b73SThierry Reding i2c-bus { 166997a3b73SThierry Reding #address-cells = <1>; 167997a3b73SThierry Reding #size-cells = <0>; 168997a3b73SThierry Reding }; 16934b4f6d0SThierry Reding }; 17034b4f6d0SThierry Reding }; 17134b4f6d0SThierry Reding 172be70771dSThierry Reding gic: interrupt-controller@50041000 { 17334b4f6d0SThierry Reding compatible = "arm,cortex-a15-gic"; 17434b4f6d0SThierry Reding #interrupt-cells = <3>; 17534b4f6d0SThierry Reding interrupt-controller; 17634b4f6d0SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 17734b4f6d0SThierry Reding <0x0 0x50042000 0x0 0x2000>, 17834b4f6d0SThierry Reding <0x0 0x50044000 0x0 0x2000>, 17934b4f6d0SThierry Reding <0x0 0x50046000 0x0 0x2000>; 18034b4f6d0SThierry Reding interrupts = <GIC_PPI 9 18134b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 18234b4f6d0SThierry Reding interrupt-parent = <&gic>; 18334b4f6d0SThierry Reding }; 18434b4f6d0SThierry Reding 185be70771dSThierry Reding gpu@57000000 { 18634b4f6d0SThierry Reding compatible = "nvidia,gk20a"; 18734b4f6d0SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 18834b4f6d0SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 18934b4f6d0SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 19034b4f6d0SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 19134b4f6d0SThierry Reding interrupt-names = "stall", "nonstall"; 19234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_GPU>, 19334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 19434b4f6d0SThierry Reding clock-names = "gpu", "pwr"; 19534b4f6d0SThierry Reding resets = <&tegra_car 184>; 19634b4f6d0SThierry Reding reset-names = "gpu"; 19734b4f6d0SThierry Reding status = "disabled"; 19834b4f6d0SThierry Reding }; 19934b4f6d0SThierry Reding 20034b4f6d0SThierry Reding lic: interrupt-controller@60004000 { 20134b4f6d0SThierry Reding compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 20234b4f6d0SThierry Reding reg = <0x0 0x60004000 0x0 0x100>, 20334b4f6d0SThierry Reding <0x0 0x60004100 0x0 0x100>, 20434b4f6d0SThierry Reding <0x0 0x60004200 0x0 0x100>, 20534b4f6d0SThierry Reding <0x0 0x60004300 0x0 0x100>, 20634b4f6d0SThierry Reding <0x0 0x60004400 0x0 0x100>; 20734b4f6d0SThierry Reding interrupt-controller; 20834b4f6d0SThierry Reding #interrupt-cells = <3>; 20934b4f6d0SThierry Reding interrupt-parent = <&gic>; 21034b4f6d0SThierry Reding }; 21134b4f6d0SThierry Reding 212be70771dSThierry Reding timer@60005000 { 21334b4f6d0SThierry Reding compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 21434b4f6d0SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 21534b4f6d0SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 21634b4f6d0SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 21734b4f6d0SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 21834b4f6d0SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 21934b4f6d0SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 22034b4f6d0SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 22134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_TIMER>; 22234b4f6d0SThierry Reding clock-names = "timer"; 22334b4f6d0SThierry Reding }; 22434b4f6d0SThierry Reding 225be70771dSThierry Reding tegra_car: clock@60006000 { 22634b4f6d0SThierry Reding compatible = "nvidia,tegra132-car"; 22734b4f6d0SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 22834b4f6d0SThierry Reding #clock-cells = <1>; 22934b4f6d0SThierry Reding #reset-cells = <1>; 23034b4f6d0SThierry Reding nvidia,external-memory-controller = <&emc>; 23134b4f6d0SThierry Reding }; 23234b4f6d0SThierry Reding 233be70771dSThierry Reding flow-controller@60007000 { 23418236a14SJon Hunter compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 23534b4f6d0SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 23634b4f6d0SThierry Reding }; 23734b4f6d0SThierry Reding 238be70771dSThierry Reding actmon@6000c800 { 23934b4f6d0SThierry Reding compatible = "nvidia,tegra124-actmon"; 24034b4f6d0SThierry Reding reg = <0x0 0x6000c800 0x0 0x400>; 24134b4f6d0SThierry Reding interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 24234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 24334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_EMC>; 24434b4f6d0SThierry Reding clock-names = "actmon", "emc"; 24534b4f6d0SThierry Reding resets = <&tegra_car 119>; 24634b4f6d0SThierry Reding reset-names = "actmon"; 24734b4f6d0SThierry Reding }; 24834b4f6d0SThierry Reding 249be70771dSThierry Reding gpio: gpio@6000d000 { 25034b4f6d0SThierry Reding compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 25134b4f6d0SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 25234b4f6d0SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 25334b4f6d0SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 25434b4f6d0SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 25534b4f6d0SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 25634b4f6d0SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 25734b4f6d0SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 25834b4f6d0SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 25934b4f6d0SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 26034b4f6d0SThierry Reding #gpio-cells = <2>; 26134b4f6d0SThierry Reding gpio-controller; 26234b4f6d0SThierry Reding #interrupt-cells = <2>; 26334b4f6d0SThierry Reding interrupt-controller; 26434b4f6d0SThierry Reding }; 26534b4f6d0SThierry Reding 266be70771dSThierry Reding apbdma: dma@60020000 { 26734b4f6d0SThierry Reding compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 26834b4f6d0SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 26934b4f6d0SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 27034b4f6d0SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 27134b4f6d0SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 27234b4f6d0SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 27334b4f6d0SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 27434b4f6d0SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 27534b4f6d0SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 27634b4f6d0SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 27734b4f6d0SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 27834b4f6d0SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 27934b4f6d0SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 28034b4f6d0SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 28134b4f6d0SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 28234b4f6d0SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 28334b4f6d0SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 28434b4f6d0SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 28534b4f6d0SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 28634b4f6d0SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 28734b4f6d0SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 28834b4f6d0SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 28934b4f6d0SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 29034b4f6d0SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 29134b4f6d0SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 29234b4f6d0SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 29334b4f6d0SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 29434b4f6d0SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 29534b4f6d0SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 29634b4f6d0SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 29734b4f6d0SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 29834b4f6d0SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 29934b4f6d0SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 30034b4f6d0SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 30134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 30234b4f6d0SThierry Reding clock-names = "dma"; 30334b4f6d0SThierry Reding resets = <&tegra_car 34>; 30434b4f6d0SThierry Reding reset-names = "dma"; 30534b4f6d0SThierry Reding #dma-cells = <1>; 30634b4f6d0SThierry Reding }; 30734b4f6d0SThierry Reding 308be70771dSThierry Reding apbmisc@70000800 { 30934b4f6d0SThierry Reding compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 31034b4f6d0SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 31134b4f6d0SThierry Reding <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 31234b4f6d0SThierry Reding }; 31334b4f6d0SThierry Reding 314be70771dSThierry Reding pinmux: pinmux@70000868 { 31534b4f6d0SThierry Reding compatible = "nvidia,tegra124-pinmux"; 31634b4f6d0SThierry Reding reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 31734b4f6d0SThierry Reding <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 31834b4f6d0SThierry Reding <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 31934b4f6d0SThierry Reding }; 32034b4f6d0SThierry Reding 32134b4f6d0SThierry Reding /* 32234b4f6d0SThierry Reding * There are two serial driver i.e. 8250 based simple serial 32334b4f6d0SThierry Reding * driver and APB DMA based serial driver for higher baudrate 324ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 32534b4f6d0SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 32668cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 32734b4f6d0SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 32834b4f6d0SThierry Reding */ 329be70771dSThierry Reding uarta: serial@70006000 { 33034b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 33134b4f6d0SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 33234b4f6d0SThierry Reding reg-shift = <2>; 33334b4f6d0SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 33434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTA>; 33534b4f6d0SThierry Reding clock-names = "serial"; 33634b4f6d0SThierry Reding resets = <&tegra_car 6>; 33734b4f6d0SThierry Reding reset-names = "serial"; 33834b4f6d0SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 33934b4f6d0SThierry Reding dma-names = "rx", "tx"; 34034b4f6d0SThierry Reding status = "disabled"; 34134b4f6d0SThierry Reding }; 34234b4f6d0SThierry Reding 343be70771dSThierry Reding uartb: serial@70006040 { 34434b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 34534b4f6d0SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 34634b4f6d0SThierry Reding reg-shift = <2>; 34734b4f6d0SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 34834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTB>; 34934b4f6d0SThierry Reding clock-names = "serial"; 35034b4f6d0SThierry Reding resets = <&tegra_car 7>; 35134b4f6d0SThierry Reding reset-names = "serial"; 35234b4f6d0SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 35334b4f6d0SThierry Reding dma-names = "rx", "tx"; 35434b4f6d0SThierry Reding status = "disabled"; 35534b4f6d0SThierry Reding }; 35634b4f6d0SThierry Reding 357be70771dSThierry Reding uartc: serial@70006200 { 35834b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 35934b4f6d0SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 36034b4f6d0SThierry Reding reg-shift = <2>; 36134b4f6d0SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 36234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTC>; 36334b4f6d0SThierry Reding clock-names = "serial"; 36434b4f6d0SThierry Reding resets = <&tegra_car 55>; 36534b4f6d0SThierry Reding reset-names = "serial"; 36634b4f6d0SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 36734b4f6d0SThierry Reding dma-names = "rx", "tx"; 36834b4f6d0SThierry Reding status = "disabled"; 36934b4f6d0SThierry Reding }; 37034b4f6d0SThierry Reding 371be70771dSThierry Reding uartd: serial@70006300 { 37234b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 37334b4f6d0SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 37434b4f6d0SThierry Reding reg-shift = <2>; 37534b4f6d0SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 37634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTD>; 37734b4f6d0SThierry Reding clock-names = "serial"; 37834b4f6d0SThierry Reding resets = <&tegra_car 65>; 37934b4f6d0SThierry Reding reset-names = "serial"; 38034b4f6d0SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 38134b4f6d0SThierry Reding dma-names = "rx", "tx"; 38234b4f6d0SThierry Reding status = "disabled"; 38334b4f6d0SThierry Reding }; 38434b4f6d0SThierry Reding 385be70771dSThierry Reding pwm: pwm@7000a000 { 38634b4f6d0SThierry Reding compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 38734b4f6d0SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 38834b4f6d0SThierry Reding #pwm-cells = <2>; 38934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PWM>; 39034b4f6d0SThierry Reding clock-names = "pwm"; 39134b4f6d0SThierry Reding resets = <&tegra_car 17>; 39234b4f6d0SThierry Reding reset-names = "pwm"; 39334b4f6d0SThierry Reding status = "disabled"; 39434b4f6d0SThierry Reding }; 39534b4f6d0SThierry Reding 396be70771dSThierry Reding i2c@7000c000 { 39734b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 39834b4f6d0SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 39934b4f6d0SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 40034b4f6d0SThierry Reding #address-cells = <1>; 40134b4f6d0SThierry Reding #size-cells = <0>; 40234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C1>; 40334b4f6d0SThierry Reding clock-names = "div-clk"; 40434b4f6d0SThierry Reding resets = <&tegra_car 12>; 40534b4f6d0SThierry Reding reset-names = "i2c"; 40634b4f6d0SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 40734b4f6d0SThierry Reding dma-names = "rx", "tx"; 40834b4f6d0SThierry Reding status = "disabled"; 40934b4f6d0SThierry Reding }; 41034b4f6d0SThierry Reding 411be70771dSThierry Reding i2c@7000c400 { 41234b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 41334b4f6d0SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 41434b4f6d0SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 41534b4f6d0SThierry Reding #address-cells = <1>; 41634b4f6d0SThierry Reding #size-cells = <0>; 41734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C2>; 41834b4f6d0SThierry Reding clock-names = "div-clk"; 41934b4f6d0SThierry Reding resets = <&tegra_car 54>; 42034b4f6d0SThierry Reding reset-names = "i2c"; 42134b4f6d0SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 42234b4f6d0SThierry Reding dma-names = "rx", "tx"; 42334b4f6d0SThierry Reding status = "disabled"; 42434b4f6d0SThierry Reding }; 42534b4f6d0SThierry Reding 426be70771dSThierry Reding i2c@7000c500 { 42734b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 42834b4f6d0SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 42934b4f6d0SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 43034b4f6d0SThierry Reding #address-cells = <1>; 43134b4f6d0SThierry Reding #size-cells = <0>; 43234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C3>; 43334b4f6d0SThierry Reding clock-names = "div-clk"; 43434b4f6d0SThierry Reding resets = <&tegra_car 67>; 43534b4f6d0SThierry Reding reset-names = "i2c"; 43634b4f6d0SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 43734b4f6d0SThierry Reding dma-names = "rx", "tx"; 43834b4f6d0SThierry Reding status = "disabled"; 43934b4f6d0SThierry Reding }; 44034b4f6d0SThierry Reding 441be70771dSThierry Reding i2c@7000c700 { 44234b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 44334b4f6d0SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 44434b4f6d0SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 44534b4f6d0SThierry Reding #address-cells = <1>; 44634b4f6d0SThierry Reding #size-cells = <0>; 44734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C4>; 44834b4f6d0SThierry Reding clock-names = "div-clk"; 44934b4f6d0SThierry Reding resets = <&tegra_car 103>; 45034b4f6d0SThierry Reding reset-names = "i2c"; 45134b4f6d0SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 45234b4f6d0SThierry Reding dma-names = "rx", "tx"; 45334b4f6d0SThierry Reding status = "disabled"; 45434b4f6d0SThierry Reding }; 45534b4f6d0SThierry Reding 456be70771dSThierry Reding i2c@7000d000 { 45734b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 45834b4f6d0SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 45934b4f6d0SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 46034b4f6d0SThierry Reding #address-cells = <1>; 46134b4f6d0SThierry Reding #size-cells = <0>; 46234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C5>; 46334b4f6d0SThierry Reding clock-names = "div-clk"; 46434b4f6d0SThierry Reding resets = <&tegra_car 47>; 46534b4f6d0SThierry Reding reset-names = "i2c"; 46634b4f6d0SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 46734b4f6d0SThierry Reding dma-names = "rx", "tx"; 46834b4f6d0SThierry Reding status = "disabled"; 46934b4f6d0SThierry Reding }; 47034b4f6d0SThierry Reding 471be70771dSThierry Reding i2c@7000d100 { 47234b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 47334b4f6d0SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 47434b4f6d0SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 47534b4f6d0SThierry Reding #address-cells = <1>; 47634b4f6d0SThierry Reding #size-cells = <0>; 47734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C6>; 47834b4f6d0SThierry Reding clock-names = "div-clk"; 47934b4f6d0SThierry Reding resets = <&tegra_car 166>; 48034b4f6d0SThierry Reding reset-names = "i2c"; 48134b4f6d0SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 48234b4f6d0SThierry Reding dma-names = "rx", "tx"; 48334b4f6d0SThierry Reding status = "disabled"; 48434b4f6d0SThierry Reding }; 48534b4f6d0SThierry Reding 486be70771dSThierry Reding spi@7000d400 { 48734b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 48834b4f6d0SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 48934b4f6d0SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 49034b4f6d0SThierry Reding #address-cells = <1>; 49134b4f6d0SThierry Reding #size-cells = <0>; 49234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC1>; 49334b4f6d0SThierry Reding clock-names = "spi"; 49434b4f6d0SThierry Reding resets = <&tegra_car 41>; 49534b4f6d0SThierry Reding reset-names = "spi"; 49634b4f6d0SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 49734b4f6d0SThierry Reding dma-names = "rx", "tx"; 49834b4f6d0SThierry Reding status = "disabled"; 49934b4f6d0SThierry Reding }; 50034b4f6d0SThierry Reding 501be70771dSThierry Reding spi@7000d600 { 50234b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 50334b4f6d0SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 50434b4f6d0SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 50534b4f6d0SThierry Reding #address-cells = <1>; 50634b4f6d0SThierry Reding #size-cells = <0>; 50734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC2>; 50834b4f6d0SThierry Reding clock-names = "spi"; 50934b4f6d0SThierry Reding resets = <&tegra_car 44>; 51034b4f6d0SThierry Reding reset-names = "spi"; 51134b4f6d0SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 51234b4f6d0SThierry Reding dma-names = "rx", "tx"; 51334b4f6d0SThierry Reding status = "disabled"; 51434b4f6d0SThierry Reding }; 51534b4f6d0SThierry Reding 516be70771dSThierry Reding spi@7000d800 { 51734b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 51834b4f6d0SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 51934b4f6d0SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 52034b4f6d0SThierry Reding #address-cells = <1>; 52134b4f6d0SThierry Reding #size-cells = <0>; 52234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC3>; 52334b4f6d0SThierry Reding clock-names = "spi"; 52434b4f6d0SThierry Reding resets = <&tegra_car 46>; 52534b4f6d0SThierry Reding reset-names = "spi"; 52634b4f6d0SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 52734b4f6d0SThierry Reding dma-names = "rx", "tx"; 52834b4f6d0SThierry Reding status = "disabled"; 52934b4f6d0SThierry Reding }; 53034b4f6d0SThierry Reding 531be70771dSThierry Reding spi@7000da00 { 53234b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 53334b4f6d0SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 53434b4f6d0SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 53534b4f6d0SThierry Reding #address-cells = <1>; 53634b4f6d0SThierry Reding #size-cells = <0>; 53734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC4>; 53834b4f6d0SThierry Reding clock-names = "spi"; 53934b4f6d0SThierry Reding resets = <&tegra_car 68>; 54034b4f6d0SThierry Reding reset-names = "spi"; 54134b4f6d0SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 54234b4f6d0SThierry Reding dma-names = "rx", "tx"; 54334b4f6d0SThierry Reding status = "disabled"; 54434b4f6d0SThierry Reding }; 54534b4f6d0SThierry Reding 546be70771dSThierry Reding spi@7000dc00 { 54734b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 54834b4f6d0SThierry Reding reg = <0x0 0x7000dc00 0x0 0x200>; 54934b4f6d0SThierry Reding interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 55034b4f6d0SThierry Reding #address-cells = <1>; 55134b4f6d0SThierry Reding #size-cells = <0>; 55234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC5>; 55334b4f6d0SThierry Reding clock-names = "spi"; 55434b4f6d0SThierry Reding resets = <&tegra_car 104>; 55534b4f6d0SThierry Reding reset-names = "spi"; 55634b4f6d0SThierry Reding dmas = <&apbdma 27>, <&apbdma 27>; 55734b4f6d0SThierry Reding dma-names = "rx", "tx"; 55834b4f6d0SThierry Reding status = "disabled"; 55934b4f6d0SThierry Reding }; 56034b4f6d0SThierry Reding 561be70771dSThierry Reding spi@7000de00 { 56234b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 56334b4f6d0SThierry Reding reg = <0x0 0x7000de00 0x0 0x200>; 56434b4f6d0SThierry Reding interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 56534b4f6d0SThierry Reding #address-cells = <1>; 56634b4f6d0SThierry Reding #size-cells = <0>; 56734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC6>; 56834b4f6d0SThierry Reding clock-names = "spi"; 56934b4f6d0SThierry Reding resets = <&tegra_car 105>; 57034b4f6d0SThierry Reding reset-names = "spi"; 57134b4f6d0SThierry Reding dmas = <&apbdma 28>, <&apbdma 28>; 57234b4f6d0SThierry Reding dma-names = "rx", "tx"; 57334b4f6d0SThierry Reding status = "disabled"; 57434b4f6d0SThierry Reding }; 57534b4f6d0SThierry Reding 576be70771dSThierry Reding rtc@7000e000 { 57734b4f6d0SThierry Reding compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 57834b4f6d0SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 57934b4f6d0SThierry Reding interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 58034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_RTC>; 58134b4f6d0SThierry Reding clock-names = "rtc"; 58234b4f6d0SThierry Reding }; 58334b4f6d0SThierry Reding 584359ae651SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 58534b4f6d0SThierry Reding compatible = "nvidia,tegra124-pmc"; 58634b4f6d0SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 58734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 58834b4f6d0SThierry Reding clock-names = "pclk", "clk32k_in"; 589359ae651SSowjanya Komatineni #clock-cells = <1>; 59034b4f6d0SThierry Reding }; 59134b4f6d0SThierry Reding 592be70771dSThierry Reding fuse@7000f800 { 59334b4f6d0SThierry Reding compatible = "nvidia,tegra124-efuse"; 59434b4f6d0SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 59534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_FUSE>; 59634b4f6d0SThierry Reding clock-names = "fuse"; 59734b4f6d0SThierry Reding resets = <&tegra_car 39>; 59834b4f6d0SThierry Reding reset-names = "fuse"; 59934b4f6d0SThierry Reding }; 60034b4f6d0SThierry Reding 601be70771dSThierry Reding mc: memory-controller@70019000 { 60234b4f6d0SThierry Reding compatible = "nvidia,tegra132-mc"; 60334b4f6d0SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 60434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_MC>; 60534b4f6d0SThierry Reding clock-names = "mc"; 60634b4f6d0SThierry Reding 60734b4f6d0SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 60834b4f6d0SThierry Reding 60934b4f6d0SThierry Reding #iommu-cells = <1>; 61034b4f6d0SThierry Reding }; 61134b4f6d0SThierry Reding 61247cd385eSThierry Reding emc: external-memory-controller@7001b000 { 6134473b1e8SThierry Reding compatible = "nvidia,tegra132-emc"; 61434b4f6d0SThierry Reding reg = <0x0 0x7001b000 0x0 0x1000>; 6150bab86abSThierry Reding clocks = <&tegra_car TEGRA124_CLK_EMC>; 6160bab86abSThierry Reding clock-names = "emc"; 61734b4f6d0SThierry Reding 61834b4f6d0SThierry Reding nvidia,memory-controller = <&mc>; 61934b4f6d0SThierry Reding }; 62034b4f6d0SThierry Reding 621be70771dSThierry Reding sata@70020000 { 62234b4f6d0SThierry Reding compatible = "nvidia,tegra124-ahci"; 62334b4f6d0SThierry Reding reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 62434b4f6d0SThierry Reding <0x0 0x70020000 0x0 0x7000>; /* SATA */ 62534b4f6d0SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 62634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SATA>, 62734b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_SATA_OOB>, 62834b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CML1>, 62934b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_E>; 63034b4f6d0SThierry Reding clock-names = "sata", "sata-oob", "cml1", "pll_e"; 63134b4f6d0SThierry Reding resets = <&tegra_car 124>, 63234b4f6d0SThierry Reding <&tegra_car 123>, 63334b4f6d0SThierry Reding <&tegra_car 129>; 63434b4f6d0SThierry Reding reset-names = "sata", "sata-oob", "sata-cold"; 63534b4f6d0SThierry Reding status = "disabled"; 63634b4f6d0SThierry Reding }; 63734b4f6d0SThierry Reding 638be70771dSThierry Reding hda@70030000 { 63934b4f6d0SThierry Reding compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 64034b4f6d0SThierry Reding "nvidia,tegra30-hda"; 64134b4f6d0SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 64234b4f6d0SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 64334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HDA>, 64434b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_HDA2HDMI>, 64534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 64634b4f6d0SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 64734b4f6d0SThierry Reding resets = <&tegra_car 125>, /* hda */ 64834b4f6d0SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 64934b4f6d0SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 65034b4f6d0SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 65134b4f6d0SThierry Reding status = "disabled"; 65234b4f6d0SThierry Reding }; 65334b4f6d0SThierry Reding 654574d9cffSThierry Reding usb@70090000 { 655574d9cffSThierry Reding compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; 656574d9cffSThierry Reding reg = <0x0 0x70090000 0x0 0x8000>, 657574d9cffSThierry Reding <0x0 0x70098000 0x0 0x1000>, 658574d9cffSThierry Reding <0x0 0x70099000 0x0 0x1000>; 659574d9cffSThierry Reding reg-names = "hcd", "fpci", "ipfs"; 660574d9cffSThierry Reding 661574d9cffSThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 662574d9cffSThierry Reding <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 663574d9cffSThierry Reding 664574d9cffSThierry Reding clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 665574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 666574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 667574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_SS>, 668574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 669574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 670574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 671574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 672574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_PLL_U_480M>, 673574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_CLK_M>, 674574d9cffSThierry Reding <&tegra_car TEGRA124_CLK_PLL_E>; 675574d9cffSThierry Reding clock-names = "xusb_host", "xusb_host_src", 676574d9cffSThierry Reding "xusb_falcon_src", "xusb_ss", 677574d9cffSThierry Reding "xusb_ss_src", "xusb_ss_div2", 678574d9cffSThierry Reding "xusb_hs_src", "xusb_fs_src", 679574d9cffSThierry Reding "pll_u_480m", "clk_m", "pll_e"; 680574d9cffSThierry Reding resets = <&tegra_car 89>, <&tegra_car 156>, 681574d9cffSThierry Reding <&tegra_car 143>; 682574d9cffSThierry Reding reset-names = "xusb_host", "xusb_ss", "xusb_src"; 683574d9cffSThierry Reding 684574d9cffSThierry Reding nvidia,xusb-padctl = <&padctl>; 685574d9cffSThierry Reding 686574d9cffSThierry Reding status = "disabled"; 687574d9cffSThierry Reding }; 688574d9cffSThierry Reding 689be70771dSThierry Reding padctl: padctl@7009f000 { 69034b4f6d0SThierry Reding compatible = "nvidia,tegra132-xusb-padctl", 69134b4f6d0SThierry Reding "nvidia,tegra124-xusb-padctl"; 69234b4f6d0SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 69334b4f6d0SThierry Reding resets = <&tegra_car 142>; 69434b4f6d0SThierry Reding reset-names = "padctl"; 69534b4f6d0SThierry Reding 696574d9cffSThierry Reding pads { 697574d9cffSThierry Reding usb2 { 698574d9cffSThierry Reding status = "disabled"; 69934b4f6d0SThierry Reding 700574d9cffSThierry Reding lanes { 701574d9cffSThierry Reding usb2-0 { 702574d9cffSThierry Reding status = "disabled"; 703574d9cffSThierry Reding #phy-cells = <0>; 704574d9cffSThierry Reding }; 705574d9cffSThierry Reding 706574d9cffSThierry Reding usb2-1 { 707574d9cffSThierry Reding status = "disabled"; 708574d9cffSThierry Reding #phy-cells = <0>; 709574d9cffSThierry Reding }; 710574d9cffSThierry Reding 711574d9cffSThierry Reding usb2-2 { 712574d9cffSThierry Reding status = "disabled"; 713574d9cffSThierry Reding #phy-cells = <0>; 714574d9cffSThierry Reding }; 715574d9cffSThierry Reding }; 716574d9cffSThierry Reding }; 717574d9cffSThierry Reding 718574d9cffSThierry Reding ulpi { 719574d9cffSThierry Reding status = "disabled"; 720574d9cffSThierry Reding 721574d9cffSThierry Reding lanes { 722574d9cffSThierry Reding ulpi-0 { 723574d9cffSThierry Reding status = "disabled"; 724574d9cffSThierry Reding #phy-cells = <0>; 725574d9cffSThierry Reding }; 726574d9cffSThierry Reding }; 727574d9cffSThierry Reding }; 728574d9cffSThierry Reding 729574d9cffSThierry Reding hsic { 730574d9cffSThierry Reding status = "disabled"; 731574d9cffSThierry Reding 732574d9cffSThierry Reding lanes { 733574d9cffSThierry Reding hsic-0 { 734574d9cffSThierry Reding status = "disabled"; 735574d9cffSThierry Reding #phy-cells = <0>; 736574d9cffSThierry Reding }; 737574d9cffSThierry Reding 738574d9cffSThierry Reding hsic-1 { 739574d9cffSThierry Reding status = "disabled"; 740574d9cffSThierry Reding #phy-cells = <0>; 741574d9cffSThierry Reding }; 742574d9cffSThierry Reding }; 743574d9cffSThierry Reding }; 744574d9cffSThierry Reding 745574d9cffSThierry Reding pcie { 746574d9cffSThierry Reding status = "disabled"; 747574d9cffSThierry Reding 748574d9cffSThierry Reding lanes { 74934b4f6d0SThierry Reding pcie-0 { 75034b4f6d0SThierry Reding status = "disabled"; 751574d9cffSThierry Reding #phy-cells = <0>; 752574d9cffSThierry Reding }; 753574d9cffSThierry Reding 754574d9cffSThierry Reding pcie-1 { 755574d9cffSThierry Reding status = "disabled"; 756574d9cffSThierry Reding #phy-cells = <0>; 757574d9cffSThierry Reding }; 758574d9cffSThierry Reding 759574d9cffSThierry Reding pcie-2 { 760574d9cffSThierry Reding status = "disabled"; 761574d9cffSThierry Reding #phy-cells = <0>; 762574d9cffSThierry Reding }; 763574d9cffSThierry Reding 764574d9cffSThierry Reding pcie-3 { 765574d9cffSThierry Reding status = "disabled"; 766574d9cffSThierry Reding #phy-cells = <0>; 767574d9cffSThierry Reding }; 768574d9cffSThierry Reding 769574d9cffSThierry Reding pcie-4 { 770574d9cffSThierry Reding status = "disabled"; 771574d9cffSThierry Reding #phy-cells = <0>; 772574d9cffSThierry Reding }; 773574d9cffSThierry Reding }; 774574d9cffSThierry Reding }; 775574d9cffSThierry Reding 776574d9cffSThierry Reding sata { 777574d9cffSThierry Reding status = "disabled"; 778574d9cffSThierry Reding 779574d9cffSThierry Reding lanes { 780574d9cffSThierry Reding sata-0 { 781574d9cffSThierry Reding status = "disabled"; 782574d9cffSThierry Reding #phy-cells = <0>; 783574d9cffSThierry Reding }; 784574d9cffSThierry Reding }; 785574d9cffSThierry Reding }; 786574d9cffSThierry Reding }; 787574d9cffSThierry Reding 788574d9cffSThierry Reding ports { 789574d9cffSThierry Reding usb2-0 { 790574d9cffSThierry Reding status = "disabled"; 79134b4f6d0SThierry Reding }; 79234b4f6d0SThierry Reding 793574d9cffSThierry Reding usb2-1 { 794574d9cffSThierry Reding status = "disabled"; 795574d9cffSThierry Reding }; 796574d9cffSThierry Reding 797574d9cffSThierry Reding usb2-2 { 798574d9cffSThierry Reding status = "disabled"; 799574d9cffSThierry Reding }; 800574d9cffSThierry Reding 801574d9cffSThierry Reding hsic-0 { 802574d9cffSThierry Reding status = "disabled"; 803574d9cffSThierry Reding }; 804574d9cffSThierry Reding 805574d9cffSThierry Reding hsic-1 { 80634b4f6d0SThierry Reding status = "disabled"; 80734b4f6d0SThierry Reding }; 80834b4f6d0SThierry Reding 80934b4f6d0SThierry Reding usb3-0 { 81034b4f6d0SThierry Reding status = "disabled"; 81134b4f6d0SThierry Reding }; 81234b4f6d0SThierry Reding 81334b4f6d0SThierry Reding usb3-1 { 81434b4f6d0SThierry Reding status = "disabled"; 81534b4f6d0SThierry Reding }; 81634b4f6d0SThierry Reding }; 81734b4f6d0SThierry Reding }; 81834b4f6d0SThierry Reding 81967bb17f6SThierry Reding mmc@700b0000 { 82034b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 82134b4f6d0SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 82234b4f6d0SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 82334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 82434b4f6d0SThierry Reding clock-names = "sdhci"; 82534b4f6d0SThierry Reding resets = <&tegra_car 14>; 82634b4f6d0SThierry Reding reset-names = "sdhci"; 82734b4f6d0SThierry Reding status = "disabled"; 82834b4f6d0SThierry Reding }; 82934b4f6d0SThierry Reding 83067bb17f6SThierry Reding mmc@700b0200 { 83134b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 83234b4f6d0SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 83334b4f6d0SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 83434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 83534b4f6d0SThierry Reding clock-names = "sdhci"; 83634b4f6d0SThierry Reding resets = <&tegra_car 9>; 83734b4f6d0SThierry Reding reset-names = "sdhci"; 83834b4f6d0SThierry Reding status = "disabled"; 83934b4f6d0SThierry Reding }; 84034b4f6d0SThierry Reding 84167bb17f6SThierry Reding mmc@700b0400 { 84234b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 84334b4f6d0SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 84434b4f6d0SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 84534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 84634b4f6d0SThierry Reding clock-names = "sdhci"; 84734b4f6d0SThierry Reding resets = <&tegra_car 69>; 84834b4f6d0SThierry Reding reset-names = "sdhci"; 84934b4f6d0SThierry Reding status = "disabled"; 85034b4f6d0SThierry Reding }; 85134b4f6d0SThierry Reding 85267bb17f6SThierry Reding mmc@700b0600 { 85334b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 85434b4f6d0SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 85534b4f6d0SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 85634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 85734b4f6d0SThierry Reding clock-names = "sdhci"; 85834b4f6d0SThierry Reding resets = <&tegra_car 15>; 85934b4f6d0SThierry Reding reset-names = "sdhci"; 86034b4f6d0SThierry Reding status = "disabled"; 86134b4f6d0SThierry Reding }; 86234b4f6d0SThierry Reding 863be70771dSThierry Reding soctherm: thermal-sensor@700e2000 { 8640fa2bfcdSWei Ni compatible = "nvidia,tegra132-soctherm"; 865644c569dSThierry Reding reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ 866644c569dSThierry Reding <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 867f4357938SWei Ni reg-names = "soctherm-reg", "ccroc-reg"; 86834b4f6d0SThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 86934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 87034b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_SOC_THERM>; 87134b4f6d0SThierry Reding clock-names = "tsensor", "soctherm"; 87234b4f6d0SThierry Reding resets = <&tegra_car 78>; 87334b4f6d0SThierry Reding reset-names = "soctherm"; 87434b4f6d0SThierry Reding #thermal-sensor-cells = <1>; 875f4357938SWei Ni 876f4357938SWei Ni throttle-cfgs { 877f4357938SWei Ni throttle_heavy: heavy { 878f4357938SWei Ni nvidia,priority = <100>; 879f4357938SWei Ni nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 880f4357938SWei Ni 881f4357938SWei Ni #cooling-cells = <2>; 882f4357938SWei Ni }; 883f4357938SWei Ni }; 88434b4f6d0SThierry Reding }; 88534b4f6d0SThierry Reding 8860fa2bfcdSWei Ni thermal-zones { 8870fa2bfcdSWei Ni cpu { 8880fa2bfcdSWei Ni polling-delay-passive = <1000>; 8890fa2bfcdSWei Ni polling-delay = <0>; 8900fa2bfcdSWei Ni 8910fa2bfcdSWei Ni thermal-sensors = 8920fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 893a6ebde25SWei Ni 894a6ebde25SWei Ni trips { 895a6ebde25SWei Ni cpu_shutdown_trip { 896a6ebde25SWei Ni temperature = <105000>; 897a6ebde25SWei Ni hysteresis = <1000>; 898a6ebde25SWei Ni type = "critical"; 899a6ebde25SWei Ni }; 900f4357938SWei Ni 901f4357938SWei Ni cpu_throttle_trip: throttle-trip { 902f4357938SWei Ni temperature = <102000>; 903f4357938SWei Ni hysteresis = <1000>; 904f4357938SWei Ni type = "hot"; 905f4357938SWei Ni }; 906a6ebde25SWei Ni }; 907a6ebde25SWei Ni 908a6ebde25SWei Ni cooling-maps { 909f4357938SWei Ni map0 { 910f4357938SWei Ni trip = <&cpu_throttle_trip>; 911f4357938SWei Ni cooling-device = <&throttle_heavy 1 1>; 912f4357938SWei Ni }; 913a6ebde25SWei Ni }; 9140fa2bfcdSWei Ni }; 9150fa2bfcdSWei Ni mem { 9160fa2bfcdSWei Ni polling-delay-passive = <0>; 9170fa2bfcdSWei Ni polling-delay = <0>; 9180fa2bfcdSWei Ni 9190fa2bfcdSWei Ni thermal-sensors = 9200fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 921a6ebde25SWei Ni 922a6ebde25SWei Ni trips { 923a6ebde25SWei Ni mem_shutdown_trip { 924a6ebde25SWei Ni temperature = <101000>; 925a6ebde25SWei Ni hysteresis = <1000>; 926a6ebde25SWei Ni type = "critical"; 927a6ebde25SWei Ni }; 928*5aaa0de9SNicolas Chauvet mem_throttle_trip { 929*5aaa0de9SNicolas Chauvet temperature = <99000>; 930*5aaa0de9SNicolas Chauvet hysteresis = <1000>; 931*5aaa0de9SNicolas Chauvet type = "hot"; 932*5aaa0de9SNicolas Chauvet }; 933a6ebde25SWei Ni }; 934a6ebde25SWei Ni 935a6ebde25SWei Ni cooling-maps { 936a6ebde25SWei Ni /* 937a6ebde25SWei Ni * There are currently no cooling maps, 938a6ebde25SWei Ni * because there are no cooling devices. 939a6ebde25SWei Ni */ 940a6ebde25SWei Ni }; 9410fa2bfcdSWei Ni }; 9420fa2bfcdSWei Ni gpu { 9430fa2bfcdSWei Ni polling-delay-passive = <1000>; 9440fa2bfcdSWei Ni polling-delay = <0>; 9450fa2bfcdSWei Ni 9460fa2bfcdSWei Ni thermal-sensors = 9470fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 948a6ebde25SWei Ni 949a6ebde25SWei Ni trips { 950a6ebde25SWei Ni gpu_shutdown_trip { 951a6ebde25SWei Ni temperature = <101000>; 952a6ebde25SWei Ni hysteresis = <1000>; 953a6ebde25SWei Ni type = "critical"; 954a6ebde25SWei Ni }; 955f4357938SWei Ni 956f4357938SWei Ni gpu_throttle_trip: throttle-trip { 957f4357938SWei Ni temperature = <99000>; 958f4357938SWei Ni hysteresis = <1000>; 959f4357938SWei Ni type = "hot"; 960f4357938SWei Ni }; 961a6ebde25SWei Ni }; 962a6ebde25SWei Ni 963a6ebde25SWei Ni cooling-maps { 964f4357938SWei Ni map0 { 965f4357938SWei Ni trip = <&gpu_throttle_trip>; 966f4357938SWei Ni cooling-device = <&throttle_heavy 1 1>; 967f4357938SWei Ni }; 968a6ebde25SWei Ni }; 9690fa2bfcdSWei Ni }; 9700fa2bfcdSWei Ni pllx { 9710fa2bfcdSWei Ni polling-delay-passive = <0>; 9720fa2bfcdSWei Ni polling-delay = <0>; 9730fa2bfcdSWei Ni 9740fa2bfcdSWei Ni thermal-sensors = 9750fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 976a6ebde25SWei Ni 977a6ebde25SWei Ni trips { 978a6ebde25SWei Ni pllx_shutdown_trip { 979a6ebde25SWei Ni temperature = <105000>; 980a6ebde25SWei Ni hysteresis = <1000>; 981a6ebde25SWei Ni type = "critical"; 982a6ebde25SWei Ni }; 983*5aaa0de9SNicolas Chauvet pllx_throttle_trip { 984*5aaa0de9SNicolas Chauvet temperature = <99000>; 985*5aaa0de9SNicolas Chauvet hysteresis = <1000>; 986*5aaa0de9SNicolas Chauvet type = "hot"; 987*5aaa0de9SNicolas Chauvet }; 988a6ebde25SWei Ni }; 989a6ebde25SWei Ni 990a6ebde25SWei Ni cooling-maps { 991a6ebde25SWei Ni /* 992a6ebde25SWei Ni * There are currently no cooling maps, 993a6ebde25SWei Ni * because there are no cooling devices. 994a6ebde25SWei Ni */ 995a6ebde25SWei Ni }; 9960fa2bfcdSWei Ni }; 9970fa2bfcdSWei Ni }; 9980fa2bfcdSWei Ni 999be70771dSThierry Reding ahub@70300000 { 100034b4f6d0SThierry Reding compatible = "nvidia,tegra124-ahub"; 100134b4f6d0SThierry Reding reg = <0x0 0x70300000 0x0 0x200>, 100234b4f6d0SThierry Reding <0x0 0x70300800 0x0 0x800>, 100334b4f6d0SThierry Reding <0x0 0x70300200 0x0 0x600>; 100434b4f6d0SThierry Reding interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 100534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 100634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_APBIF>; 100734b4f6d0SThierry Reding clock-names = "d_audio", "apbif"; 100834b4f6d0SThierry Reding resets = <&tegra_car 106>, /* d_audio */ 100934b4f6d0SThierry Reding <&tegra_car 107>, /* apbif */ 101034b4f6d0SThierry Reding <&tegra_car 30>, /* i2s0 */ 101134b4f6d0SThierry Reding <&tegra_car 11>, /* i2s1 */ 101234b4f6d0SThierry Reding <&tegra_car 18>, /* i2s2 */ 101334b4f6d0SThierry Reding <&tegra_car 101>, /* i2s3 */ 101434b4f6d0SThierry Reding <&tegra_car 102>, /* i2s4 */ 101534b4f6d0SThierry Reding <&tegra_car 108>, /* dam0 */ 101634b4f6d0SThierry Reding <&tegra_car 109>, /* dam1 */ 101734b4f6d0SThierry Reding <&tegra_car 110>, /* dam2 */ 101834b4f6d0SThierry Reding <&tegra_car 10>, /* spdif */ 101934b4f6d0SThierry Reding <&tegra_car 153>, /* amx */ 102034b4f6d0SThierry Reding <&tegra_car 185>, /* amx1 */ 102134b4f6d0SThierry Reding <&tegra_car 154>, /* adx */ 102234b4f6d0SThierry Reding <&tegra_car 180>, /* adx1 */ 102334b4f6d0SThierry Reding <&tegra_car 186>, /* afc0 */ 102434b4f6d0SThierry Reding <&tegra_car 187>, /* afc1 */ 102534b4f6d0SThierry Reding <&tegra_car 188>, /* afc2 */ 102634b4f6d0SThierry Reding <&tegra_car 189>, /* afc3 */ 102734b4f6d0SThierry Reding <&tegra_car 190>, /* afc4 */ 102834b4f6d0SThierry Reding <&tegra_car 191>; /* afc5 */ 102934b4f6d0SThierry Reding reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 103034b4f6d0SThierry Reding "i2s3", "i2s4", "dam0", "dam1", "dam2", 103134b4f6d0SThierry Reding "spdif", "amx", "amx1", "adx", "adx1", 103234b4f6d0SThierry Reding "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 103334b4f6d0SThierry Reding dmas = <&apbdma 1>, <&apbdma 1>, 103434b4f6d0SThierry Reding <&apbdma 2>, <&apbdma 2>, 103534b4f6d0SThierry Reding <&apbdma 3>, <&apbdma 3>, 103634b4f6d0SThierry Reding <&apbdma 4>, <&apbdma 4>, 103734b4f6d0SThierry Reding <&apbdma 6>, <&apbdma 6>, 103834b4f6d0SThierry Reding <&apbdma 7>, <&apbdma 7>, 103934b4f6d0SThierry Reding <&apbdma 12>, <&apbdma 12>, 104034b4f6d0SThierry Reding <&apbdma 13>, <&apbdma 13>, 104134b4f6d0SThierry Reding <&apbdma 14>, <&apbdma 14>, 104234b4f6d0SThierry Reding <&apbdma 29>, <&apbdma 29>; 104334b4f6d0SThierry Reding dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 104434b4f6d0SThierry Reding "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 104534b4f6d0SThierry Reding "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 104634b4f6d0SThierry Reding "rx9", "tx9"; 104734b4f6d0SThierry Reding ranges; 104834b4f6d0SThierry Reding #address-cells = <2>; 104934b4f6d0SThierry Reding #size-cells = <2>; 105034b4f6d0SThierry Reding 1051be70771dSThierry Reding tegra_i2s0: i2s@70301000 { 105234b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 105334b4f6d0SThierry Reding reg = <0x0 0x70301000 0x0 0x100>; 105434b4f6d0SThierry Reding nvidia,ahub-cif-ids = <4 4>; 105534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S0>; 105634b4f6d0SThierry Reding clock-names = "i2s"; 105734b4f6d0SThierry Reding resets = <&tegra_car 30>; 105834b4f6d0SThierry Reding reset-names = "i2s"; 105934b4f6d0SThierry Reding status = "disabled"; 106034b4f6d0SThierry Reding }; 106134b4f6d0SThierry Reding 1062be70771dSThierry Reding tegra_i2s1: i2s@70301100 { 106334b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 106434b4f6d0SThierry Reding reg = <0x0 0x70301100 0x0 0x100>; 106534b4f6d0SThierry Reding nvidia,ahub-cif-ids = <5 5>; 106634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S1>; 106734b4f6d0SThierry Reding clock-names = "i2s"; 106834b4f6d0SThierry Reding resets = <&tegra_car 11>; 106934b4f6d0SThierry Reding reset-names = "i2s"; 107034b4f6d0SThierry Reding status = "disabled"; 107134b4f6d0SThierry Reding }; 107234b4f6d0SThierry Reding 1073be70771dSThierry Reding tegra_i2s2: i2s@70301200 { 107434b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 107534b4f6d0SThierry Reding reg = <0x0 0x70301200 0x0 0x100>; 107634b4f6d0SThierry Reding nvidia,ahub-cif-ids = <6 6>; 107734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S2>; 107834b4f6d0SThierry Reding clock-names = "i2s"; 107934b4f6d0SThierry Reding resets = <&tegra_car 18>; 108034b4f6d0SThierry Reding reset-names = "i2s"; 108134b4f6d0SThierry Reding status = "disabled"; 108234b4f6d0SThierry Reding }; 108334b4f6d0SThierry Reding 1084be70771dSThierry Reding tegra_i2s3: i2s@70301300 { 108534b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 108634b4f6d0SThierry Reding reg = <0x0 0x70301300 0x0 0x100>; 108734b4f6d0SThierry Reding nvidia,ahub-cif-ids = <7 7>; 108834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S3>; 108934b4f6d0SThierry Reding clock-names = "i2s"; 109034b4f6d0SThierry Reding resets = <&tegra_car 101>; 109134b4f6d0SThierry Reding reset-names = "i2s"; 109234b4f6d0SThierry Reding status = "disabled"; 109334b4f6d0SThierry Reding }; 109434b4f6d0SThierry Reding 1095be70771dSThierry Reding tegra_i2s4: i2s@70301400 { 109634b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 109734b4f6d0SThierry Reding reg = <0x0 0x70301400 0x0 0x100>; 109834b4f6d0SThierry Reding nvidia,ahub-cif-ids = <8 8>; 109934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S4>; 110034b4f6d0SThierry Reding clock-names = "i2s"; 110134b4f6d0SThierry Reding resets = <&tegra_car 102>; 110234b4f6d0SThierry Reding reset-names = "i2s"; 110334b4f6d0SThierry Reding status = "disabled"; 110434b4f6d0SThierry Reding }; 110534b4f6d0SThierry Reding }; 110634b4f6d0SThierry Reding 1107be70771dSThierry Reding usb@7d000000 { 110834b4f6d0SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 110934b4f6d0SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 111034b4f6d0SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 111134b4f6d0SThierry Reding phy_type = "utmi"; 111234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USBD>; 111334b4f6d0SThierry Reding clock-names = "usb"; 111434b4f6d0SThierry Reding resets = <&tegra_car 22>; 111534b4f6d0SThierry Reding reset-names = "usb"; 111634b4f6d0SThierry Reding nvidia,phy = <&phy1>; 111734b4f6d0SThierry Reding status = "disabled"; 111834b4f6d0SThierry Reding }; 111934b4f6d0SThierry Reding 1120be70771dSThierry Reding phy1: usb-phy@7d000000 { 112134b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 112234b4f6d0SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 112334b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 112434b4f6d0SThierry Reding phy_type = "utmi"; 112534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USBD>, 112634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 112734b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 112834b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 112934b4f6d0SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 113034b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 113127e2c657SThierry Reding #phy-cells = <0>; 113234b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 113334b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 113434b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 113534b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 113634b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 113734b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 113834b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 113934b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 114034b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 114134b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 114234b4f6d0SThierry Reding nvidia,has-utmi-pad-registers; 114334b4f6d0SThierry Reding status = "disabled"; 114434b4f6d0SThierry Reding }; 114534b4f6d0SThierry Reding 1146be70771dSThierry Reding usb@7d004000 { 114734b4f6d0SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 114834b4f6d0SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 114934b4f6d0SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 115034b4f6d0SThierry Reding phy_type = "utmi"; 115134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB2>; 115234b4f6d0SThierry Reding clock-names = "usb"; 115334b4f6d0SThierry Reding resets = <&tegra_car 58>; 115434b4f6d0SThierry Reding reset-names = "usb"; 115534b4f6d0SThierry Reding nvidia,phy = <&phy2>; 115634b4f6d0SThierry Reding status = "disabled"; 115734b4f6d0SThierry Reding }; 115834b4f6d0SThierry Reding 1159be70771dSThierry Reding phy2: usb-phy@7d004000 { 116034b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 116134b4f6d0SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 116234b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 116334b4f6d0SThierry Reding phy_type = "utmi"; 116434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB2>, 116534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 116634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 116734b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 116834b4f6d0SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 116934b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 117027e2c657SThierry Reding #phy-cells = <0>; 117134b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 117234b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 117334b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 117434b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 117534b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 117634b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 117734b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 117834b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 117934b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 118034b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 118134b4f6d0SThierry Reding status = "disabled"; 118234b4f6d0SThierry Reding }; 118334b4f6d0SThierry Reding 1184be70771dSThierry Reding usb@7d008000 { 118534b4f6d0SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 118634b4f6d0SThierry Reding reg = <0x0 0x7d008000 0x0 0x4000>; 118734b4f6d0SThierry Reding interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 118834b4f6d0SThierry Reding phy_type = "utmi"; 118934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB3>; 119034b4f6d0SThierry Reding clock-names = "usb"; 119134b4f6d0SThierry Reding resets = <&tegra_car 59>; 119234b4f6d0SThierry Reding reset-names = "usb"; 119334b4f6d0SThierry Reding nvidia,phy = <&phy3>; 119434b4f6d0SThierry Reding status = "disabled"; 119534b4f6d0SThierry Reding }; 119634b4f6d0SThierry Reding 1197be70771dSThierry Reding phy3: usb-phy@7d008000 { 119834b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 119934b4f6d0SThierry Reding reg = <0x0 0x7d008000 0x0 0x4000>, 120034b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 120134b4f6d0SThierry Reding phy_type = "utmi"; 120234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB3>, 120334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 120434b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 120534b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 120634b4f6d0SThierry Reding resets = <&tegra_car 59>, <&tegra_car 22>; 120734b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 120827e2c657SThierry Reding #phy-cells = <0>; 120934b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 121034b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 121134b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 121234b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 121334b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 121434b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 121534b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 121634b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 121734b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 121834b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 121934b4f6d0SThierry Reding status = "disabled"; 122034b4f6d0SThierry Reding }; 122134b4f6d0SThierry Reding 122234b4f6d0SThierry Reding cpus { 122334b4f6d0SThierry Reding #address-cells = <1>; 122434b4f6d0SThierry Reding #size-cells = <0>; 122534b4f6d0SThierry Reding 122634b4f6d0SThierry Reding cpu@0 { 122734b4f6d0SThierry Reding device_type = "cpu"; 122831af04cdSRob Herring compatible = "nvidia,denver"; 122934b4f6d0SThierry Reding reg = <0>; 123034b4f6d0SThierry Reding }; 123134b4f6d0SThierry Reding 123234b4f6d0SThierry Reding cpu@1 { 123334b4f6d0SThierry Reding device_type = "cpu"; 123431af04cdSRob Herring compatible = "nvidia,denver"; 123534b4f6d0SThierry Reding reg = <1>; 123634b4f6d0SThierry Reding }; 123734b4f6d0SThierry Reding }; 123834b4f6d0SThierry Reding 123934b4f6d0SThierry Reding timer { 124034b4f6d0SThierry Reding compatible = "arm,armv7-timer"; 124134b4f6d0SThierry Reding interrupts = <GIC_PPI 13 124234b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 124334b4f6d0SThierry Reding <GIC_PPI 14 124434b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 124534b4f6d0SThierry Reding <GIC_PPI 11 124634b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 124734b4f6d0SThierry Reding <GIC_PPI 10 124834b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 124934b4f6d0SThierry Reding interrupt-parent = <&gic>; 125034b4f6d0SThierry Reding }; 125134b4f6d0SThierry Reding}; 1252