134b4f6d0SThierry Reding#include <dt-bindings/clock/tegra124-car.h> 234b4f6d0SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 334b4f6d0SThierry Reding#include <dt-bindings/memory/tegra124-mc.h> 434b4f6d0SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 534b4f6d0SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 634b4f6d0SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 70fa2bfcdSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 834b4f6d0SThierry Reding 934b4f6d0SThierry Reding/ { 1034b4f6d0SThierry Reding compatible = "nvidia,tegra132", "nvidia,tegra124"; 1134b4f6d0SThierry Reding interrupt-parent = <&lic>; 1234b4f6d0SThierry Reding #address-cells = <2>; 1334b4f6d0SThierry Reding #size-cells = <2>; 1434b4f6d0SThierry Reding 15475d99fcSRob Herring pcie@1003000 { 1634b4f6d0SThierry Reding compatible = "nvidia,tegra124-pcie"; 1734b4f6d0SThierry Reding device_type = "pci"; 1834b4f6d0SThierry Reding reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 1934b4f6d0SThierry Reding 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 2034b4f6d0SThierry Reding 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 2134b4f6d0SThierry Reding reg-names = "pads", "afi", "cs"; 2234b4f6d0SThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2334b4f6d0SThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2434b4f6d0SThierry Reding interrupt-names = "intr", "msi"; 2534b4f6d0SThierry Reding 2634b4f6d0SThierry Reding #interrupt-cells = <1>; 2734b4f6d0SThierry Reding interrupt-map-mask = <0 0 0 0>; 2834b4f6d0SThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2934b4f6d0SThierry Reding 3034b4f6d0SThierry Reding bus-range = <0x00 0xff>; 3134b4f6d0SThierry Reding #address-cells = <3>; 3234b4f6d0SThierry Reding #size-cells = <2>; 3334b4f6d0SThierry Reding 3434b4f6d0SThierry Reding ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 3534b4f6d0SThierry Reding 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 3634b4f6d0SThierry Reding 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 3734b4f6d0SThierry Reding 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 3834b4f6d0SThierry Reding 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 3934b4f6d0SThierry Reding 4034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PCIE>, 4134b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_AFI>, 4234b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_E>, 4334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CML0>; 4434b4f6d0SThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 4534b4f6d0SThierry Reding resets = <&tegra_car 70>, 4634b4f6d0SThierry Reding <&tegra_car 72>, 4734b4f6d0SThierry Reding <&tegra_car 74>; 4834b4f6d0SThierry Reding reset-names = "pex", "afi", "pcie_x"; 4934b4f6d0SThierry Reding status = "disabled"; 5034b4f6d0SThierry Reding 5134b4f6d0SThierry Reding phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 5234b4f6d0SThierry Reding phy-names = "pcie"; 5334b4f6d0SThierry Reding 5434b4f6d0SThierry Reding pci@1,0 { 5534b4f6d0SThierry Reding device_type = "pci"; 5634b4f6d0SThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 5734b4f6d0SThierry Reding reg = <0x000800 0 0 0 0>; 58475d99fcSRob Herring bus-range = <0x00 0xff>; 5934b4f6d0SThierry Reding status = "disabled"; 6034b4f6d0SThierry Reding 6134b4f6d0SThierry Reding #address-cells = <3>; 6234b4f6d0SThierry Reding #size-cells = <2>; 6334b4f6d0SThierry Reding ranges; 6434b4f6d0SThierry Reding 6534b4f6d0SThierry Reding nvidia,num-lanes = <2>; 6634b4f6d0SThierry Reding }; 6734b4f6d0SThierry Reding 6834b4f6d0SThierry Reding pci@2,0 { 6934b4f6d0SThierry Reding device_type = "pci"; 7034b4f6d0SThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 7134b4f6d0SThierry Reding reg = <0x001000 0 0 0 0>; 72475d99fcSRob Herring bus-range = <0x00 0xff>; 7334b4f6d0SThierry Reding status = "disabled"; 7434b4f6d0SThierry Reding 7534b4f6d0SThierry Reding #address-cells = <3>; 7634b4f6d0SThierry Reding #size-cells = <2>; 7734b4f6d0SThierry Reding ranges; 7834b4f6d0SThierry Reding 7934b4f6d0SThierry Reding nvidia,num-lanes = <1>; 8034b4f6d0SThierry Reding }; 8134b4f6d0SThierry Reding }; 8234b4f6d0SThierry Reding 83be70771dSThierry Reding host1x@50000000 { 8434b4f6d0SThierry Reding compatible = "nvidia,tegra124-host1x", "simple-bus"; 8534b4f6d0SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 8634b4f6d0SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 8734b4f6d0SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 8834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 8934b4f6d0SThierry Reding clock-names = "host1x"; 9034b4f6d0SThierry Reding resets = <&tegra_car 28>; 9134b4f6d0SThierry Reding reset-names = "host1x"; 9234b4f6d0SThierry Reding 9334b4f6d0SThierry Reding #address-cells = <2>; 9434b4f6d0SThierry Reding #size-cells = <2>; 9534b4f6d0SThierry Reding 9634b4f6d0SThierry Reding ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 9734b4f6d0SThierry Reding 98be70771dSThierry Reding dc@54200000 { 9934b4f6d0SThierry Reding compatible = "nvidia,tegra124-dc"; 10034b4f6d0SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 10134b4f6d0SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 10234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DISP1>, 10334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_P>; 10434b4f6d0SThierry Reding clock-names = "dc", "parent"; 10534b4f6d0SThierry Reding resets = <&tegra_car 27>; 10634b4f6d0SThierry Reding reset-names = "dc"; 10734b4f6d0SThierry Reding 10834b4f6d0SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 10934b4f6d0SThierry Reding 11034b4f6d0SThierry Reding nvidia,head = <0>; 11134b4f6d0SThierry Reding }; 11234b4f6d0SThierry Reding 113be70771dSThierry Reding dc@54240000 { 11434b4f6d0SThierry Reding compatible = "nvidia,tegra124-dc"; 11534b4f6d0SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 11634b4f6d0SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 11734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DISP2>, 11834b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_P>; 11934b4f6d0SThierry Reding clock-names = "dc", "parent"; 12034b4f6d0SThierry Reding resets = <&tegra_car 26>; 12134b4f6d0SThierry Reding reset-names = "dc"; 12234b4f6d0SThierry Reding 12334b4f6d0SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 12434b4f6d0SThierry Reding 12534b4f6d0SThierry Reding nvidia,head = <1>; 12634b4f6d0SThierry Reding }; 12734b4f6d0SThierry Reding 128be70771dSThierry Reding hdmi@54280000 { 12934b4f6d0SThierry Reding compatible = "nvidia,tegra124-hdmi"; 13034b4f6d0SThierry Reding reg = <0x0 0x54280000 0x0 0x00040000>; 13134b4f6d0SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 13234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HDMI>, 13334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 13434b4f6d0SThierry Reding clock-names = "hdmi", "parent"; 13534b4f6d0SThierry Reding resets = <&tegra_car 51>; 13634b4f6d0SThierry Reding reset-names = "hdmi"; 13734b4f6d0SThierry Reding status = "disabled"; 13834b4f6d0SThierry Reding }; 13934b4f6d0SThierry Reding 140be70771dSThierry Reding sor@54540000 { 14134b4f6d0SThierry Reding compatible = "nvidia,tegra124-sor"; 14234b4f6d0SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 14334b4f6d0SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 14434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SOR0>, 14534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 14634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_DP>, 14734b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CLK_M>; 14834b4f6d0SThierry Reding clock-names = "sor", "parent", "dp", "safe"; 14934b4f6d0SThierry Reding resets = <&tegra_car 182>; 15034b4f6d0SThierry Reding reset-names = "sor"; 15134b4f6d0SThierry Reding status = "disabled"; 15234b4f6d0SThierry Reding }; 15334b4f6d0SThierry Reding 154be70771dSThierry Reding dpaux: dpaux@545c0000 { 15534b4f6d0SThierry Reding compatible = "nvidia,tegra124-dpaux"; 15634b4f6d0SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 15734b4f6d0SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 15834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 15934b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_DP>; 16034b4f6d0SThierry Reding clock-names = "dpaux", "parent"; 16134b4f6d0SThierry Reding resets = <&tegra_car 181>; 16234b4f6d0SThierry Reding reset-names = "dpaux"; 16334b4f6d0SThierry Reding status = "disabled"; 16434b4f6d0SThierry Reding }; 16534b4f6d0SThierry Reding }; 16634b4f6d0SThierry Reding 167be70771dSThierry Reding gic: interrupt-controller@50041000 { 16834b4f6d0SThierry Reding compatible = "arm,cortex-a15-gic"; 16934b4f6d0SThierry Reding #interrupt-cells = <3>; 17034b4f6d0SThierry Reding interrupt-controller; 17134b4f6d0SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 17234b4f6d0SThierry Reding <0x0 0x50042000 0x0 0x2000>, 17334b4f6d0SThierry Reding <0x0 0x50044000 0x0 0x2000>, 17434b4f6d0SThierry Reding <0x0 0x50046000 0x0 0x2000>; 17534b4f6d0SThierry Reding interrupts = <GIC_PPI 9 17634b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 17734b4f6d0SThierry Reding interrupt-parent = <&gic>; 17834b4f6d0SThierry Reding }; 17934b4f6d0SThierry Reding 180be70771dSThierry Reding gpu@57000000 { 18134b4f6d0SThierry Reding compatible = "nvidia,gk20a"; 18234b4f6d0SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 18334b4f6d0SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 18434b4f6d0SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 18534b4f6d0SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 18634b4f6d0SThierry Reding interrupt-names = "stall", "nonstall"; 18734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_GPU>, 18834b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 18934b4f6d0SThierry Reding clock-names = "gpu", "pwr"; 19034b4f6d0SThierry Reding resets = <&tegra_car 184>; 19134b4f6d0SThierry Reding reset-names = "gpu"; 19234b4f6d0SThierry Reding status = "disabled"; 19334b4f6d0SThierry Reding }; 19434b4f6d0SThierry Reding 19534b4f6d0SThierry Reding lic: interrupt-controller@60004000 { 19634b4f6d0SThierry Reding compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 19734b4f6d0SThierry Reding reg = <0x0 0x60004000 0x0 0x100>, 19834b4f6d0SThierry Reding <0x0 0x60004100 0x0 0x100>, 19934b4f6d0SThierry Reding <0x0 0x60004200 0x0 0x100>, 20034b4f6d0SThierry Reding <0x0 0x60004300 0x0 0x100>, 20134b4f6d0SThierry Reding <0x0 0x60004400 0x0 0x100>; 20234b4f6d0SThierry Reding interrupt-controller; 20334b4f6d0SThierry Reding #interrupt-cells = <3>; 20434b4f6d0SThierry Reding interrupt-parent = <&gic>; 20534b4f6d0SThierry Reding }; 20634b4f6d0SThierry Reding 207be70771dSThierry Reding timer@60005000 { 20834b4f6d0SThierry Reding compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 20934b4f6d0SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 21034b4f6d0SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 21134b4f6d0SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 21234b4f6d0SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 21334b4f6d0SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 21434b4f6d0SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 21534b4f6d0SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 21634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_TIMER>; 21734b4f6d0SThierry Reding clock-names = "timer"; 21834b4f6d0SThierry Reding }; 21934b4f6d0SThierry Reding 220be70771dSThierry Reding tegra_car: clock@60006000 { 22134b4f6d0SThierry Reding compatible = "nvidia,tegra132-car"; 22234b4f6d0SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 22334b4f6d0SThierry Reding #clock-cells = <1>; 22434b4f6d0SThierry Reding #reset-cells = <1>; 22534b4f6d0SThierry Reding nvidia,external-memory-controller = <&emc>; 22634b4f6d0SThierry Reding }; 22734b4f6d0SThierry Reding 228be70771dSThierry Reding flow-controller@60007000 { 22918236a14SJon Hunter compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 23034b4f6d0SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 23134b4f6d0SThierry Reding }; 23234b4f6d0SThierry Reding 233be70771dSThierry Reding actmon@6000c800 { 23434b4f6d0SThierry Reding compatible = "nvidia,tegra124-actmon"; 23534b4f6d0SThierry Reding reg = <0x0 0x6000c800 0x0 0x400>; 23634b4f6d0SThierry Reding interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 23734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 23834b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_EMC>; 23934b4f6d0SThierry Reding clock-names = "actmon", "emc"; 24034b4f6d0SThierry Reding resets = <&tegra_car 119>; 24134b4f6d0SThierry Reding reset-names = "actmon"; 24234b4f6d0SThierry Reding }; 24334b4f6d0SThierry Reding 244be70771dSThierry Reding gpio: gpio@6000d000 { 24534b4f6d0SThierry Reding compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 24634b4f6d0SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 24734b4f6d0SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 24834b4f6d0SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 24934b4f6d0SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 25034b4f6d0SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 25134b4f6d0SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 25234b4f6d0SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 25334b4f6d0SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 25434b4f6d0SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 25534b4f6d0SThierry Reding #gpio-cells = <2>; 25634b4f6d0SThierry Reding gpio-controller; 25734b4f6d0SThierry Reding #interrupt-cells = <2>; 25834b4f6d0SThierry Reding interrupt-controller; 25934b4f6d0SThierry Reding }; 26034b4f6d0SThierry Reding 261be70771dSThierry Reding apbdma: dma@60020000 { 26234b4f6d0SThierry Reding compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 26334b4f6d0SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 26434b4f6d0SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 26534b4f6d0SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 26634b4f6d0SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 26734b4f6d0SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 26834b4f6d0SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 26934b4f6d0SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 27034b4f6d0SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 27134b4f6d0SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 27234b4f6d0SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 27334b4f6d0SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 27434b4f6d0SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 27534b4f6d0SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 27634b4f6d0SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 27734b4f6d0SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 27834b4f6d0SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 27934b4f6d0SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 28034b4f6d0SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 28134b4f6d0SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 28234b4f6d0SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 28334b4f6d0SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 28434b4f6d0SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 28534b4f6d0SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 28634b4f6d0SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 28734b4f6d0SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 28834b4f6d0SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 28934b4f6d0SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 29034b4f6d0SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 29134b4f6d0SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 29234b4f6d0SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 29334b4f6d0SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 29434b4f6d0SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 29534b4f6d0SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 29634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 29734b4f6d0SThierry Reding clock-names = "dma"; 29834b4f6d0SThierry Reding resets = <&tegra_car 34>; 29934b4f6d0SThierry Reding reset-names = "dma"; 30034b4f6d0SThierry Reding #dma-cells = <1>; 30134b4f6d0SThierry Reding }; 30234b4f6d0SThierry Reding 303be70771dSThierry Reding apbmisc@70000800 { 30434b4f6d0SThierry Reding compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 30534b4f6d0SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 30634b4f6d0SThierry Reding <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 30734b4f6d0SThierry Reding }; 30834b4f6d0SThierry Reding 309be70771dSThierry Reding pinmux: pinmux@70000868 { 31034b4f6d0SThierry Reding compatible = "nvidia,tegra124-pinmux"; 31134b4f6d0SThierry Reding reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 31234b4f6d0SThierry Reding <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 31334b4f6d0SThierry Reding <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 31434b4f6d0SThierry Reding }; 31534b4f6d0SThierry Reding 31634b4f6d0SThierry Reding /* 31734b4f6d0SThierry Reding * There are two serial driver i.e. 8250 based simple serial 31834b4f6d0SThierry Reding * driver and APB DMA based serial driver for higher baudrate 319ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 32034b4f6d0SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 32168cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 32234b4f6d0SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 32334b4f6d0SThierry Reding */ 324be70771dSThierry Reding uarta: serial@70006000 { 32534b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 32634b4f6d0SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 32734b4f6d0SThierry Reding reg-shift = <2>; 32834b4f6d0SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 32934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTA>; 33034b4f6d0SThierry Reding clock-names = "serial"; 33134b4f6d0SThierry Reding resets = <&tegra_car 6>; 33234b4f6d0SThierry Reding reset-names = "serial"; 33334b4f6d0SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 33434b4f6d0SThierry Reding dma-names = "rx", "tx"; 33534b4f6d0SThierry Reding status = "disabled"; 33634b4f6d0SThierry Reding }; 33734b4f6d0SThierry Reding 338be70771dSThierry Reding uartb: serial@70006040 { 33934b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 34034b4f6d0SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 34134b4f6d0SThierry Reding reg-shift = <2>; 34234b4f6d0SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 34334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTB>; 34434b4f6d0SThierry Reding clock-names = "serial"; 34534b4f6d0SThierry Reding resets = <&tegra_car 7>; 34634b4f6d0SThierry Reding reset-names = "serial"; 34734b4f6d0SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 34834b4f6d0SThierry Reding dma-names = "rx", "tx"; 34934b4f6d0SThierry Reding status = "disabled"; 35034b4f6d0SThierry Reding }; 35134b4f6d0SThierry Reding 352be70771dSThierry Reding uartc: serial@70006200 { 35334b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 35434b4f6d0SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 35534b4f6d0SThierry Reding reg-shift = <2>; 35634b4f6d0SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 35734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTC>; 35834b4f6d0SThierry Reding clock-names = "serial"; 35934b4f6d0SThierry Reding resets = <&tegra_car 55>; 36034b4f6d0SThierry Reding reset-names = "serial"; 36134b4f6d0SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 36234b4f6d0SThierry Reding dma-names = "rx", "tx"; 36334b4f6d0SThierry Reding status = "disabled"; 36434b4f6d0SThierry Reding }; 36534b4f6d0SThierry Reding 366be70771dSThierry Reding uartd: serial@70006300 { 36734b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 36834b4f6d0SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 36934b4f6d0SThierry Reding reg-shift = <2>; 37034b4f6d0SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 37134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTD>; 37234b4f6d0SThierry Reding clock-names = "serial"; 37334b4f6d0SThierry Reding resets = <&tegra_car 65>; 37434b4f6d0SThierry Reding reset-names = "serial"; 37534b4f6d0SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 37634b4f6d0SThierry Reding dma-names = "rx", "tx"; 37734b4f6d0SThierry Reding status = "disabled"; 37834b4f6d0SThierry Reding }; 37934b4f6d0SThierry Reding 380be70771dSThierry Reding pwm: pwm@7000a000 { 38134b4f6d0SThierry Reding compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 38234b4f6d0SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 38334b4f6d0SThierry Reding #pwm-cells = <2>; 38434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PWM>; 38534b4f6d0SThierry Reding clock-names = "pwm"; 38634b4f6d0SThierry Reding resets = <&tegra_car 17>; 38734b4f6d0SThierry Reding reset-names = "pwm"; 38834b4f6d0SThierry Reding status = "disabled"; 38934b4f6d0SThierry Reding }; 39034b4f6d0SThierry Reding 391be70771dSThierry Reding i2c@7000c000 { 39234b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 39334b4f6d0SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 39434b4f6d0SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 39534b4f6d0SThierry Reding #address-cells = <1>; 39634b4f6d0SThierry Reding #size-cells = <0>; 39734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C1>; 39834b4f6d0SThierry Reding clock-names = "div-clk"; 39934b4f6d0SThierry Reding resets = <&tegra_car 12>; 40034b4f6d0SThierry Reding reset-names = "i2c"; 40134b4f6d0SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 40234b4f6d0SThierry Reding dma-names = "rx", "tx"; 40334b4f6d0SThierry Reding status = "disabled"; 40434b4f6d0SThierry Reding }; 40534b4f6d0SThierry Reding 406be70771dSThierry Reding i2c@7000c400 { 40734b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 40834b4f6d0SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 40934b4f6d0SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 41034b4f6d0SThierry Reding #address-cells = <1>; 41134b4f6d0SThierry Reding #size-cells = <0>; 41234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C2>; 41334b4f6d0SThierry Reding clock-names = "div-clk"; 41434b4f6d0SThierry Reding resets = <&tegra_car 54>; 41534b4f6d0SThierry Reding reset-names = "i2c"; 41634b4f6d0SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 41734b4f6d0SThierry Reding dma-names = "rx", "tx"; 41834b4f6d0SThierry Reding status = "disabled"; 41934b4f6d0SThierry Reding }; 42034b4f6d0SThierry Reding 421be70771dSThierry Reding i2c@7000c500 { 42234b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 42334b4f6d0SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 42434b4f6d0SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 42534b4f6d0SThierry Reding #address-cells = <1>; 42634b4f6d0SThierry Reding #size-cells = <0>; 42734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C3>; 42834b4f6d0SThierry Reding clock-names = "div-clk"; 42934b4f6d0SThierry Reding resets = <&tegra_car 67>; 43034b4f6d0SThierry Reding reset-names = "i2c"; 43134b4f6d0SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 43234b4f6d0SThierry Reding dma-names = "rx", "tx"; 43334b4f6d0SThierry Reding status = "disabled"; 43434b4f6d0SThierry Reding }; 43534b4f6d0SThierry Reding 436be70771dSThierry Reding i2c@7000c700 { 43734b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 43834b4f6d0SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 43934b4f6d0SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 44034b4f6d0SThierry Reding #address-cells = <1>; 44134b4f6d0SThierry Reding #size-cells = <0>; 44234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C4>; 44334b4f6d0SThierry Reding clock-names = "div-clk"; 44434b4f6d0SThierry Reding resets = <&tegra_car 103>; 44534b4f6d0SThierry Reding reset-names = "i2c"; 44634b4f6d0SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 44734b4f6d0SThierry Reding dma-names = "rx", "tx"; 44834b4f6d0SThierry Reding status = "disabled"; 44934b4f6d0SThierry Reding }; 45034b4f6d0SThierry Reding 451be70771dSThierry Reding i2c@7000d000 { 45234b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 45334b4f6d0SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 45434b4f6d0SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 45534b4f6d0SThierry Reding #address-cells = <1>; 45634b4f6d0SThierry Reding #size-cells = <0>; 45734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C5>; 45834b4f6d0SThierry Reding clock-names = "div-clk"; 45934b4f6d0SThierry Reding resets = <&tegra_car 47>; 46034b4f6d0SThierry Reding reset-names = "i2c"; 46134b4f6d0SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 46234b4f6d0SThierry Reding dma-names = "rx", "tx"; 46334b4f6d0SThierry Reding status = "disabled"; 46434b4f6d0SThierry Reding }; 46534b4f6d0SThierry Reding 466be70771dSThierry Reding i2c@7000d100 { 46734b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 46834b4f6d0SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 46934b4f6d0SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 47034b4f6d0SThierry Reding #address-cells = <1>; 47134b4f6d0SThierry Reding #size-cells = <0>; 47234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C6>; 47334b4f6d0SThierry Reding clock-names = "div-clk"; 47434b4f6d0SThierry Reding resets = <&tegra_car 166>; 47534b4f6d0SThierry Reding reset-names = "i2c"; 47634b4f6d0SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 47734b4f6d0SThierry Reding dma-names = "rx", "tx"; 47834b4f6d0SThierry Reding status = "disabled"; 47934b4f6d0SThierry Reding }; 48034b4f6d0SThierry Reding 481be70771dSThierry Reding spi@7000d400 { 48234b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 48334b4f6d0SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 48434b4f6d0SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 48534b4f6d0SThierry Reding #address-cells = <1>; 48634b4f6d0SThierry Reding #size-cells = <0>; 48734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC1>; 48834b4f6d0SThierry Reding clock-names = "spi"; 48934b4f6d0SThierry Reding resets = <&tegra_car 41>; 49034b4f6d0SThierry Reding reset-names = "spi"; 49134b4f6d0SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 49234b4f6d0SThierry Reding dma-names = "rx", "tx"; 49334b4f6d0SThierry Reding status = "disabled"; 49434b4f6d0SThierry Reding }; 49534b4f6d0SThierry Reding 496be70771dSThierry Reding spi@7000d600 { 49734b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 49834b4f6d0SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 49934b4f6d0SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 50034b4f6d0SThierry Reding #address-cells = <1>; 50134b4f6d0SThierry Reding #size-cells = <0>; 50234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC2>; 50334b4f6d0SThierry Reding clock-names = "spi"; 50434b4f6d0SThierry Reding resets = <&tegra_car 44>; 50534b4f6d0SThierry Reding reset-names = "spi"; 50634b4f6d0SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 50734b4f6d0SThierry Reding dma-names = "rx", "tx"; 50834b4f6d0SThierry Reding status = "disabled"; 50934b4f6d0SThierry Reding }; 51034b4f6d0SThierry Reding 511be70771dSThierry Reding spi@7000d800 { 51234b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 51334b4f6d0SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 51434b4f6d0SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 51534b4f6d0SThierry Reding #address-cells = <1>; 51634b4f6d0SThierry Reding #size-cells = <0>; 51734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC3>; 51834b4f6d0SThierry Reding clock-names = "spi"; 51934b4f6d0SThierry Reding resets = <&tegra_car 46>; 52034b4f6d0SThierry Reding reset-names = "spi"; 52134b4f6d0SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 52234b4f6d0SThierry Reding dma-names = "rx", "tx"; 52334b4f6d0SThierry Reding status = "disabled"; 52434b4f6d0SThierry Reding }; 52534b4f6d0SThierry Reding 526be70771dSThierry Reding spi@7000da00 { 52734b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 52834b4f6d0SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 52934b4f6d0SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 53034b4f6d0SThierry Reding #address-cells = <1>; 53134b4f6d0SThierry Reding #size-cells = <0>; 53234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC4>; 53334b4f6d0SThierry Reding clock-names = "spi"; 53434b4f6d0SThierry Reding resets = <&tegra_car 68>; 53534b4f6d0SThierry Reding reset-names = "spi"; 53634b4f6d0SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 53734b4f6d0SThierry Reding dma-names = "rx", "tx"; 53834b4f6d0SThierry Reding status = "disabled"; 53934b4f6d0SThierry Reding }; 54034b4f6d0SThierry Reding 541be70771dSThierry Reding spi@7000dc00 { 54234b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 54334b4f6d0SThierry Reding reg = <0x0 0x7000dc00 0x0 0x200>; 54434b4f6d0SThierry Reding interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 54534b4f6d0SThierry Reding #address-cells = <1>; 54634b4f6d0SThierry Reding #size-cells = <0>; 54734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC5>; 54834b4f6d0SThierry Reding clock-names = "spi"; 54934b4f6d0SThierry Reding resets = <&tegra_car 104>; 55034b4f6d0SThierry Reding reset-names = "spi"; 55134b4f6d0SThierry Reding dmas = <&apbdma 27>, <&apbdma 27>; 55234b4f6d0SThierry Reding dma-names = "rx", "tx"; 55334b4f6d0SThierry Reding status = "disabled"; 55434b4f6d0SThierry Reding }; 55534b4f6d0SThierry Reding 556be70771dSThierry Reding spi@7000de00 { 55734b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 55834b4f6d0SThierry Reding reg = <0x0 0x7000de00 0x0 0x200>; 55934b4f6d0SThierry Reding interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 56034b4f6d0SThierry Reding #address-cells = <1>; 56134b4f6d0SThierry Reding #size-cells = <0>; 56234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC6>; 56334b4f6d0SThierry Reding clock-names = "spi"; 56434b4f6d0SThierry Reding resets = <&tegra_car 105>; 56534b4f6d0SThierry Reding reset-names = "spi"; 56634b4f6d0SThierry Reding dmas = <&apbdma 28>, <&apbdma 28>; 56734b4f6d0SThierry Reding dma-names = "rx", "tx"; 56834b4f6d0SThierry Reding status = "disabled"; 56934b4f6d0SThierry Reding }; 57034b4f6d0SThierry Reding 571be70771dSThierry Reding rtc@7000e000 { 57234b4f6d0SThierry Reding compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 57334b4f6d0SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 57434b4f6d0SThierry Reding interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 57534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_RTC>; 57634b4f6d0SThierry Reding clock-names = "rtc"; 57734b4f6d0SThierry Reding }; 57834b4f6d0SThierry Reding 579be70771dSThierry Reding pmc@7000e400 { 58034b4f6d0SThierry Reding compatible = "nvidia,tegra124-pmc"; 58134b4f6d0SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 58234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 58334b4f6d0SThierry Reding clock-names = "pclk", "clk32k_in"; 58434b4f6d0SThierry Reding }; 58534b4f6d0SThierry Reding 586be70771dSThierry Reding fuse@7000f800 { 58734b4f6d0SThierry Reding compatible = "nvidia,tegra124-efuse"; 58834b4f6d0SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 58934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_FUSE>; 59034b4f6d0SThierry Reding clock-names = "fuse"; 59134b4f6d0SThierry Reding resets = <&tegra_car 39>; 59234b4f6d0SThierry Reding reset-names = "fuse"; 59334b4f6d0SThierry Reding }; 59434b4f6d0SThierry Reding 595be70771dSThierry Reding mc: memory-controller@70019000 { 59634b4f6d0SThierry Reding compatible = "nvidia,tegra132-mc"; 59734b4f6d0SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 59834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_MC>; 59934b4f6d0SThierry Reding clock-names = "mc"; 60034b4f6d0SThierry Reding 60134b4f6d0SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 60234b4f6d0SThierry Reding 60334b4f6d0SThierry Reding #iommu-cells = <1>; 60434b4f6d0SThierry Reding }; 60534b4f6d0SThierry Reding 606be70771dSThierry Reding emc: emc@7001b000 { 60734b4f6d0SThierry Reding compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 60834b4f6d0SThierry Reding reg = <0x0 0x7001b000 0x0 0x1000>; 60934b4f6d0SThierry Reding 61034b4f6d0SThierry Reding nvidia,memory-controller = <&mc>; 61134b4f6d0SThierry Reding }; 61234b4f6d0SThierry Reding 613be70771dSThierry Reding sata@70020000 { 61434b4f6d0SThierry Reding compatible = "nvidia,tegra124-ahci"; 61534b4f6d0SThierry Reding reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 61634b4f6d0SThierry Reding <0x0 0x70020000 0x0 0x7000>; /* SATA */ 61734b4f6d0SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 61834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SATA>, 61934b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_SATA_OOB>, 62034b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CML1>, 62134b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_E>; 62234b4f6d0SThierry Reding clock-names = "sata", "sata-oob", "cml1", "pll_e"; 62334b4f6d0SThierry Reding resets = <&tegra_car 124>, 62434b4f6d0SThierry Reding <&tegra_car 123>, 62534b4f6d0SThierry Reding <&tegra_car 129>; 62634b4f6d0SThierry Reding reset-names = "sata", "sata-oob", "sata-cold"; 62734b4f6d0SThierry Reding phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 62834b4f6d0SThierry Reding phy-names = "sata-phy"; 62934b4f6d0SThierry Reding status = "disabled"; 63034b4f6d0SThierry Reding }; 63134b4f6d0SThierry Reding 632be70771dSThierry Reding hda@70030000 { 63334b4f6d0SThierry Reding compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 63434b4f6d0SThierry Reding "nvidia,tegra30-hda"; 63534b4f6d0SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 63634b4f6d0SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 63734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HDA>, 63834b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_HDA2HDMI>, 63934b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 64034b4f6d0SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 64134b4f6d0SThierry Reding resets = <&tegra_car 125>, /* hda */ 64234b4f6d0SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 64334b4f6d0SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 64434b4f6d0SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 64534b4f6d0SThierry Reding status = "disabled"; 64634b4f6d0SThierry Reding }; 64734b4f6d0SThierry Reding 648be70771dSThierry Reding padctl: padctl@7009f000 { 64934b4f6d0SThierry Reding compatible = "nvidia,tegra132-xusb-padctl", 65034b4f6d0SThierry Reding "nvidia,tegra124-xusb-padctl"; 65134b4f6d0SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 65234b4f6d0SThierry Reding resets = <&tegra_car 142>; 65334b4f6d0SThierry Reding reset-names = "padctl"; 65434b4f6d0SThierry Reding 65534b4f6d0SThierry Reding #phy-cells = <1>; 65634b4f6d0SThierry Reding 65734b4f6d0SThierry Reding phys { 65834b4f6d0SThierry Reding pcie-0 { 65934b4f6d0SThierry Reding status = "disabled"; 66034b4f6d0SThierry Reding }; 66134b4f6d0SThierry Reding 66234b4f6d0SThierry Reding sata-0 { 66334b4f6d0SThierry Reding status = "disabled"; 66434b4f6d0SThierry Reding }; 66534b4f6d0SThierry Reding 66634b4f6d0SThierry Reding usb3-0 { 66734b4f6d0SThierry Reding status = "disabled"; 66834b4f6d0SThierry Reding }; 66934b4f6d0SThierry Reding 67034b4f6d0SThierry Reding usb3-1 { 67134b4f6d0SThierry Reding status = "disabled"; 67234b4f6d0SThierry Reding }; 67334b4f6d0SThierry Reding 67434b4f6d0SThierry Reding utmi-0 { 67534b4f6d0SThierry Reding status = "disabled"; 67634b4f6d0SThierry Reding }; 67734b4f6d0SThierry Reding 67834b4f6d0SThierry Reding utmi-1 { 67934b4f6d0SThierry Reding status = "disabled"; 68034b4f6d0SThierry Reding }; 68134b4f6d0SThierry Reding 68234b4f6d0SThierry Reding utmi-2 { 68334b4f6d0SThierry Reding status = "disabled"; 68434b4f6d0SThierry Reding }; 68534b4f6d0SThierry Reding }; 68634b4f6d0SThierry Reding }; 68734b4f6d0SThierry Reding 688be70771dSThierry Reding sdhci@700b0000 { 68934b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 69034b4f6d0SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 69134b4f6d0SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 69234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 69334b4f6d0SThierry Reding clock-names = "sdhci"; 69434b4f6d0SThierry Reding resets = <&tegra_car 14>; 69534b4f6d0SThierry Reding reset-names = "sdhci"; 69634b4f6d0SThierry Reding status = "disabled"; 69734b4f6d0SThierry Reding }; 69834b4f6d0SThierry Reding 699be70771dSThierry Reding sdhci@700b0200 { 70034b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 70134b4f6d0SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 70234b4f6d0SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 70334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 70434b4f6d0SThierry Reding clock-names = "sdhci"; 70534b4f6d0SThierry Reding resets = <&tegra_car 9>; 70634b4f6d0SThierry Reding reset-names = "sdhci"; 70734b4f6d0SThierry Reding status = "disabled"; 70834b4f6d0SThierry Reding }; 70934b4f6d0SThierry Reding 710be70771dSThierry Reding sdhci@700b0400 { 71134b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 71234b4f6d0SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 71334b4f6d0SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 71434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 71534b4f6d0SThierry Reding clock-names = "sdhci"; 71634b4f6d0SThierry Reding resets = <&tegra_car 69>; 71734b4f6d0SThierry Reding reset-names = "sdhci"; 71834b4f6d0SThierry Reding status = "disabled"; 71934b4f6d0SThierry Reding }; 72034b4f6d0SThierry Reding 721be70771dSThierry Reding sdhci@700b0600 { 72234b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 72334b4f6d0SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 72434b4f6d0SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 72534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 72634b4f6d0SThierry Reding clock-names = "sdhci"; 72734b4f6d0SThierry Reding resets = <&tegra_car 15>; 72834b4f6d0SThierry Reding reset-names = "sdhci"; 72934b4f6d0SThierry Reding status = "disabled"; 73034b4f6d0SThierry Reding }; 73134b4f6d0SThierry Reding 732be70771dSThierry Reding soctherm: thermal-sensor@700e2000 { 7330fa2bfcdSWei Ni compatible = "nvidia,tegra132-soctherm"; 734f4357938SWei Ni reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */ 735f4357938SWei Ni 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 736f4357938SWei Ni reg-names = "soctherm-reg", "ccroc-reg"; 73734b4f6d0SThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 73834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 73934b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_SOC_THERM>; 74034b4f6d0SThierry Reding clock-names = "tsensor", "soctherm"; 74134b4f6d0SThierry Reding resets = <&tegra_car 78>; 74234b4f6d0SThierry Reding reset-names = "soctherm"; 74334b4f6d0SThierry Reding #thermal-sensor-cells = <1>; 744f4357938SWei Ni 745f4357938SWei Ni throttle-cfgs { 746f4357938SWei Ni throttle_heavy: heavy { 747f4357938SWei Ni nvidia,priority = <100>; 748f4357938SWei Ni nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 749f4357938SWei Ni 750f4357938SWei Ni #cooling-cells = <2>; 751f4357938SWei Ni }; 752f4357938SWei Ni }; 75334b4f6d0SThierry Reding }; 75434b4f6d0SThierry Reding 7550fa2bfcdSWei Ni thermal-zones { 7560fa2bfcdSWei Ni cpu { 7570fa2bfcdSWei Ni polling-delay-passive = <1000>; 7580fa2bfcdSWei Ni polling-delay = <0>; 7590fa2bfcdSWei Ni 7600fa2bfcdSWei Ni thermal-sensors = 7610fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 762a6ebde25SWei Ni 763a6ebde25SWei Ni trips { 764a6ebde25SWei Ni cpu_shutdown_trip { 765a6ebde25SWei Ni temperature = <105000>; 766a6ebde25SWei Ni hysteresis = <1000>; 767a6ebde25SWei Ni type = "critical"; 768a6ebde25SWei Ni }; 769f4357938SWei Ni 770f4357938SWei Ni cpu_throttle_trip: throttle-trip { 771f4357938SWei Ni temperature = <102000>; 772f4357938SWei Ni hysteresis = <1000>; 773f4357938SWei Ni type = "hot"; 774f4357938SWei Ni }; 775a6ebde25SWei Ni }; 776a6ebde25SWei Ni 777a6ebde25SWei Ni cooling-maps { 778f4357938SWei Ni map0 { 779f4357938SWei Ni trip = <&cpu_throttle_trip>; 780f4357938SWei Ni cooling-device = <&throttle_heavy 1 1>; 781f4357938SWei Ni }; 782a6ebde25SWei Ni }; 7830fa2bfcdSWei Ni }; 7840fa2bfcdSWei Ni mem { 7850fa2bfcdSWei Ni polling-delay-passive = <0>; 7860fa2bfcdSWei Ni polling-delay = <0>; 7870fa2bfcdSWei Ni 7880fa2bfcdSWei Ni thermal-sensors = 7890fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 790a6ebde25SWei Ni 791a6ebde25SWei Ni trips { 792a6ebde25SWei Ni mem_shutdown_trip { 793a6ebde25SWei Ni temperature = <101000>; 794a6ebde25SWei Ni hysteresis = <1000>; 795a6ebde25SWei Ni type = "critical"; 796a6ebde25SWei Ni }; 797a6ebde25SWei Ni }; 798a6ebde25SWei Ni 799a6ebde25SWei Ni cooling-maps { 800a6ebde25SWei Ni /* 801a6ebde25SWei Ni * There are currently no cooling maps, 802a6ebde25SWei Ni * because there are no cooling devices. 803a6ebde25SWei Ni */ 804a6ebde25SWei Ni }; 8050fa2bfcdSWei Ni }; 8060fa2bfcdSWei Ni gpu { 8070fa2bfcdSWei Ni polling-delay-passive = <1000>; 8080fa2bfcdSWei Ni polling-delay = <0>; 8090fa2bfcdSWei Ni 8100fa2bfcdSWei Ni thermal-sensors = 8110fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 812a6ebde25SWei Ni 813a6ebde25SWei Ni trips { 814a6ebde25SWei Ni gpu_shutdown_trip { 815a6ebde25SWei Ni temperature = <101000>; 816a6ebde25SWei Ni hysteresis = <1000>; 817a6ebde25SWei Ni type = "critical"; 818a6ebde25SWei Ni }; 819f4357938SWei Ni 820f4357938SWei Ni gpu_throttle_trip: throttle-trip { 821f4357938SWei Ni temperature = <99000>; 822f4357938SWei Ni hysteresis = <1000>; 823f4357938SWei Ni type = "hot"; 824f4357938SWei Ni }; 825a6ebde25SWei Ni }; 826a6ebde25SWei Ni 827a6ebde25SWei Ni cooling-maps { 828f4357938SWei Ni map0 { 829f4357938SWei Ni trip = <&gpu_throttle_trip>; 830f4357938SWei Ni cooling-device = <&throttle_heavy 1 1>; 831f4357938SWei Ni }; 832a6ebde25SWei Ni }; 8330fa2bfcdSWei Ni }; 8340fa2bfcdSWei Ni pllx { 8350fa2bfcdSWei Ni polling-delay-passive = <0>; 8360fa2bfcdSWei Ni polling-delay = <0>; 8370fa2bfcdSWei Ni 8380fa2bfcdSWei Ni thermal-sensors = 8390fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 840a6ebde25SWei Ni 841a6ebde25SWei Ni trips { 842a6ebde25SWei Ni pllx_shutdown_trip { 843a6ebde25SWei Ni temperature = <105000>; 844a6ebde25SWei Ni hysteresis = <1000>; 845a6ebde25SWei Ni type = "critical"; 846a6ebde25SWei Ni }; 847a6ebde25SWei Ni }; 848a6ebde25SWei Ni 849a6ebde25SWei Ni cooling-maps { 850a6ebde25SWei Ni /* 851a6ebde25SWei Ni * There are currently no cooling maps, 852a6ebde25SWei Ni * because there are no cooling devices. 853a6ebde25SWei Ni */ 854a6ebde25SWei Ni }; 8550fa2bfcdSWei Ni }; 8560fa2bfcdSWei Ni }; 8570fa2bfcdSWei Ni 858be70771dSThierry Reding ahub@70300000 { 85934b4f6d0SThierry Reding compatible = "nvidia,tegra124-ahub"; 86034b4f6d0SThierry Reding reg = <0x0 0x70300000 0x0 0x200>, 86134b4f6d0SThierry Reding <0x0 0x70300800 0x0 0x800>, 86234b4f6d0SThierry Reding <0x0 0x70300200 0x0 0x600>; 86334b4f6d0SThierry Reding interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 86434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 86534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_APBIF>; 86634b4f6d0SThierry Reding clock-names = "d_audio", "apbif"; 86734b4f6d0SThierry Reding resets = <&tegra_car 106>, /* d_audio */ 86834b4f6d0SThierry Reding <&tegra_car 107>, /* apbif */ 86934b4f6d0SThierry Reding <&tegra_car 30>, /* i2s0 */ 87034b4f6d0SThierry Reding <&tegra_car 11>, /* i2s1 */ 87134b4f6d0SThierry Reding <&tegra_car 18>, /* i2s2 */ 87234b4f6d0SThierry Reding <&tegra_car 101>, /* i2s3 */ 87334b4f6d0SThierry Reding <&tegra_car 102>, /* i2s4 */ 87434b4f6d0SThierry Reding <&tegra_car 108>, /* dam0 */ 87534b4f6d0SThierry Reding <&tegra_car 109>, /* dam1 */ 87634b4f6d0SThierry Reding <&tegra_car 110>, /* dam2 */ 87734b4f6d0SThierry Reding <&tegra_car 10>, /* spdif */ 87834b4f6d0SThierry Reding <&tegra_car 153>, /* amx */ 87934b4f6d0SThierry Reding <&tegra_car 185>, /* amx1 */ 88034b4f6d0SThierry Reding <&tegra_car 154>, /* adx */ 88134b4f6d0SThierry Reding <&tegra_car 180>, /* adx1 */ 88234b4f6d0SThierry Reding <&tegra_car 186>, /* afc0 */ 88334b4f6d0SThierry Reding <&tegra_car 187>, /* afc1 */ 88434b4f6d0SThierry Reding <&tegra_car 188>, /* afc2 */ 88534b4f6d0SThierry Reding <&tegra_car 189>, /* afc3 */ 88634b4f6d0SThierry Reding <&tegra_car 190>, /* afc4 */ 88734b4f6d0SThierry Reding <&tegra_car 191>; /* afc5 */ 88834b4f6d0SThierry Reding reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 88934b4f6d0SThierry Reding "i2s3", "i2s4", "dam0", "dam1", "dam2", 89034b4f6d0SThierry Reding "spdif", "amx", "amx1", "adx", "adx1", 89134b4f6d0SThierry Reding "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 89234b4f6d0SThierry Reding dmas = <&apbdma 1>, <&apbdma 1>, 89334b4f6d0SThierry Reding <&apbdma 2>, <&apbdma 2>, 89434b4f6d0SThierry Reding <&apbdma 3>, <&apbdma 3>, 89534b4f6d0SThierry Reding <&apbdma 4>, <&apbdma 4>, 89634b4f6d0SThierry Reding <&apbdma 6>, <&apbdma 6>, 89734b4f6d0SThierry Reding <&apbdma 7>, <&apbdma 7>, 89834b4f6d0SThierry Reding <&apbdma 12>, <&apbdma 12>, 89934b4f6d0SThierry Reding <&apbdma 13>, <&apbdma 13>, 90034b4f6d0SThierry Reding <&apbdma 14>, <&apbdma 14>, 90134b4f6d0SThierry Reding <&apbdma 29>, <&apbdma 29>; 90234b4f6d0SThierry Reding dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 90334b4f6d0SThierry Reding "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 90434b4f6d0SThierry Reding "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 90534b4f6d0SThierry Reding "rx9", "tx9"; 90634b4f6d0SThierry Reding ranges; 90734b4f6d0SThierry Reding #address-cells = <2>; 90834b4f6d0SThierry Reding #size-cells = <2>; 90934b4f6d0SThierry Reding 910be70771dSThierry Reding tegra_i2s0: i2s@70301000 { 91134b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 91234b4f6d0SThierry Reding reg = <0x0 0x70301000 0x0 0x100>; 91334b4f6d0SThierry Reding nvidia,ahub-cif-ids = <4 4>; 91434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S0>; 91534b4f6d0SThierry Reding clock-names = "i2s"; 91634b4f6d0SThierry Reding resets = <&tegra_car 30>; 91734b4f6d0SThierry Reding reset-names = "i2s"; 91834b4f6d0SThierry Reding status = "disabled"; 91934b4f6d0SThierry Reding }; 92034b4f6d0SThierry Reding 921be70771dSThierry Reding tegra_i2s1: i2s@70301100 { 92234b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 92334b4f6d0SThierry Reding reg = <0x0 0x70301100 0x0 0x100>; 92434b4f6d0SThierry Reding nvidia,ahub-cif-ids = <5 5>; 92534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S1>; 92634b4f6d0SThierry Reding clock-names = "i2s"; 92734b4f6d0SThierry Reding resets = <&tegra_car 11>; 92834b4f6d0SThierry Reding reset-names = "i2s"; 92934b4f6d0SThierry Reding status = "disabled"; 93034b4f6d0SThierry Reding }; 93134b4f6d0SThierry Reding 932be70771dSThierry Reding tegra_i2s2: i2s@70301200 { 93334b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 93434b4f6d0SThierry Reding reg = <0x0 0x70301200 0x0 0x100>; 93534b4f6d0SThierry Reding nvidia,ahub-cif-ids = <6 6>; 93634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S2>; 93734b4f6d0SThierry Reding clock-names = "i2s"; 93834b4f6d0SThierry Reding resets = <&tegra_car 18>; 93934b4f6d0SThierry Reding reset-names = "i2s"; 94034b4f6d0SThierry Reding status = "disabled"; 94134b4f6d0SThierry Reding }; 94234b4f6d0SThierry Reding 943be70771dSThierry Reding tegra_i2s3: i2s@70301300 { 94434b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 94534b4f6d0SThierry Reding reg = <0x0 0x70301300 0x0 0x100>; 94634b4f6d0SThierry Reding nvidia,ahub-cif-ids = <7 7>; 94734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S3>; 94834b4f6d0SThierry Reding clock-names = "i2s"; 94934b4f6d0SThierry Reding resets = <&tegra_car 101>; 95034b4f6d0SThierry Reding reset-names = "i2s"; 95134b4f6d0SThierry Reding status = "disabled"; 95234b4f6d0SThierry Reding }; 95334b4f6d0SThierry Reding 954be70771dSThierry Reding tegra_i2s4: i2s@70301400 { 95534b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 95634b4f6d0SThierry Reding reg = <0x0 0x70301400 0x0 0x100>; 95734b4f6d0SThierry Reding nvidia,ahub-cif-ids = <8 8>; 95834b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S4>; 95934b4f6d0SThierry Reding clock-names = "i2s"; 96034b4f6d0SThierry Reding resets = <&tegra_car 102>; 96134b4f6d0SThierry Reding reset-names = "i2s"; 96234b4f6d0SThierry Reding status = "disabled"; 96334b4f6d0SThierry Reding }; 96434b4f6d0SThierry Reding }; 96534b4f6d0SThierry Reding 966be70771dSThierry Reding usb@7d000000 { 96734b4f6d0SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 96834b4f6d0SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 96934b4f6d0SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 97034b4f6d0SThierry Reding phy_type = "utmi"; 97134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USBD>; 97234b4f6d0SThierry Reding clock-names = "usb"; 97334b4f6d0SThierry Reding resets = <&tegra_car 22>; 97434b4f6d0SThierry Reding reset-names = "usb"; 97534b4f6d0SThierry Reding nvidia,phy = <&phy1>; 97634b4f6d0SThierry Reding status = "disabled"; 97734b4f6d0SThierry Reding }; 97834b4f6d0SThierry Reding 979be70771dSThierry Reding phy1: usb-phy@7d000000 { 98034b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 98134b4f6d0SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 98234b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 98334b4f6d0SThierry Reding phy_type = "utmi"; 98434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USBD>, 98534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 98634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 98734b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 98834b4f6d0SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 98934b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 99034b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 99134b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 99234b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 99334b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 99434b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 99534b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 99634b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 99734b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 99834b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 99934b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 100034b4f6d0SThierry Reding nvidia,has-utmi-pad-registers; 100134b4f6d0SThierry Reding status = "disabled"; 100234b4f6d0SThierry Reding }; 100334b4f6d0SThierry Reding 1004be70771dSThierry Reding usb@7d004000 { 100534b4f6d0SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 100634b4f6d0SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 100734b4f6d0SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 100834b4f6d0SThierry Reding phy_type = "utmi"; 100934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB2>; 101034b4f6d0SThierry Reding clock-names = "usb"; 101134b4f6d0SThierry Reding resets = <&tegra_car 58>; 101234b4f6d0SThierry Reding reset-names = "usb"; 101334b4f6d0SThierry Reding nvidia,phy = <&phy2>; 101434b4f6d0SThierry Reding status = "disabled"; 101534b4f6d0SThierry Reding }; 101634b4f6d0SThierry Reding 1017be70771dSThierry Reding phy2: usb-phy@7d004000 { 101834b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 101934b4f6d0SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 102034b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 102134b4f6d0SThierry Reding phy_type = "utmi"; 102234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB2>, 102334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 102434b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 102534b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 102634b4f6d0SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 102734b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 102834b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 102934b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 103034b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 103134b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 103234b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 103334b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 103434b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 103534b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 103634b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 103734b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 103834b4f6d0SThierry Reding status = "disabled"; 103934b4f6d0SThierry Reding }; 104034b4f6d0SThierry Reding 1041be70771dSThierry Reding usb@7d008000 { 104234b4f6d0SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 104334b4f6d0SThierry Reding reg = <0x0 0x7d008000 0x0 0x4000>; 104434b4f6d0SThierry Reding interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 104534b4f6d0SThierry Reding phy_type = "utmi"; 104634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB3>; 104734b4f6d0SThierry Reding clock-names = "usb"; 104834b4f6d0SThierry Reding resets = <&tegra_car 59>; 104934b4f6d0SThierry Reding reset-names = "usb"; 105034b4f6d0SThierry Reding nvidia,phy = <&phy3>; 105134b4f6d0SThierry Reding status = "disabled"; 105234b4f6d0SThierry Reding }; 105334b4f6d0SThierry Reding 1054be70771dSThierry Reding phy3: usb-phy@7d008000 { 105534b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 105634b4f6d0SThierry Reding reg = <0x0 0x7d008000 0x0 0x4000>, 105734b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 105834b4f6d0SThierry Reding phy_type = "utmi"; 105934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB3>, 106034b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 106134b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 106234b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 106334b4f6d0SThierry Reding resets = <&tegra_car 59>, <&tegra_car 22>; 106434b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 106534b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 106634b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 106734b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 106834b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 106934b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 107034b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 107134b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 107234b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 107334b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 107434b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 107534b4f6d0SThierry Reding status = "disabled"; 107634b4f6d0SThierry Reding }; 107734b4f6d0SThierry Reding 107834b4f6d0SThierry Reding cpus { 107934b4f6d0SThierry Reding #address-cells = <1>; 108034b4f6d0SThierry Reding #size-cells = <0>; 108134b4f6d0SThierry Reding 108234b4f6d0SThierry Reding cpu@0 { 108334b4f6d0SThierry Reding device_type = "cpu"; 108434b4f6d0SThierry Reding compatible = "nvidia,denver", "arm,armv8"; 108534b4f6d0SThierry Reding reg = <0>; 108634b4f6d0SThierry Reding }; 108734b4f6d0SThierry Reding 108834b4f6d0SThierry Reding cpu@1 { 108934b4f6d0SThierry Reding device_type = "cpu"; 109034b4f6d0SThierry Reding compatible = "nvidia,denver", "arm,armv8"; 109134b4f6d0SThierry Reding reg = <1>; 109234b4f6d0SThierry Reding }; 109334b4f6d0SThierry Reding }; 109434b4f6d0SThierry Reding 109534b4f6d0SThierry Reding timer { 109634b4f6d0SThierry Reding compatible = "arm,armv7-timer"; 109734b4f6d0SThierry Reding interrupts = <GIC_PPI 13 109834b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 109934b4f6d0SThierry Reding <GIC_PPI 14 110034b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 110134b4f6d0SThierry Reding <GIC_PPI 11 110234b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 110334b4f6d0SThierry Reding <GIC_PPI 10 110434b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 110534b4f6d0SThierry Reding interrupt-parent = <&gic>; 110634b4f6d0SThierry Reding }; 110734b4f6d0SThierry Reding}; 1108