134b4f6d0SThierry Reding#include <dt-bindings/clock/tegra124-car.h> 234b4f6d0SThierry Reding#include <dt-bindings/gpio/tegra-gpio.h> 334b4f6d0SThierry Reding#include <dt-bindings/memory/tegra124-mc.h> 434b4f6d0SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra.h> 534b4f6d0SThierry Reding#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 634b4f6d0SThierry Reding#include <dt-bindings/interrupt-controller/arm-gic.h> 70fa2bfcdSWei Ni#include <dt-bindings/thermal/tegra124-soctherm.h> 834b4f6d0SThierry Reding 934b4f6d0SThierry Reding/ { 1034b4f6d0SThierry Reding compatible = "nvidia,tegra132", "nvidia,tegra124"; 1134b4f6d0SThierry Reding interrupt-parent = <&lic>; 1234b4f6d0SThierry Reding #address-cells = <2>; 1334b4f6d0SThierry Reding #size-cells = <2>; 1434b4f6d0SThierry Reding 15be70771dSThierry Reding pcie-controller@01003000 { 1634b4f6d0SThierry Reding compatible = "nvidia,tegra124-pcie"; 1734b4f6d0SThierry Reding device_type = "pci"; 1834b4f6d0SThierry Reding reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 1934b4f6d0SThierry Reding 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 2034b4f6d0SThierry Reding 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 2134b4f6d0SThierry Reding reg-names = "pads", "afi", "cs"; 2234b4f6d0SThierry Reding interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2334b4f6d0SThierry Reding <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2434b4f6d0SThierry Reding interrupt-names = "intr", "msi"; 2534b4f6d0SThierry Reding 2634b4f6d0SThierry Reding #interrupt-cells = <1>; 2734b4f6d0SThierry Reding interrupt-map-mask = <0 0 0 0>; 2834b4f6d0SThierry Reding interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2934b4f6d0SThierry Reding 3034b4f6d0SThierry Reding bus-range = <0x00 0xff>; 3134b4f6d0SThierry Reding #address-cells = <3>; 3234b4f6d0SThierry Reding #size-cells = <2>; 3334b4f6d0SThierry Reding 3434b4f6d0SThierry Reding ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 3534b4f6d0SThierry Reding 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 3634b4f6d0SThierry Reding 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 3734b4f6d0SThierry Reding 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 3834b4f6d0SThierry Reding 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 3934b4f6d0SThierry Reding 4034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PCIE>, 4134b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_AFI>, 4234b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_E>, 4334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CML0>; 4434b4f6d0SThierry Reding clock-names = "pex", "afi", "pll_e", "cml"; 4534b4f6d0SThierry Reding resets = <&tegra_car 70>, 4634b4f6d0SThierry Reding <&tegra_car 72>, 4734b4f6d0SThierry Reding <&tegra_car 74>; 4834b4f6d0SThierry Reding reset-names = "pex", "afi", "pcie_x"; 4934b4f6d0SThierry Reding status = "disabled"; 5034b4f6d0SThierry Reding 5134b4f6d0SThierry Reding phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 5234b4f6d0SThierry Reding phy-names = "pcie"; 5334b4f6d0SThierry Reding 5434b4f6d0SThierry Reding pci@1,0 { 5534b4f6d0SThierry Reding device_type = "pci"; 5634b4f6d0SThierry Reding assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 5734b4f6d0SThierry Reding reg = <0x000800 0 0 0 0>; 5834b4f6d0SThierry Reding status = "disabled"; 5934b4f6d0SThierry Reding 6034b4f6d0SThierry Reding #address-cells = <3>; 6134b4f6d0SThierry Reding #size-cells = <2>; 6234b4f6d0SThierry Reding ranges; 6334b4f6d0SThierry Reding 6434b4f6d0SThierry Reding nvidia,num-lanes = <2>; 6534b4f6d0SThierry Reding }; 6634b4f6d0SThierry Reding 6734b4f6d0SThierry Reding pci@2,0 { 6834b4f6d0SThierry Reding device_type = "pci"; 6934b4f6d0SThierry Reding assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 7034b4f6d0SThierry Reding reg = <0x001000 0 0 0 0>; 7134b4f6d0SThierry Reding status = "disabled"; 7234b4f6d0SThierry Reding 7334b4f6d0SThierry Reding #address-cells = <3>; 7434b4f6d0SThierry Reding #size-cells = <2>; 7534b4f6d0SThierry Reding ranges; 7634b4f6d0SThierry Reding 7734b4f6d0SThierry Reding nvidia,num-lanes = <1>; 7834b4f6d0SThierry Reding }; 7934b4f6d0SThierry Reding }; 8034b4f6d0SThierry Reding 81be70771dSThierry Reding host1x@50000000 { 8234b4f6d0SThierry Reding compatible = "nvidia,tegra124-host1x", "simple-bus"; 8334b4f6d0SThierry Reding reg = <0x0 0x50000000 0x0 0x00034000>; 8434b4f6d0SThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 8534b4f6d0SThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 8634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 8734b4f6d0SThierry Reding clock-names = "host1x"; 8834b4f6d0SThierry Reding resets = <&tegra_car 28>; 8934b4f6d0SThierry Reding reset-names = "host1x"; 9034b4f6d0SThierry Reding 9134b4f6d0SThierry Reding #address-cells = <2>; 9234b4f6d0SThierry Reding #size-cells = <2>; 9334b4f6d0SThierry Reding 9434b4f6d0SThierry Reding ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 9534b4f6d0SThierry Reding 96be70771dSThierry Reding dc@54200000 { 9734b4f6d0SThierry Reding compatible = "nvidia,tegra124-dc"; 9834b4f6d0SThierry Reding reg = <0x0 0x54200000 0x0 0x00040000>; 9934b4f6d0SThierry Reding interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 10034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DISP1>, 10134b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_P>; 10234b4f6d0SThierry Reding clock-names = "dc", "parent"; 10334b4f6d0SThierry Reding resets = <&tegra_car 27>; 10434b4f6d0SThierry Reding reset-names = "dc"; 10534b4f6d0SThierry Reding 10634b4f6d0SThierry Reding iommus = <&mc TEGRA_SWGROUP_DC>; 10734b4f6d0SThierry Reding 10834b4f6d0SThierry Reding nvidia,head = <0>; 10934b4f6d0SThierry Reding }; 11034b4f6d0SThierry Reding 111be70771dSThierry Reding dc@54240000 { 11234b4f6d0SThierry Reding compatible = "nvidia,tegra124-dc"; 11334b4f6d0SThierry Reding reg = <0x0 0x54240000 0x0 0x00040000>; 11434b4f6d0SThierry Reding interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 11534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DISP2>, 11634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_P>; 11734b4f6d0SThierry Reding clock-names = "dc", "parent"; 11834b4f6d0SThierry Reding resets = <&tegra_car 26>; 11934b4f6d0SThierry Reding reset-names = "dc"; 12034b4f6d0SThierry Reding 12134b4f6d0SThierry Reding iommus = <&mc TEGRA_SWGROUP_DCB>; 12234b4f6d0SThierry Reding 12334b4f6d0SThierry Reding nvidia,head = <1>; 12434b4f6d0SThierry Reding }; 12534b4f6d0SThierry Reding 126be70771dSThierry Reding hdmi@54280000 { 12734b4f6d0SThierry Reding compatible = "nvidia,tegra124-hdmi"; 12834b4f6d0SThierry Reding reg = <0x0 0x54280000 0x0 0x00040000>; 12934b4f6d0SThierry Reding interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 13034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HDMI>, 13134b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 13234b4f6d0SThierry Reding clock-names = "hdmi", "parent"; 13334b4f6d0SThierry Reding resets = <&tegra_car 51>; 13434b4f6d0SThierry Reding reset-names = "hdmi"; 13534b4f6d0SThierry Reding status = "disabled"; 13634b4f6d0SThierry Reding }; 13734b4f6d0SThierry Reding 138be70771dSThierry Reding sor@54540000 { 13934b4f6d0SThierry Reding compatible = "nvidia,tegra124-sor"; 14034b4f6d0SThierry Reding reg = <0x0 0x54540000 0x0 0x00040000>; 14134b4f6d0SThierry Reding interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 14234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SOR0>, 14334b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 14434b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_DP>, 14534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CLK_M>; 14634b4f6d0SThierry Reding clock-names = "sor", "parent", "dp", "safe"; 14734b4f6d0SThierry Reding resets = <&tegra_car 182>; 14834b4f6d0SThierry Reding reset-names = "sor"; 14934b4f6d0SThierry Reding status = "disabled"; 15034b4f6d0SThierry Reding }; 15134b4f6d0SThierry Reding 152be70771dSThierry Reding dpaux: dpaux@545c0000 { 15334b4f6d0SThierry Reding compatible = "nvidia,tegra124-dpaux"; 15434b4f6d0SThierry Reding reg = <0x0 0x545c0000 0x0 0x00040000>; 15534b4f6d0SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 15634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 15734b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_DP>; 15834b4f6d0SThierry Reding clock-names = "dpaux", "parent"; 15934b4f6d0SThierry Reding resets = <&tegra_car 181>; 16034b4f6d0SThierry Reding reset-names = "dpaux"; 16134b4f6d0SThierry Reding status = "disabled"; 16234b4f6d0SThierry Reding }; 16334b4f6d0SThierry Reding }; 16434b4f6d0SThierry Reding 165be70771dSThierry Reding gic: interrupt-controller@50041000 { 16634b4f6d0SThierry Reding compatible = "arm,cortex-a15-gic"; 16734b4f6d0SThierry Reding #interrupt-cells = <3>; 16834b4f6d0SThierry Reding interrupt-controller; 16934b4f6d0SThierry Reding reg = <0x0 0x50041000 0x0 0x1000>, 17034b4f6d0SThierry Reding <0x0 0x50042000 0x0 0x2000>, 17134b4f6d0SThierry Reding <0x0 0x50044000 0x0 0x2000>, 17234b4f6d0SThierry Reding <0x0 0x50046000 0x0 0x2000>; 17334b4f6d0SThierry Reding interrupts = <GIC_PPI 9 17434b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 17534b4f6d0SThierry Reding interrupt-parent = <&gic>; 17634b4f6d0SThierry Reding }; 17734b4f6d0SThierry Reding 178be70771dSThierry Reding gpu@57000000 { 17934b4f6d0SThierry Reding compatible = "nvidia,gk20a"; 18034b4f6d0SThierry Reding reg = <0x0 0x57000000 0x0 0x01000000>, 18134b4f6d0SThierry Reding <0x0 0x58000000 0x0 0x01000000>; 18234b4f6d0SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 18334b4f6d0SThierry Reding <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 18434b4f6d0SThierry Reding interrupt-names = "stall", "nonstall"; 18534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_GPU>, 18634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 18734b4f6d0SThierry Reding clock-names = "gpu", "pwr"; 18834b4f6d0SThierry Reding resets = <&tegra_car 184>; 18934b4f6d0SThierry Reding reset-names = "gpu"; 19034b4f6d0SThierry Reding status = "disabled"; 19134b4f6d0SThierry Reding }; 19234b4f6d0SThierry Reding 19334b4f6d0SThierry Reding lic: interrupt-controller@60004000 { 19434b4f6d0SThierry Reding compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 19534b4f6d0SThierry Reding reg = <0x0 0x60004000 0x0 0x100>, 19634b4f6d0SThierry Reding <0x0 0x60004100 0x0 0x100>, 19734b4f6d0SThierry Reding <0x0 0x60004200 0x0 0x100>, 19834b4f6d0SThierry Reding <0x0 0x60004300 0x0 0x100>, 19934b4f6d0SThierry Reding <0x0 0x60004400 0x0 0x100>; 20034b4f6d0SThierry Reding interrupt-controller; 20134b4f6d0SThierry Reding #interrupt-cells = <3>; 20234b4f6d0SThierry Reding interrupt-parent = <&gic>; 20334b4f6d0SThierry Reding }; 20434b4f6d0SThierry Reding 205be70771dSThierry Reding timer@60005000 { 20634b4f6d0SThierry Reding compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 20734b4f6d0SThierry Reding reg = <0x0 0x60005000 0x0 0x400>; 20834b4f6d0SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 20934b4f6d0SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 21034b4f6d0SThierry Reding <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 21134b4f6d0SThierry Reding <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 21234b4f6d0SThierry Reding <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 21334b4f6d0SThierry Reding <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 21434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_TIMER>; 21534b4f6d0SThierry Reding clock-names = "timer"; 21634b4f6d0SThierry Reding }; 21734b4f6d0SThierry Reding 218be70771dSThierry Reding tegra_car: clock@60006000 { 21934b4f6d0SThierry Reding compatible = "nvidia,tegra132-car"; 22034b4f6d0SThierry Reding reg = <0x0 0x60006000 0x0 0x1000>; 22134b4f6d0SThierry Reding #clock-cells = <1>; 22234b4f6d0SThierry Reding #reset-cells = <1>; 22334b4f6d0SThierry Reding nvidia,external-memory-controller = <&emc>; 22434b4f6d0SThierry Reding }; 22534b4f6d0SThierry Reding 226be70771dSThierry Reding flow-controller@60007000 { 22734b4f6d0SThierry Reding compatible = "nvidia,tegra124-flowctrl"; 22834b4f6d0SThierry Reding reg = <0x0 0x60007000 0x0 0x1000>; 22934b4f6d0SThierry Reding }; 23034b4f6d0SThierry Reding 231be70771dSThierry Reding actmon@6000c800 { 23234b4f6d0SThierry Reding compatible = "nvidia,tegra124-actmon"; 23334b4f6d0SThierry Reding reg = <0x0 0x6000c800 0x0 0x400>; 23434b4f6d0SThierry Reding interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 23534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 23634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_EMC>; 23734b4f6d0SThierry Reding clock-names = "actmon", "emc"; 23834b4f6d0SThierry Reding resets = <&tegra_car 119>; 23934b4f6d0SThierry Reding reset-names = "actmon"; 24034b4f6d0SThierry Reding }; 24134b4f6d0SThierry Reding 242be70771dSThierry Reding gpio: gpio@6000d000 { 24334b4f6d0SThierry Reding compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 24434b4f6d0SThierry Reding reg = <0x0 0x6000d000 0x0 0x1000>; 24534b4f6d0SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 24634b4f6d0SThierry Reding <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 24734b4f6d0SThierry Reding <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 24834b4f6d0SThierry Reding <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 24934b4f6d0SThierry Reding <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 25034b4f6d0SThierry Reding <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 25134b4f6d0SThierry Reding <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 25234b4f6d0SThierry Reding <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 25334b4f6d0SThierry Reding #gpio-cells = <2>; 25434b4f6d0SThierry Reding gpio-controller; 25534b4f6d0SThierry Reding #interrupt-cells = <2>; 25634b4f6d0SThierry Reding interrupt-controller; 25734b4f6d0SThierry Reding }; 25834b4f6d0SThierry Reding 259be70771dSThierry Reding apbdma: dma@60020000 { 26034b4f6d0SThierry Reding compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 26134b4f6d0SThierry Reding reg = <0x0 0x60020000 0x0 0x1400>; 26234b4f6d0SThierry Reding interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 26334b4f6d0SThierry Reding <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 26434b4f6d0SThierry Reding <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 26534b4f6d0SThierry Reding <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 26634b4f6d0SThierry Reding <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 26734b4f6d0SThierry Reding <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 26834b4f6d0SThierry Reding <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 26934b4f6d0SThierry Reding <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 27034b4f6d0SThierry Reding <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 27134b4f6d0SThierry Reding <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 27234b4f6d0SThierry Reding <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 27334b4f6d0SThierry Reding <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 27434b4f6d0SThierry Reding <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 27534b4f6d0SThierry Reding <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 27634b4f6d0SThierry Reding <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 27734b4f6d0SThierry Reding <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 27834b4f6d0SThierry Reding <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 27934b4f6d0SThierry Reding <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 28034b4f6d0SThierry Reding <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 28134b4f6d0SThierry Reding <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 28234b4f6d0SThierry Reding <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 28334b4f6d0SThierry Reding <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 28434b4f6d0SThierry Reding <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 28534b4f6d0SThierry Reding <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 28634b4f6d0SThierry Reding <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 28734b4f6d0SThierry Reding <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 28834b4f6d0SThierry Reding <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 28934b4f6d0SThierry Reding <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 29034b4f6d0SThierry Reding <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 29134b4f6d0SThierry Reding <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 29234b4f6d0SThierry Reding <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 29334b4f6d0SThierry Reding <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 29434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 29534b4f6d0SThierry Reding clock-names = "dma"; 29634b4f6d0SThierry Reding resets = <&tegra_car 34>; 29734b4f6d0SThierry Reding reset-names = "dma"; 29834b4f6d0SThierry Reding #dma-cells = <1>; 29934b4f6d0SThierry Reding }; 30034b4f6d0SThierry Reding 301be70771dSThierry Reding apbmisc@70000800 { 30234b4f6d0SThierry Reding compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 30334b4f6d0SThierry Reding reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 30434b4f6d0SThierry Reding <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 30534b4f6d0SThierry Reding }; 30634b4f6d0SThierry Reding 307be70771dSThierry Reding pinmux: pinmux@70000868 { 30834b4f6d0SThierry Reding compatible = "nvidia,tegra124-pinmux"; 30934b4f6d0SThierry Reding reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 31034b4f6d0SThierry Reding <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 31134b4f6d0SThierry Reding <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 31234b4f6d0SThierry Reding }; 31334b4f6d0SThierry Reding 31434b4f6d0SThierry Reding /* 31534b4f6d0SThierry Reding * There are two serial driver i.e. 8250 based simple serial 31634b4f6d0SThierry Reding * driver and APB DMA based serial driver for higher baudrate 317ef769e32SAdam Buchbinder * and performance. To enable the 8250 based driver, the compatible 31834b4f6d0SThierry Reding * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 31968cd8b2eSThierry Reding * the APB DMA based serial driver, the compatible is 32034b4f6d0SThierry Reding * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 32134b4f6d0SThierry Reding */ 322be70771dSThierry Reding uarta: serial@70006000 { 32334b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 32434b4f6d0SThierry Reding reg = <0x0 0x70006000 0x0 0x40>; 32534b4f6d0SThierry Reding reg-shift = <2>; 32634b4f6d0SThierry Reding interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 32734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTA>; 32834b4f6d0SThierry Reding clock-names = "serial"; 32934b4f6d0SThierry Reding resets = <&tegra_car 6>; 33034b4f6d0SThierry Reding reset-names = "serial"; 33134b4f6d0SThierry Reding dmas = <&apbdma 8>, <&apbdma 8>; 33234b4f6d0SThierry Reding dma-names = "rx", "tx"; 33334b4f6d0SThierry Reding status = "disabled"; 33434b4f6d0SThierry Reding }; 33534b4f6d0SThierry Reding 336be70771dSThierry Reding uartb: serial@70006040 { 33734b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 33834b4f6d0SThierry Reding reg = <0x0 0x70006040 0x0 0x40>; 33934b4f6d0SThierry Reding reg-shift = <2>; 34034b4f6d0SThierry Reding interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 34134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTB>; 34234b4f6d0SThierry Reding clock-names = "serial"; 34334b4f6d0SThierry Reding resets = <&tegra_car 7>; 34434b4f6d0SThierry Reding reset-names = "serial"; 34534b4f6d0SThierry Reding dmas = <&apbdma 9>, <&apbdma 9>; 34634b4f6d0SThierry Reding dma-names = "rx", "tx"; 34734b4f6d0SThierry Reding status = "disabled"; 34834b4f6d0SThierry Reding }; 34934b4f6d0SThierry Reding 350be70771dSThierry Reding uartc: serial@70006200 { 35134b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 35234b4f6d0SThierry Reding reg = <0x0 0x70006200 0x0 0x40>; 35334b4f6d0SThierry Reding reg-shift = <2>; 35434b4f6d0SThierry Reding interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 35534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTC>; 35634b4f6d0SThierry Reding clock-names = "serial"; 35734b4f6d0SThierry Reding resets = <&tegra_car 55>; 35834b4f6d0SThierry Reding reset-names = "serial"; 35934b4f6d0SThierry Reding dmas = <&apbdma 10>, <&apbdma 10>; 36034b4f6d0SThierry Reding dma-names = "rx", "tx"; 36134b4f6d0SThierry Reding status = "disabled"; 36234b4f6d0SThierry Reding }; 36334b4f6d0SThierry Reding 364be70771dSThierry Reding uartd: serial@70006300 { 36534b4f6d0SThierry Reding compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 36634b4f6d0SThierry Reding reg = <0x0 0x70006300 0x0 0x40>; 36734b4f6d0SThierry Reding reg-shift = <2>; 36834b4f6d0SThierry Reding interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 36934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_UARTD>; 37034b4f6d0SThierry Reding clock-names = "serial"; 37134b4f6d0SThierry Reding resets = <&tegra_car 65>; 37234b4f6d0SThierry Reding reset-names = "serial"; 37334b4f6d0SThierry Reding dmas = <&apbdma 19>, <&apbdma 19>; 37434b4f6d0SThierry Reding dma-names = "rx", "tx"; 37534b4f6d0SThierry Reding status = "disabled"; 37634b4f6d0SThierry Reding }; 37734b4f6d0SThierry Reding 378be70771dSThierry Reding pwm: pwm@7000a000 { 37934b4f6d0SThierry Reding compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 38034b4f6d0SThierry Reding reg = <0x0 0x7000a000 0x0 0x100>; 38134b4f6d0SThierry Reding #pwm-cells = <2>; 38234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PWM>; 38334b4f6d0SThierry Reding clock-names = "pwm"; 38434b4f6d0SThierry Reding resets = <&tegra_car 17>; 38534b4f6d0SThierry Reding reset-names = "pwm"; 38634b4f6d0SThierry Reding status = "disabled"; 38734b4f6d0SThierry Reding }; 38834b4f6d0SThierry Reding 389be70771dSThierry Reding i2c@7000c000 { 39034b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 39134b4f6d0SThierry Reding reg = <0x0 0x7000c000 0x0 0x100>; 39234b4f6d0SThierry Reding interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 39334b4f6d0SThierry Reding #address-cells = <1>; 39434b4f6d0SThierry Reding #size-cells = <0>; 39534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C1>; 39634b4f6d0SThierry Reding clock-names = "div-clk"; 39734b4f6d0SThierry Reding resets = <&tegra_car 12>; 39834b4f6d0SThierry Reding reset-names = "i2c"; 39934b4f6d0SThierry Reding dmas = <&apbdma 21>, <&apbdma 21>; 40034b4f6d0SThierry Reding dma-names = "rx", "tx"; 40134b4f6d0SThierry Reding status = "disabled"; 40234b4f6d0SThierry Reding }; 40334b4f6d0SThierry Reding 404be70771dSThierry Reding i2c@7000c400 { 40534b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 40634b4f6d0SThierry Reding reg = <0x0 0x7000c400 0x0 0x100>; 40734b4f6d0SThierry Reding interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 40834b4f6d0SThierry Reding #address-cells = <1>; 40934b4f6d0SThierry Reding #size-cells = <0>; 41034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C2>; 41134b4f6d0SThierry Reding clock-names = "div-clk"; 41234b4f6d0SThierry Reding resets = <&tegra_car 54>; 41334b4f6d0SThierry Reding reset-names = "i2c"; 41434b4f6d0SThierry Reding dmas = <&apbdma 22>, <&apbdma 22>; 41534b4f6d0SThierry Reding dma-names = "rx", "tx"; 41634b4f6d0SThierry Reding status = "disabled"; 41734b4f6d0SThierry Reding }; 41834b4f6d0SThierry Reding 419be70771dSThierry Reding i2c@7000c500 { 42034b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 42134b4f6d0SThierry Reding reg = <0x0 0x7000c500 0x0 0x100>; 42234b4f6d0SThierry Reding interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 42334b4f6d0SThierry Reding #address-cells = <1>; 42434b4f6d0SThierry Reding #size-cells = <0>; 42534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C3>; 42634b4f6d0SThierry Reding clock-names = "div-clk"; 42734b4f6d0SThierry Reding resets = <&tegra_car 67>; 42834b4f6d0SThierry Reding reset-names = "i2c"; 42934b4f6d0SThierry Reding dmas = <&apbdma 23>, <&apbdma 23>; 43034b4f6d0SThierry Reding dma-names = "rx", "tx"; 43134b4f6d0SThierry Reding status = "disabled"; 43234b4f6d0SThierry Reding }; 43334b4f6d0SThierry Reding 434be70771dSThierry Reding i2c@7000c700 { 43534b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 43634b4f6d0SThierry Reding reg = <0x0 0x7000c700 0x0 0x100>; 43734b4f6d0SThierry Reding interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 43834b4f6d0SThierry Reding #address-cells = <1>; 43934b4f6d0SThierry Reding #size-cells = <0>; 44034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C4>; 44134b4f6d0SThierry Reding clock-names = "div-clk"; 44234b4f6d0SThierry Reding resets = <&tegra_car 103>; 44334b4f6d0SThierry Reding reset-names = "i2c"; 44434b4f6d0SThierry Reding dmas = <&apbdma 26>, <&apbdma 26>; 44534b4f6d0SThierry Reding dma-names = "rx", "tx"; 44634b4f6d0SThierry Reding status = "disabled"; 44734b4f6d0SThierry Reding }; 44834b4f6d0SThierry Reding 449be70771dSThierry Reding i2c@7000d000 { 45034b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 45134b4f6d0SThierry Reding reg = <0x0 0x7000d000 0x0 0x100>; 45234b4f6d0SThierry Reding interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 45334b4f6d0SThierry Reding #address-cells = <1>; 45434b4f6d0SThierry Reding #size-cells = <0>; 45534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C5>; 45634b4f6d0SThierry Reding clock-names = "div-clk"; 45734b4f6d0SThierry Reding resets = <&tegra_car 47>; 45834b4f6d0SThierry Reding reset-names = "i2c"; 45934b4f6d0SThierry Reding dmas = <&apbdma 24>, <&apbdma 24>; 46034b4f6d0SThierry Reding dma-names = "rx", "tx"; 46134b4f6d0SThierry Reding status = "disabled"; 46234b4f6d0SThierry Reding }; 46334b4f6d0SThierry Reding 464be70771dSThierry Reding i2c@7000d100 { 46534b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 46634b4f6d0SThierry Reding reg = <0x0 0x7000d100 0x0 0x100>; 46734b4f6d0SThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 46834b4f6d0SThierry Reding #address-cells = <1>; 46934b4f6d0SThierry Reding #size-cells = <0>; 47034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2C6>; 47134b4f6d0SThierry Reding clock-names = "div-clk"; 47234b4f6d0SThierry Reding resets = <&tegra_car 166>; 47334b4f6d0SThierry Reding reset-names = "i2c"; 47434b4f6d0SThierry Reding dmas = <&apbdma 30>, <&apbdma 30>; 47534b4f6d0SThierry Reding dma-names = "rx", "tx"; 47634b4f6d0SThierry Reding status = "disabled"; 47734b4f6d0SThierry Reding }; 47834b4f6d0SThierry Reding 479be70771dSThierry Reding spi@7000d400 { 48034b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 48134b4f6d0SThierry Reding reg = <0x0 0x7000d400 0x0 0x200>; 48234b4f6d0SThierry Reding interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 48334b4f6d0SThierry Reding #address-cells = <1>; 48434b4f6d0SThierry Reding #size-cells = <0>; 48534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC1>; 48634b4f6d0SThierry Reding clock-names = "spi"; 48734b4f6d0SThierry Reding resets = <&tegra_car 41>; 48834b4f6d0SThierry Reding reset-names = "spi"; 48934b4f6d0SThierry Reding dmas = <&apbdma 15>, <&apbdma 15>; 49034b4f6d0SThierry Reding dma-names = "rx", "tx"; 49134b4f6d0SThierry Reding status = "disabled"; 49234b4f6d0SThierry Reding }; 49334b4f6d0SThierry Reding 494be70771dSThierry Reding spi@7000d600 { 49534b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 49634b4f6d0SThierry Reding reg = <0x0 0x7000d600 0x0 0x200>; 49734b4f6d0SThierry Reding interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 49834b4f6d0SThierry Reding #address-cells = <1>; 49934b4f6d0SThierry Reding #size-cells = <0>; 50034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC2>; 50134b4f6d0SThierry Reding clock-names = "spi"; 50234b4f6d0SThierry Reding resets = <&tegra_car 44>; 50334b4f6d0SThierry Reding reset-names = "spi"; 50434b4f6d0SThierry Reding dmas = <&apbdma 16>, <&apbdma 16>; 50534b4f6d0SThierry Reding dma-names = "rx", "tx"; 50634b4f6d0SThierry Reding status = "disabled"; 50734b4f6d0SThierry Reding }; 50834b4f6d0SThierry Reding 509be70771dSThierry Reding spi@7000d800 { 51034b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 51134b4f6d0SThierry Reding reg = <0x0 0x7000d800 0x0 0x200>; 51234b4f6d0SThierry Reding interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 51334b4f6d0SThierry Reding #address-cells = <1>; 51434b4f6d0SThierry Reding #size-cells = <0>; 51534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC3>; 51634b4f6d0SThierry Reding clock-names = "spi"; 51734b4f6d0SThierry Reding resets = <&tegra_car 46>; 51834b4f6d0SThierry Reding reset-names = "spi"; 51934b4f6d0SThierry Reding dmas = <&apbdma 17>, <&apbdma 17>; 52034b4f6d0SThierry Reding dma-names = "rx", "tx"; 52134b4f6d0SThierry Reding status = "disabled"; 52234b4f6d0SThierry Reding }; 52334b4f6d0SThierry Reding 524be70771dSThierry Reding spi@7000da00 { 52534b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 52634b4f6d0SThierry Reding reg = <0x0 0x7000da00 0x0 0x200>; 52734b4f6d0SThierry Reding interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 52834b4f6d0SThierry Reding #address-cells = <1>; 52934b4f6d0SThierry Reding #size-cells = <0>; 53034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC4>; 53134b4f6d0SThierry Reding clock-names = "spi"; 53234b4f6d0SThierry Reding resets = <&tegra_car 68>; 53334b4f6d0SThierry Reding reset-names = "spi"; 53434b4f6d0SThierry Reding dmas = <&apbdma 18>, <&apbdma 18>; 53534b4f6d0SThierry Reding dma-names = "rx", "tx"; 53634b4f6d0SThierry Reding status = "disabled"; 53734b4f6d0SThierry Reding }; 53834b4f6d0SThierry Reding 539be70771dSThierry Reding spi@7000dc00 { 54034b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 54134b4f6d0SThierry Reding reg = <0x0 0x7000dc00 0x0 0x200>; 54234b4f6d0SThierry Reding interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 54334b4f6d0SThierry Reding #address-cells = <1>; 54434b4f6d0SThierry Reding #size-cells = <0>; 54534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC5>; 54634b4f6d0SThierry Reding clock-names = "spi"; 54734b4f6d0SThierry Reding resets = <&tegra_car 104>; 54834b4f6d0SThierry Reding reset-names = "spi"; 54934b4f6d0SThierry Reding dmas = <&apbdma 27>, <&apbdma 27>; 55034b4f6d0SThierry Reding dma-names = "rx", "tx"; 55134b4f6d0SThierry Reding status = "disabled"; 55234b4f6d0SThierry Reding }; 55334b4f6d0SThierry Reding 554be70771dSThierry Reding spi@7000de00 { 55534b4f6d0SThierry Reding compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 55634b4f6d0SThierry Reding reg = <0x0 0x7000de00 0x0 0x200>; 55734b4f6d0SThierry Reding interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 55834b4f6d0SThierry Reding #address-cells = <1>; 55934b4f6d0SThierry Reding #size-cells = <0>; 56034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SBC6>; 56134b4f6d0SThierry Reding clock-names = "spi"; 56234b4f6d0SThierry Reding resets = <&tegra_car 105>; 56334b4f6d0SThierry Reding reset-names = "spi"; 56434b4f6d0SThierry Reding dmas = <&apbdma 28>, <&apbdma 28>; 56534b4f6d0SThierry Reding dma-names = "rx", "tx"; 56634b4f6d0SThierry Reding status = "disabled"; 56734b4f6d0SThierry Reding }; 56834b4f6d0SThierry Reding 569be70771dSThierry Reding rtc@7000e000 { 57034b4f6d0SThierry Reding compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 57134b4f6d0SThierry Reding reg = <0x0 0x7000e000 0x0 0x100>; 57234b4f6d0SThierry Reding interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 57334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_RTC>; 57434b4f6d0SThierry Reding clock-names = "rtc"; 57534b4f6d0SThierry Reding }; 57634b4f6d0SThierry Reding 577be70771dSThierry Reding pmc@7000e400 { 57834b4f6d0SThierry Reding compatible = "nvidia,tegra124-pmc"; 57934b4f6d0SThierry Reding reg = <0x0 0x7000e400 0x0 0x400>; 58034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 58134b4f6d0SThierry Reding clock-names = "pclk", "clk32k_in"; 58234b4f6d0SThierry Reding }; 58334b4f6d0SThierry Reding 584be70771dSThierry Reding fuse@7000f800 { 58534b4f6d0SThierry Reding compatible = "nvidia,tegra124-efuse"; 58634b4f6d0SThierry Reding reg = <0x0 0x7000f800 0x0 0x400>; 58734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_FUSE>; 58834b4f6d0SThierry Reding clock-names = "fuse"; 58934b4f6d0SThierry Reding resets = <&tegra_car 39>; 59034b4f6d0SThierry Reding reset-names = "fuse"; 59134b4f6d0SThierry Reding }; 59234b4f6d0SThierry Reding 593be70771dSThierry Reding mc: memory-controller@70019000 { 59434b4f6d0SThierry Reding compatible = "nvidia,tegra132-mc"; 59534b4f6d0SThierry Reding reg = <0x0 0x70019000 0x0 0x1000>; 59634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_MC>; 59734b4f6d0SThierry Reding clock-names = "mc"; 59834b4f6d0SThierry Reding 59934b4f6d0SThierry Reding interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 60034b4f6d0SThierry Reding 60134b4f6d0SThierry Reding #iommu-cells = <1>; 60234b4f6d0SThierry Reding }; 60334b4f6d0SThierry Reding 604be70771dSThierry Reding emc: emc@7001b000 { 60534b4f6d0SThierry Reding compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 60634b4f6d0SThierry Reding reg = <0x0 0x7001b000 0x0 0x1000>; 60734b4f6d0SThierry Reding 60834b4f6d0SThierry Reding nvidia,memory-controller = <&mc>; 60934b4f6d0SThierry Reding }; 61034b4f6d0SThierry Reding 611be70771dSThierry Reding sata@70020000 { 61234b4f6d0SThierry Reding compatible = "nvidia,tegra124-ahci"; 61334b4f6d0SThierry Reding reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 61434b4f6d0SThierry Reding <0x0 0x70020000 0x0 0x7000>; /* SATA */ 61534b4f6d0SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 61634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SATA>, 61734b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_SATA_OOB>, 61834b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_CML1>, 61934b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_E>; 62034b4f6d0SThierry Reding clock-names = "sata", "sata-oob", "cml1", "pll_e"; 62134b4f6d0SThierry Reding resets = <&tegra_car 124>, 62234b4f6d0SThierry Reding <&tegra_car 123>, 62334b4f6d0SThierry Reding <&tegra_car 129>; 62434b4f6d0SThierry Reding reset-names = "sata", "sata-oob", "sata-cold"; 62534b4f6d0SThierry Reding phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 62634b4f6d0SThierry Reding phy-names = "sata-phy"; 62734b4f6d0SThierry Reding status = "disabled"; 62834b4f6d0SThierry Reding }; 62934b4f6d0SThierry Reding 630be70771dSThierry Reding hda@70030000 { 63134b4f6d0SThierry Reding compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 63234b4f6d0SThierry Reding "nvidia,tegra30-hda"; 63334b4f6d0SThierry Reding reg = <0x0 0x70030000 0x0 0x10000>; 63434b4f6d0SThierry Reding interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 63534b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_HDA>, 63634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_HDA2HDMI>, 63734b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 63834b4f6d0SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 63934b4f6d0SThierry Reding resets = <&tegra_car 125>, /* hda */ 64034b4f6d0SThierry Reding <&tegra_car 128>, /* hda2hdmi */ 64134b4f6d0SThierry Reding <&tegra_car 111>; /* hda2codec_2x */ 64234b4f6d0SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 64334b4f6d0SThierry Reding status = "disabled"; 64434b4f6d0SThierry Reding }; 64534b4f6d0SThierry Reding 646be70771dSThierry Reding padctl: padctl@7009f000 { 64734b4f6d0SThierry Reding compatible = "nvidia,tegra132-xusb-padctl", 64834b4f6d0SThierry Reding "nvidia,tegra124-xusb-padctl"; 64934b4f6d0SThierry Reding reg = <0x0 0x7009f000 0x0 0x1000>; 65034b4f6d0SThierry Reding resets = <&tegra_car 142>; 65134b4f6d0SThierry Reding reset-names = "padctl"; 65234b4f6d0SThierry Reding 65334b4f6d0SThierry Reding #phy-cells = <1>; 65434b4f6d0SThierry Reding 65534b4f6d0SThierry Reding phys { 65634b4f6d0SThierry Reding pcie-0 { 65734b4f6d0SThierry Reding status = "disabled"; 65834b4f6d0SThierry Reding }; 65934b4f6d0SThierry Reding 66034b4f6d0SThierry Reding sata-0 { 66134b4f6d0SThierry Reding status = "disabled"; 66234b4f6d0SThierry Reding }; 66334b4f6d0SThierry Reding 66434b4f6d0SThierry Reding usb3-0 { 66534b4f6d0SThierry Reding status = "disabled"; 66634b4f6d0SThierry Reding }; 66734b4f6d0SThierry Reding 66834b4f6d0SThierry Reding usb3-1 { 66934b4f6d0SThierry Reding status = "disabled"; 67034b4f6d0SThierry Reding }; 67134b4f6d0SThierry Reding 67234b4f6d0SThierry Reding utmi-0 { 67334b4f6d0SThierry Reding status = "disabled"; 67434b4f6d0SThierry Reding }; 67534b4f6d0SThierry Reding 67634b4f6d0SThierry Reding utmi-1 { 67734b4f6d0SThierry Reding status = "disabled"; 67834b4f6d0SThierry Reding }; 67934b4f6d0SThierry Reding 68034b4f6d0SThierry Reding utmi-2 { 68134b4f6d0SThierry Reding status = "disabled"; 68234b4f6d0SThierry Reding }; 68334b4f6d0SThierry Reding }; 68434b4f6d0SThierry Reding }; 68534b4f6d0SThierry Reding 686be70771dSThierry Reding sdhci@700b0000 { 68734b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 68834b4f6d0SThierry Reding reg = <0x0 0x700b0000 0x0 0x200>; 68934b4f6d0SThierry Reding interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 69034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 69134b4f6d0SThierry Reding clock-names = "sdhci"; 69234b4f6d0SThierry Reding resets = <&tegra_car 14>; 69334b4f6d0SThierry Reding reset-names = "sdhci"; 69434b4f6d0SThierry Reding status = "disabled"; 69534b4f6d0SThierry Reding }; 69634b4f6d0SThierry Reding 697be70771dSThierry Reding sdhci@700b0200 { 69834b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 69934b4f6d0SThierry Reding reg = <0x0 0x700b0200 0x0 0x200>; 70034b4f6d0SThierry Reding interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 70134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 70234b4f6d0SThierry Reding clock-names = "sdhci"; 70334b4f6d0SThierry Reding resets = <&tegra_car 9>; 70434b4f6d0SThierry Reding reset-names = "sdhci"; 70534b4f6d0SThierry Reding status = "disabled"; 70634b4f6d0SThierry Reding }; 70734b4f6d0SThierry Reding 708be70771dSThierry Reding sdhci@700b0400 { 70934b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 71034b4f6d0SThierry Reding reg = <0x0 0x700b0400 0x0 0x200>; 71134b4f6d0SThierry Reding interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 71234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 71334b4f6d0SThierry Reding clock-names = "sdhci"; 71434b4f6d0SThierry Reding resets = <&tegra_car 69>; 71534b4f6d0SThierry Reding reset-names = "sdhci"; 71634b4f6d0SThierry Reding status = "disabled"; 71734b4f6d0SThierry Reding }; 71834b4f6d0SThierry Reding 719be70771dSThierry Reding sdhci@700b0600 { 72034b4f6d0SThierry Reding compatible = "nvidia,tegra124-sdhci"; 72134b4f6d0SThierry Reding reg = <0x0 0x700b0600 0x0 0x200>; 72234b4f6d0SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 72334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 72434b4f6d0SThierry Reding clock-names = "sdhci"; 72534b4f6d0SThierry Reding resets = <&tegra_car 15>; 72634b4f6d0SThierry Reding reset-names = "sdhci"; 72734b4f6d0SThierry Reding status = "disabled"; 72834b4f6d0SThierry Reding }; 72934b4f6d0SThierry Reding 730be70771dSThierry Reding soctherm: thermal-sensor@700e2000 { 7310fa2bfcdSWei Ni compatible = "nvidia,tegra132-soctherm"; 7320fa2bfcdSWei Ni reg = <0x0 0x700e2000 0x0 0x600>; 73334b4f6d0SThierry Reding interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 73434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 73534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_SOC_THERM>; 73634b4f6d0SThierry Reding clock-names = "tsensor", "soctherm"; 73734b4f6d0SThierry Reding resets = <&tegra_car 78>; 73834b4f6d0SThierry Reding reset-names = "soctherm"; 73934b4f6d0SThierry Reding #thermal-sensor-cells = <1>; 74034b4f6d0SThierry Reding }; 74134b4f6d0SThierry Reding 7420fa2bfcdSWei Ni thermal-zones { 7430fa2bfcdSWei Ni cpu { 7440fa2bfcdSWei Ni polling-delay-passive = <1000>; 7450fa2bfcdSWei Ni polling-delay = <0>; 7460fa2bfcdSWei Ni 7470fa2bfcdSWei Ni thermal-sensors = 7480fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 7490fa2bfcdSWei Ni }; 7500fa2bfcdSWei Ni mem { 7510fa2bfcdSWei Ni polling-delay-passive = <0>; 7520fa2bfcdSWei Ni polling-delay = <0>; 7530fa2bfcdSWei Ni 7540fa2bfcdSWei Ni thermal-sensors = 7550fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 7560fa2bfcdSWei Ni }; 7570fa2bfcdSWei Ni gpu { 7580fa2bfcdSWei Ni polling-delay-passive = <1000>; 7590fa2bfcdSWei Ni polling-delay = <0>; 7600fa2bfcdSWei Ni 7610fa2bfcdSWei Ni thermal-sensors = 7620fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 7630fa2bfcdSWei Ni }; 7640fa2bfcdSWei Ni pllx { 7650fa2bfcdSWei Ni polling-delay-passive = <0>; 7660fa2bfcdSWei Ni polling-delay = <0>; 7670fa2bfcdSWei Ni 7680fa2bfcdSWei Ni thermal-sensors = 7690fa2bfcdSWei Ni <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 7700fa2bfcdSWei Ni }; 7710fa2bfcdSWei Ni }; 7720fa2bfcdSWei Ni 773be70771dSThierry Reding ahub@70300000 { 77434b4f6d0SThierry Reding compatible = "nvidia,tegra124-ahub"; 77534b4f6d0SThierry Reding reg = <0x0 0x70300000 0x0 0x200>, 77634b4f6d0SThierry Reding <0x0 0x70300800 0x0 0x800>, 77734b4f6d0SThierry Reding <0x0 0x70300200 0x0 0x600>; 77834b4f6d0SThierry Reding interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 77934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 78034b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_APBIF>; 78134b4f6d0SThierry Reding clock-names = "d_audio", "apbif"; 78234b4f6d0SThierry Reding resets = <&tegra_car 106>, /* d_audio */ 78334b4f6d0SThierry Reding <&tegra_car 107>, /* apbif */ 78434b4f6d0SThierry Reding <&tegra_car 30>, /* i2s0 */ 78534b4f6d0SThierry Reding <&tegra_car 11>, /* i2s1 */ 78634b4f6d0SThierry Reding <&tegra_car 18>, /* i2s2 */ 78734b4f6d0SThierry Reding <&tegra_car 101>, /* i2s3 */ 78834b4f6d0SThierry Reding <&tegra_car 102>, /* i2s4 */ 78934b4f6d0SThierry Reding <&tegra_car 108>, /* dam0 */ 79034b4f6d0SThierry Reding <&tegra_car 109>, /* dam1 */ 79134b4f6d0SThierry Reding <&tegra_car 110>, /* dam2 */ 79234b4f6d0SThierry Reding <&tegra_car 10>, /* spdif */ 79334b4f6d0SThierry Reding <&tegra_car 153>, /* amx */ 79434b4f6d0SThierry Reding <&tegra_car 185>, /* amx1 */ 79534b4f6d0SThierry Reding <&tegra_car 154>, /* adx */ 79634b4f6d0SThierry Reding <&tegra_car 180>, /* adx1 */ 79734b4f6d0SThierry Reding <&tegra_car 186>, /* afc0 */ 79834b4f6d0SThierry Reding <&tegra_car 187>, /* afc1 */ 79934b4f6d0SThierry Reding <&tegra_car 188>, /* afc2 */ 80034b4f6d0SThierry Reding <&tegra_car 189>, /* afc3 */ 80134b4f6d0SThierry Reding <&tegra_car 190>, /* afc4 */ 80234b4f6d0SThierry Reding <&tegra_car 191>; /* afc5 */ 80334b4f6d0SThierry Reding reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 80434b4f6d0SThierry Reding "i2s3", "i2s4", "dam0", "dam1", "dam2", 80534b4f6d0SThierry Reding "spdif", "amx", "amx1", "adx", "adx1", 80634b4f6d0SThierry Reding "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 80734b4f6d0SThierry Reding dmas = <&apbdma 1>, <&apbdma 1>, 80834b4f6d0SThierry Reding <&apbdma 2>, <&apbdma 2>, 80934b4f6d0SThierry Reding <&apbdma 3>, <&apbdma 3>, 81034b4f6d0SThierry Reding <&apbdma 4>, <&apbdma 4>, 81134b4f6d0SThierry Reding <&apbdma 6>, <&apbdma 6>, 81234b4f6d0SThierry Reding <&apbdma 7>, <&apbdma 7>, 81334b4f6d0SThierry Reding <&apbdma 12>, <&apbdma 12>, 81434b4f6d0SThierry Reding <&apbdma 13>, <&apbdma 13>, 81534b4f6d0SThierry Reding <&apbdma 14>, <&apbdma 14>, 81634b4f6d0SThierry Reding <&apbdma 29>, <&apbdma 29>; 81734b4f6d0SThierry Reding dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 81834b4f6d0SThierry Reding "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 81934b4f6d0SThierry Reding "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 82034b4f6d0SThierry Reding "rx9", "tx9"; 82134b4f6d0SThierry Reding ranges; 82234b4f6d0SThierry Reding #address-cells = <2>; 82334b4f6d0SThierry Reding #size-cells = <2>; 82434b4f6d0SThierry Reding 825be70771dSThierry Reding tegra_i2s0: i2s@70301000 { 82634b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 82734b4f6d0SThierry Reding reg = <0x0 0x70301000 0x0 0x100>; 82834b4f6d0SThierry Reding nvidia,ahub-cif-ids = <4 4>; 82934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S0>; 83034b4f6d0SThierry Reding clock-names = "i2s"; 83134b4f6d0SThierry Reding resets = <&tegra_car 30>; 83234b4f6d0SThierry Reding reset-names = "i2s"; 83334b4f6d0SThierry Reding status = "disabled"; 83434b4f6d0SThierry Reding }; 83534b4f6d0SThierry Reding 836be70771dSThierry Reding tegra_i2s1: i2s@70301100 { 83734b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 83834b4f6d0SThierry Reding reg = <0x0 0x70301100 0x0 0x100>; 83934b4f6d0SThierry Reding nvidia,ahub-cif-ids = <5 5>; 84034b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S1>; 84134b4f6d0SThierry Reding clock-names = "i2s"; 84234b4f6d0SThierry Reding resets = <&tegra_car 11>; 84334b4f6d0SThierry Reding reset-names = "i2s"; 84434b4f6d0SThierry Reding status = "disabled"; 84534b4f6d0SThierry Reding }; 84634b4f6d0SThierry Reding 847be70771dSThierry Reding tegra_i2s2: i2s@70301200 { 84834b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 84934b4f6d0SThierry Reding reg = <0x0 0x70301200 0x0 0x100>; 85034b4f6d0SThierry Reding nvidia,ahub-cif-ids = <6 6>; 85134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S2>; 85234b4f6d0SThierry Reding clock-names = "i2s"; 85334b4f6d0SThierry Reding resets = <&tegra_car 18>; 85434b4f6d0SThierry Reding reset-names = "i2s"; 85534b4f6d0SThierry Reding status = "disabled"; 85634b4f6d0SThierry Reding }; 85734b4f6d0SThierry Reding 858be70771dSThierry Reding tegra_i2s3: i2s@70301300 { 85934b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 86034b4f6d0SThierry Reding reg = <0x0 0x70301300 0x0 0x100>; 86134b4f6d0SThierry Reding nvidia,ahub-cif-ids = <7 7>; 86234b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S3>; 86334b4f6d0SThierry Reding clock-names = "i2s"; 86434b4f6d0SThierry Reding resets = <&tegra_car 101>; 86534b4f6d0SThierry Reding reset-names = "i2s"; 86634b4f6d0SThierry Reding status = "disabled"; 86734b4f6d0SThierry Reding }; 86834b4f6d0SThierry Reding 869be70771dSThierry Reding tegra_i2s4: i2s@70301400 { 87034b4f6d0SThierry Reding compatible = "nvidia,tegra124-i2s"; 87134b4f6d0SThierry Reding reg = <0x0 0x70301400 0x0 0x100>; 87234b4f6d0SThierry Reding nvidia,ahub-cif-ids = <8 8>; 87334b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_I2S4>; 87434b4f6d0SThierry Reding clock-names = "i2s"; 87534b4f6d0SThierry Reding resets = <&tegra_car 102>; 87634b4f6d0SThierry Reding reset-names = "i2s"; 87734b4f6d0SThierry Reding status = "disabled"; 87834b4f6d0SThierry Reding }; 87934b4f6d0SThierry Reding }; 88034b4f6d0SThierry Reding 881be70771dSThierry Reding usb@7d000000 { 88234b4f6d0SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 88334b4f6d0SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>; 88434b4f6d0SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 88534b4f6d0SThierry Reding phy_type = "utmi"; 88634b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USBD>; 88734b4f6d0SThierry Reding clock-names = "usb"; 88834b4f6d0SThierry Reding resets = <&tegra_car 22>; 88934b4f6d0SThierry Reding reset-names = "usb"; 89034b4f6d0SThierry Reding nvidia,phy = <&phy1>; 89134b4f6d0SThierry Reding status = "disabled"; 89234b4f6d0SThierry Reding }; 89334b4f6d0SThierry Reding 894be70771dSThierry Reding phy1: usb-phy@7d000000 { 89534b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 89634b4f6d0SThierry Reding reg = <0x0 0x7d000000 0x0 0x4000>, 89734b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 89834b4f6d0SThierry Reding phy_type = "utmi"; 89934b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USBD>, 90034b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 90134b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 90234b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 90334b4f6d0SThierry Reding resets = <&tegra_car 22>, <&tegra_car 22>; 90434b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 90534b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 90634b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 90734b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 90834b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 90934b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 91034b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 91134b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 91234b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 91334b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 91434b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 91534b4f6d0SThierry Reding nvidia,has-utmi-pad-registers; 91634b4f6d0SThierry Reding status = "disabled"; 91734b4f6d0SThierry Reding }; 91834b4f6d0SThierry Reding 919be70771dSThierry Reding usb@7d004000 { 92034b4f6d0SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 92134b4f6d0SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>; 92234b4f6d0SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 92334b4f6d0SThierry Reding phy_type = "utmi"; 92434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB2>; 92534b4f6d0SThierry Reding clock-names = "usb"; 92634b4f6d0SThierry Reding resets = <&tegra_car 58>; 92734b4f6d0SThierry Reding reset-names = "usb"; 92834b4f6d0SThierry Reding nvidia,phy = <&phy2>; 92934b4f6d0SThierry Reding status = "disabled"; 93034b4f6d0SThierry Reding }; 93134b4f6d0SThierry Reding 932be70771dSThierry Reding phy2: usb-phy@7d004000 { 93334b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 93434b4f6d0SThierry Reding reg = <0x0 0x7d004000 0x0 0x4000>, 93534b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 93634b4f6d0SThierry Reding phy_type = "utmi"; 93734b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB2>, 93834b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 93934b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 94034b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 94134b4f6d0SThierry Reding resets = <&tegra_car 58>, <&tegra_car 22>; 94234b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 94334b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 94434b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 94534b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 94634b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 94734b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 94834b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 94934b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 95034b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 95134b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 95234b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 95334b4f6d0SThierry Reding status = "disabled"; 95434b4f6d0SThierry Reding }; 95534b4f6d0SThierry Reding 956be70771dSThierry Reding usb@7d008000 { 95734b4f6d0SThierry Reding compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 95834b4f6d0SThierry Reding reg = <0x0 0x7d008000 0x0 0x4000>; 95934b4f6d0SThierry Reding interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 96034b4f6d0SThierry Reding phy_type = "utmi"; 96134b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB3>; 96234b4f6d0SThierry Reding clock-names = "usb"; 96334b4f6d0SThierry Reding resets = <&tegra_car 59>; 96434b4f6d0SThierry Reding reset-names = "usb"; 96534b4f6d0SThierry Reding nvidia,phy = <&phy3>; 96634b4f6d0SThierry Reding status = "disabled"; 96734b4f6d0SThierry Reding }; 96834b4f6d0SThierry Reding 969be70771dSThierry Reding phy3: usb-phy@7d008000 { 97034b4f6d0SThierry Reding compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 97134b4f6d0SThierry Reding reg = <0x0 0x7d008000 0x0 0x4000>, 97234b4f6d0SThierry Reding <0x0 0x7d000000 0x0 0x4000>; 97334b4f6d0SThierry Reding phy_type = "utmi"; 97434b4f6d0SThierry Reding clocks = <&tegra_car TEGRA124_CLK_USB3>, 97534b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_PLL_U>, 97634b4f6d0SThierry Reding <&tegra_car TEGRA124_CLK_USBD>; 97734b4f6d0SThierry Reding clock-names = "reg", "pll_u", "utmi-pads"; 97834b4f6d0SThierry Reding resets = <&tegra_car 59>, <&tegra_car 22>; 97934b4f6d0SThierry Reding reset-names = "usb", "utmi-pads"; 98034b4f6d0SThierry Reding nvidia,hssync-start-delay = <0>; 98134b4f6d0SThierry Reding nvidia,idle-wait-delay = <17>; 98234b4f6d0SThierry Reding nvidia,elastic-limit = <16>; 98334b4f6d0SThierry Reding nvidia,term-range-adj = <6>; 98434b4f6d0SThierry Reding nvidia,xcvr-setup = <9>; 98534b4f6d0SThierry Reding nvidia,xcvr-lsfslew = <0>; 98634b4f6d0SThierry Reding nvidia,xcvr-lsrslew = <3>; 98734b4f6d0SThierry Reding nvidia,hssquelch-level = <2>; 98834b4f6d0SThierry Reding nvidia,hsdiscon-level = <5>; 98934b4f6d0SThierry Reding nvidia,xcvr-hsslew = <12>; 99034b4f6d0SThierry Reding status = "disabled"; 99134b4f6d0SThierry Reding }; 99234b4f6d0SThierry Reding 99334b4f6d0SThierry Reding cpus { 99434b4f6d0SThierry Reding #address-cells = <1>; 99534b4f6d0SThierry Reding #size-cells = <0>; 99634b4f6d0SThierry Reding 99734b4f6d0SThierry Reding cpu@0 { 99834b4f6d0SThierry Reding device_type = "cpu"; 99934b4f6d0SThierry Reding compatible = "nvidia,denver", "arm,armv8"; 100034b4f6d0SThierry Reding reg = <0>; 100134b4f6d0SThierry Reding }; 100234b4f6d0SThierry Reding 100334b4f6d0SThierry Reding cpu@1 { 100434b4f6d0SThierry Reding device_type = "cpu"; 100534b4f6d0SThierry Reding compatible = "nvidia,denver", "arm,armv8"; 100634b4f6d0SThierry Reding reg = <1>; 100734b4f6d0SThierry Reding }; 100834b4f6d0SThierry Reding }; 100934b4f6d0SThierry Reding 101034b4f6d0SThierry Reding timer { 101134b4f6d0SThierry Reding compatible = "arm,armv7-timer"; 101234b4f6d0SThierry Reding interrupts = <GIC_PPI 13 101334b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 101434b4f6d0SThierry Reding <GIC_PPI 14 101534b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 101634b4f6d0SThierry Reding <GIC_PPI 11 101734b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 101834b4f6d0SThierry Reding <GIC_PPI 10 101934b4f6d0SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 102034b4f6d0SThierry Reding interrupt-parent = <&gic>; 102134b4f6d0SThierry Reding }; 102234b4f6d0SThierry Reding}; 1023