16ff94537SFabien Parent// SPDX-License-Identifier: (GPL-2.0 OR MIT) 26ff94537SFabien Parent/* 36ff94537SFabien Parent * (C) 2018 MediaTek Inc. 46ff94537SFabien Parent * Copyright (C) 2022 BayLibre SAS 56ff94537SFabien Parent * Fabien Parent <fparent@baylibre.com> 66ff94537SFabien Parent * Bernhard Rosenkränzer <bero@baylibre.com> 76ff94537SFabien Parent */ 86ff94537SFabien Parent#include <dt-bindings/clock/mediatek,mt8365-clk.h> 96ff94537SFabien Parent#include <dt-bindings/interrupt-controller/arm-gic.h> 106ff94537SFabien Parent#include <dt-bindings/interrupt-controller/irq.h> 116ff94537SFabien Parent#include <dt-bindings/phy/phy.h> 126ff94537SFabien Parent 136ff94537SFabien Parent/ { 146ff94537SFabien Parent compatible = "mediatek,mt8365"; 156ff94537SFabien Parent interrupt-parent = <&sysirq>; 166ff94537SFabien Parent #address-cells = <2>; 176ff94537SFabien Parent #size-cells = <2>; 186ff94537SFabien Parent 196ff94537SFabien Parent cpus { 206ff94537SFabien Parent #address-cells = <1>; 216ff94537SFabien Parent #size-cells = <0>; 226ff94537SFabien Parent 236ff94537SFabien Parent cpu-map { 246ff94537SFabien Parent cluster0 { 256ff94537SFabien Parent core0 { 266ff94537SFabien Parent cpu = <&cpu0>; 276ff94537SFabien Parent }; 286ff94537SFabien Parent core1 { 296ff94537SFabien Parent cpu = <&cpu1>; 306ff94537SFabien Parent }; 316ff94537SFabien Parent core2 { 326ff94537SFabien Parent cpu = <&cpu2>; 336ff94537SFabien Parent }; 346ff94537SFabien Parent core3 { 356ff94537SFabien Parent cpu = <&cpu3>; 366ff94537SFabien Parent }; 376ff94537SFabien Parent }; 386ff94537SFabien Parent }; 396ff94537SFabien Parent 406ff94537SFabien Parent cpu0: cpu@0 { 416ff94537SFabien Parent device_type = "cpu"; 426ff94537SFabien Parent compatible = "arm,cortex-a53"; 436ff94537SFabien Parent reg = <0x0>; 446ff94537SFabien Parent #cooling-cells = <2>; 456ff94537SFabien Parent enable-method = "psci"; 466ff94537SFabien Parent i-cache-size = <0x8000>; 476ff94537SFabien Parent i-cache-line-size = <64>; 486ff94537SFabien Parent i-cache-sets = <256>; 496ff94537SFabien Parent d-cache-size = <0x8000>; 506ff94537SFabien Parent d-cache-line-size = <64>; 516ff94537SFabien Parent d-cache-sets = <256>; 526ff94537SFabien Parent next-level-cache = <&l2>; 536ff94537SFabien Parent }; 546ff94537SFabien Parent 556ff94537SFabien Parent cpu1: cpu@1 { 566ff94537SFabien Parent device_type = "cpu"; 576ff94537SFabien Parent compatible = "arm,cortex-a53"; 586ff94537SFabien Parent reg = <0x1>; 596ff94537SFabien Parent #cooling-cells = <2>; 606ff94537SFabien Parent enable-method = "psci"; 616ff94537SFabien Parent i-cache-size = <0x8000>; 626ff94537SFabien Parent i-cache-line-size = <64>; 636ff94537SFabien Parent i-cache-sets = <256>; 646ff94537SFabien Parent d-cache-size = <0x8000>; 656ff94537SFabien Parent d-cache-line-size = <64>; 666ff94537SFabien Parent d-cache-sets = <256>; 676ff94537SFabien Parent next-level-cache = <&l2>; 686ff94537SFabien Parent }; 696ff94537SFabien Parent 706ff94537SFabien Parent cpu2: cpu@2 { 716ff94537SFabien Parent device_type = "cpu"; 726ff94537SFabien Parent compatible = "arm,cortex-a53"; 736ff94537SFabien Parent reg = <0x2>; 746ff94537SFabien Parent #cooling-cells = <2>; 756ff94537SFabien Parent enable-method = "psci"; 766ff94537SFabien Parent i-cache-size = <0x8000>; 776ff94537SFabien Parent i-cache-line-size = <64>; 786ff94537SFabien Parent i-cache-sets = <256>; 796ff94537SFabien Parent d-cache-size = <0x8000>; 806ff94537SFabien Parent d-cache-line-size = <64>; 816ff94537SFabien Parent d-cache-sets = <256>; 826ff94537SFabien Parent next-level-cache = <&l2>; 836ff94537SFabien Parent }; 846ff94537SFabien Parent 856ff94537SFabien Parent cpu3: cpu@3 { 866ff94537SFabien Parent device_type = "cpu"; 876ff94537SFabien Parent compatible = "arm,cortex-a53"; 886ff94537SFabien Parent reg = <0x3>; 896ff94537SFabien Parent #cooling-cells = <2>; 906ff94537SFabien Parent enable-method = "psci"; 916ff94537SFabien Parent i-cache-size = <0x8000>; 926ff94537SFabien Parent i-cache-line-size = <64>; 936ff94537SFabien Parent i-cache-sets = <256>; 946ff94537SFabien Parent d-cache-size = <0x8000>; 956ff94537SFabien Parent d-cache-line-size = <64>; 966ff94537SFabien Parent d-cache-sets = <256>; 976ff94537SFabien Parent next-level-cache = <&l2>; 986ff94537SFabien Parent }; 996ff94537SFabien Parent 1006ff94537SFabien Parent l2: l2-cache { 1016ff94537SFabien Parent compatible = "cache"; 1026ff94537SFabien Parent cache-level = <2>; 1036ff94537SFabien Parent cache-size = <0x80000>; 1046ff94537SFabien Parent cache-line-size = <64>; 1056ff94537SFabien Parent cache-sets = <512>; 1066ff94537SFabien Parent cache-unified; 1076ff94537SFabien Parent }; 1086ff94537SFabien Parent }; 1096ff94537SFabien Parent 1106ff94537SFabien Parent clk26m: oscillator { 1116ff94537SFabien Parent compatible = "fixed-clock"; 1126ff94537SFabien Parent #clock-cells = <0>; 1136ff94537SFabien Parent clock-frequency = <26000000>; 1146ff94537SFabien Parent clock-output-names = "clk26m"; 1156ff94537SFabien Parent }; 1166ff94537SFabien Parent 1176ff94537SFabien Parent psci { 1186ff94537SFabien Parent compatible = "arm,psci-1.0"; 1196ff94537SFabien Parent method = "smc"; 1206ff94537SFabien Parent }; 1216ff94537SFabien Parent 1226ff94537SFabien Parent soc { 1236ff94537SFabien Parent #address-cells = <2>; 1246ff94537SFabien Parent #size-cells = <2>; 1256ff94537SFabien Parent compatible = "simple-bus"; 1266ff94537SFabien Parent ranges; 1276ff94537SFabien Parent 1286ff94537SFabien Parent gic: interrupt-controller@c000000 { 1296ff94537SFabien Parent compatible = "arm,gic-v3"; 1306ff94537SFabien Parent #interrupt-cells = <3>; 1316ff94537SFabien Parent interrupt-parent = <&gic>; 1326ff94537SFabien Parent interrupt-controller; 1336ff94537SFabien Parent reg = <0 0x0c000000 0 0x10000>, /* GICD */ 1346ff94537SFabien Parent <0 0x0c080000 0 0x80000>, /* GICR */ 1356ff94537SFabien Parent <0 0x0c400000 0 0x2000>, /* GICC */ 1366ff94537SFabien Parent <0 0x0c410000 0 0x1000>, /* GICH */ 1376ff94537SFabien Parent <0 0x0c420000 0 0x2000>; /* GICV */ 1386ff94537SFabien Parent 1396ff94537SFabien Parent interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1406ff94537SFabien Parent }; 1416ff94537SFabien Parent 1426ff94537SFabien Parent topckgen: syscon@10000000 { 1436ff94537SFabien Parent compatible = "mediatek,mt8365-topckgen", "syscon"; 1446ff94537SFabien Parent reg = <0 0x10000000 0 0x1000>; 1456ff94537SFabien Parent #clock-cells = <1>; 1466ff94537SFabien Parent }; 1476ff94537SFabien Parent 1486ff94537SFabien Parent infracfg: syscon@10001000 { 1496ff94537SFabien Parent compatible = "mediatek,mt8365-infracfg", "syscon"; 1506ff94537SFabien Parent reg = <0 0x10001000 0 0x1000>; 1516ff94537SFabien Parent #clock-cells = <1>; 1526ff94537SFabien Parent }; 1536ff94537SFabien Parent 1546ff94537SFabien Parent pericfg: syscon@10003000 { 1556ff94537SFabien Parent compatible = "mediatek,mt8365-pericfg", "syscon"; 1566ff94537SFabien Parent reg = <0 0x10003000 0 0x1000>; 1576ff94537SFabien Parent #clock-cells = <1>; 1586ff94537SFabien Parent }; 1596ff94537SFabien Parent 1606ff94537SFabien Parent syscfg_pctl: syscfg-pctl@10005000 { 1616ff94537SFabien Parent compatible = "mediatek,mt8365-syscfg", "syscon"; 1626ff94537SFabien Parent reg = <0 0x10005000 0 0x1000>; 1636ff94537SFabien Parent }; 1646ff94537SFabien Parent 1656ff94537SFabien Parent pio: pinctrl@1000b000 { 1666ff94537SFabien Parent compatible = "mediatek,mt8365-pinctrl"; 1676ff94537SFabien Parent reg = <0 0x1000b000 0 0x1000>; 1686ff94537SFabien Parent mediatek,pctl-regmap = <&syscfg_pctl>; 1696ff94537SFabien Parent gpio-controller; 1706ff94537SFabien Parent #gpio-cells = <2>; 1716ff94537SFabien Parent interrupt-controller; 1726ff94537SFabien Parent #interrupt-cells = <2>; 1736ff94537SFabien Parent interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1746ff94537SFabien Parent }; 1756ff94537SFabien Parent 1766ff94537SFabien Parent apmixedsys: syscon@1000c000 { 1776ff94537SFabien Parent compatible = "mediatek,mt8365-apmixedsys", "syscon"; 1786ff94537SFabien Parent reg = <0 0x1000c000 0 0x1000>; 1796ff94537SFabien Parent #clock-cells = <1>; 1806ff94537SFabien Parent }; 1816ff94537SFabien Parent 1826ff94537SFabien Parent keypad: keypad@10010000 { 1836ff94537SFabien Parent compatible = "mediatek,mt6779-keypad"; 1846ff94537SFabien Parent reg = <0 0x10010000 0 0x1000>; 1856ff94537SFabien Parent wakeup-source; 1866ff94537SFabien Parent interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 1876ff94537SFabien Parent clocks = <&clk26m>; 1886ff94537SFabien Parent clock-names = "kpd"; 1896ff94537SFabien Parent status = "disabled"; 1906ff94537SFabien Parent }; 1916ff94537SFabien Parent 1926ff94537SFabien Parent mcucfg: syscon@10200000 { 1936ff94537SFabien Parent compatible = "mediatek,mt8365-mcucfg", "syscon"; 1946ff94537SFabien Parent reg = <0 0x10200000 0 0x2000>; 1956ff94537SFabien Parent #clock-cells = <1>; 1966ff94537SFabien Parent }; 1976ff94537SFabien Parent 1986ff94537SFabien Parent sysirq: interrupt-controller@10200a80 { 1996ff94537SFabien Parent compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 2006ff94537SFabien Parent interrupt-controller; 2016ff94537SFabien Parent #interrupt-cells = <3>; 2026ff94537SFabien Parent interrupt-parent = <&gic>; 2036ff94537SFabien Parent reg = <0 0x10200a80 0 0x20>; 2046ff94537SFabien Parent }; 2056ff94537SFabien Parent 2066ff94537SFabien Parent infracfg_nao: infracfg@1020e000 { 2076ff94537SFabien Parent compatible = "mediatek,mt8365-infracfg", "syscon"; 2086ff94537SFabien Parent reg = <0 0x1020e000 0 0x1000>; 2096ff94537SFabien Parent #clock-cells = <1>; 2106ff94537SFabien Parent }; 2116ff94537SFabien Parent 2126ff94537SFabien Parent rng: rng@1020f000 { 2136ff94537SFabien Parent compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 2146ff94537SFabien Parent reg = <0 0x1020f000 0 0x100>; 2156ff94537SFabien Parent clocks = <&infracfg CLK_IFR_TRNG>; 2166ff94537SFabien Parent clock-names = "rng"; 2176ff94537SFabien Parent }; 2186ff94537SFabien Parent 2196ff94537SFabien Parent apdma: dma-controller@11000280 { 2206ff94537SFabien Parent compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 2216ff94537SFabien Parent reg = <0 0x11000280 0 0x80>, 2226ff94537SFabien Parent <0 0x11000300 0 0x80>, 2236ff94537SFabien Parent <0 0x11000380 0 0x80>, 2246ff94537SFabien Parent <0 0x11000400 0 0x80>, 2256ff94537SFabien Parent <0 0x11000580 0 0x80>, 2266ff94537SFabien Parent <0 0x11000600 0 0x80>; 2276ff94537SFabien Parent interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 2286ff94537SFabien Parent <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 2296ff94537SFabien Parent <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 2306ff94537SFabien Parent <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 2316ff94537SFabien Parent <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 2326ff94537SFabien Parent <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 2336ff94537SFabien Parent dma-requests = <6>; 2346ff94537SFabien Parent clocks = <&infracfg CLK_IFR_AP_DMA>; 2356ff94537SFabien Parent clock-names = "apdma"; 2366ff94537SFabien Parent #dma-cells = <1>; 2376ff94537SFabien Parent }; 2386ff94537SFabien Parent 2396ff94537SFabien Parent uart0: serial@11002000 { 2406ff94537SFabien Parent compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 2416ff94537SFabien Parent reg = <0 0x11002000 0 0x1000>; 2426ff94537SFabien Parent interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 2436ff94537SFabien Parent clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 2446ff94537SFabien Parent clock-names = "baud", "bus"; 2456ff94537SFabien Parent dmas = <&apdma 0>, <&apdma 1>; 2466ff94537SFabien Parent dma-names = "tx", "rx"; 2476ff94537SFabien Parent status = "disabled"; 2486ff94537SFabien Parent }; 2496ff94537SFabien Parent 2506ff94537SFabien Parent uart1: serial@11003000 { 2516ff94537SFabien Parent compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 2526ff94537SFabien Parent reg = <0 0x11003000 0 0x1000>; 2536ff94537SFabien Parent interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 2546ff94537SFabien Parent clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 2556ff94537SFabien Parent clock-names = "baud", "bus"; 2566ff94537SFabien Parent dmas = <&apdma 2>, <&apdma 3>; 2576ff94537SFabien Parent dma-names = "tx", "rx"; 2586ff94537SFabien Parent status = "disabled"; 2596ff94537SFabien Parent }; 2606ff94537SFabien Parent 2616ff94537SFabien Parent uart2: serial@11004000 { 2626ff94537SFabien Parent compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 2636ff94537SFabien Parent reg = <0 0x11004000 0 0x1000>; 2646ff94537SFabien Parent interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 2656ff94537SFabien Parent clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 2666ff94537SFabien Parent clock-names = "baud", "bus"; 2676ff94537SFabien Parent dmas = <&apdma 4>, <&apdma 5>; 2686ff94537SFabien Parent dma-names = "tx", "rx"; 2696ff94537SFabien Parent status = "disabled"; 2706ff94537SFabien Parent }; 2716ff94537SFabien Parent 2726ff94537SFabien Parent pwm: pwm@11006000 { 2736ff94537SFabien Parent compatible = "mediatek,mt8365-pwm"; 2746ff94537SFabien Parent reg = <0 0x11006000 0 0x1000>; 2756ff94537SFabien Parent #pwm-cells = <2>; 2766ff94537SFabien Parent interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 2776ff94537SFabien Parent clocks = <&infracfg CLK_IFR_PWM_HCLK>, 2786ff94537SFabien Parent <&infracfg CLK_IFR_PWM>, 2796ff94537SFabien Parent <&infracfg CLK_IFR_PWM1>, 2806ff94537SFabien Parent <&infracfg CLK_IFR_PWM2>, 2816ff94537SFabien Parent <&infracfg CLK_IFR_PWM3>; 2826ff94537SFabien Parent clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 2836ff94537SFabien Parent }; 2846ff94537SFabien Parent 285*dbf17e13SAlexandre Mergnat i2c0: i2c@11007000 { 286*dbf17e13SAlexandre Mergnat compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 287*dbf17e13SAlexandre Mergnat reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 288*dbf17e13SAlexandre Mergnat interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 289*dbf17e13SAlexandre Mergnat clock-div = <1>; 290*dbf17e13SAlexandre Mergnat clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 291*dbf17e13SAlexandre Mergnat clock-names = "main", "dma"; 292*dbf17e13SAlexandre Mergnat #address-cells = <1>; 293*dbf17e13SAlexandre Mergnat #size-cells = <0>; 294*dbf17e13SAlexandre Mergnat status = "disabled"; 295*dbf17e13SAlexandre Mergnat }; 296*dbf17e13SAlexandre Mergnat 297*dbf17e13SAlexandre Mergnat i2c1: i2c@11008000 { 298*dbf17e13SAlexandre Mergnat compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 299*dbf17e13SAlexandre Mergnat reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 300*dbf17e13SAlexandre Mergnat interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 301*dbf17e13SAlexandre Mergnat clock-div = <1>; 302*dbf17e13SAlexandre Mergnat clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 303*dbf17e13SAlexandre Mergnat clock-names = "main", "dma"; 304*dbf17e13SAlexandre Mergnat #address-cells = <1>; 305*dbf17e13SAlexandre Mergnat #size-cells = <0>; 306*dbf17e13SAlexandre Mergnat status = "disabled"; 307*dbf17e13SAlexandre Mergnat }; 308*dbf17e13SAlexandre Mergnat 309*dbf17e13SAlexandre Mergnat i2c2: i2c@11009000 { 310*dbf17e13SAlexandre Mergnat compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 311*dbf17e13SAlexandre Mergnat reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 312*dbf17e13SAlexandre Mergnat interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 313*dbf17e13SAlexandre Mergnat clock-div = <1>; 314*dbf17e13SAlexandre Mergnat clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 315*dbf17e13SAlexandre Mergnat clock-names = "main", "dma"; 316*dbf17e13SAlexandre Mergnat #address-cells = <1>; 317*dbf17e13SAlexandre Mergnat #size-cells = <0>; 318*dbf17e13SAlexandre Mergnat status = "disabled"; 319*dbf17e13SAlexandre Mergnat }; 320*dbf17e13SAlexandre Mergnat 3216ff94537SFabien Parent spi: spi@1100a000 { 3226ff94537SFabien Parent compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 3236ff94537SFabien Parent reg = <0 0x1100a000 0 0x100>; 3246ff94537SFabien Parent #address-cells = <1>; 3256ff94537SFabien Parent #size-cells = <0>; 3266ff94537SFabien Parent interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 3276ff94537SFabien Parent clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 3286ff94537SFabien Parent <&topckgen CLK_TOP_SPI_SEL>, 3296ff94537SFabien Parent <&infracfg CLK_IFR_SPI0>; 3306ff94537SFabien Parent clock-names = "parent-clk", "sel-clk", "spi-clk"; 3316ff94537SFabien Parent status = "disabled"; 3326ff94537SFabien Parent }; 3336ff94537SFabien Parent 334*dbf17e13SAlexandre Mergnat i2c3: i2c@1100f000 { 335*dbf17e13SAlexandre Mergnat compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 336*dbf17e13SAlexandre Mergnat reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 337*dbf17e13SAlexandre Mergnat interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 338*dbf17e13SAlexandre Mergnat clock-div = <1>; 339*dbf17e13SAlexandre Mergnat clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 340*dbf17e13SAlexandre Mergnat clock-names = "main", "dma"; 341*dbf17e13SAlexandre Mergnat #address-cells = <1>; 342*dbf17e13SAlexandre Mergnat #size-cells = <0>; 343*dbf17e13SAlexandre Mergnat status = "disabled"; 344*dbf17e13SAlexandre Mergnat }; 345*dbf17e13SAlexandre Mergnat 3466ff94537SFabien Parent ssusb: usb@11201000 { 3476ff94537SFabien Parent compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 3486ff94537SFabien Parent reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 3496ff94537SFabien Parent reg-names = "mac", "ippc"; 3506ff94537SFabien Parent interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 3516ff94537SFabien Parent phys = <&u2port0 PHY_TYPE_USB2>, 3526ff94537SFabien Parent <&u2port1 PHY_TYPE_USB2>; 3536ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 3546ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_REF>, 3556ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_SYS>, 3566ff94537SFabien Parent <&infracfg CLK_IFR_ICUSB>; 3576ff94537SFabien Parent clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 3586ff94537SFabien Parent #address-cells = <2>; 3596ff94537SFabien Parent #size-cells = <2>; 3606ff94537SFabien Parent ranges; 3616ff94537SFabien Parent status = "disabled"; 3626ff94537SFabien Parent 3636ff94537SFabien Parent usb_host: usb@11200000 { 3646ff94537SFabien Parent compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 3656ff94537SFabien Parent reg = <0 0x11200000 0 0x1000>; 3666ff94537SFabien Parent reg-names = "mac"; 3676ff94537SFabien Parent interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 3686ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 3696ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_REF>, 3706ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_SYS>, 3716ff94537SFabien Parent <&infracfg CLK_IFR_ICUSB>, 3726ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_XHCI>; 3736ff94537SFabien Parent clock-names = "sys_ck", "ref_ck", "mcu_ck", 3746ff94537SFabien Parent "dma_ck", "xhci_ck"; 3756ff94537SFabien Parent status = "disabled"; 3766ff94537SFabien Parent }; 3776ff94537SFabien Parent }; 3786ff94537SFabien Parent 3796ff94537SFabien Parent u3phy: t-phy@11cc0000 { 3806ff94537SFabien Parent compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 3816ff94537SFabien Parent #address-cells = <1>; 3826ff94537SFabien Parent #size-cells = <1>; 3836ff94537SFabien Parent ranges = <0 0 0x11cc0000 0x9000>; 3846ff94537SFabien Parent 3856ff94537SFabien Parent u2port0: usb-phy@0 { 3866ff94537SFabien Parent reg = <0x0 0x400>; 3876ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 3886ff94537SFabien Parent <&topckgen CLK_TOP_USB20_48M_EN>; 3896ff94537SFabien Parent clock-names = "ref", "da_ref"; 3906ff94537SFabien Parent #phy-cells = <1>; 3916ff94537SFabien Parent }; 3926ff94537SFabien Parent 3936ff94537SFabien Parent u2port1: usb-phy@1000 { 3946ff94537SFabien Parent reg = <0x1000 0x400>; 3956ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 3966ff94537SFabien Parent <&topckgen CLK_TOP_USB20_48M_EN>; 3976ff94537SFabien Parent clock-names = "ref", "da_ref"; 3986ff94537SFabien Parent #phy-cells = <1>; 3996ff94537SFabien Parent }; 4006ff94537SFabien Parent }; 4016ff94537SFabien Parent }; 4026ff94537SFabien Parent 4036ff94537SFabien Parent timer { 4046ff94537SFabien Parent compatible = "arm,armv8-timer"; 4056ff94537SFabien Parent interrupt-parent = <&gic>; 4066ff94537SFabien Parent interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4076ff94537SFabien Parent <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4086ff94537SFabien Parent <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4096ff94537SFabien Parent <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4106ff94537SFabien Parent }; 4116ff94537SFabien Parent 4126ff94537SFabien Parent system_clk: dummy13m { 4136ff94537SFabien Parent compatible = "fixed-clock"; 4146ff94537SFabien Parent clock-frequency = <13000000>; 4156ff94537SFabien Parent #clock-cells = <0>; 4166ff94537SFabien Parent }; 4176ff94537SFabien Parent 4186ff94537SFabien Parent systimer: timer@10017000 { 4196ff94537SFabien Parent compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 4206ff94537SFabien Parent reg = <0 0x10017000 0 0x100>; 4216ff94537SFabien Parent interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4226ff94537SFabien Parent clocks = <&system_clk>; 4236ff94537SFabien Parent clock-names = "clk13m"; 4246ff94537SFabien Parent }; 4256ff94537SFabien Parent}; 426