1*6ff94537SFabien Parent// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*6ff94537SFabien Parent/* 3*6ff94537SFabien Parent * (C) 2018 MediaTek Inc. 4*6ff94537SFabien Parent * Copyright (C) 2022 BayLibre SAS 5*6ff94537SFabien Parent * Fabien Parent <fparent@baylibre.com> 6*6ff94537SFabien Parent * Bernhard Rosenkränzer <bero@baylibre.com> 7*6ff94537SFabien Parent */ 8*6ff94537SFabien Parent#include <dt-bindings/clock/mediatek,mt8365-clk.h> 9*6ff94537SFabien Parent#include <dt-bindings/interrupt-controller/arm-gic.h> 10*6ff94537SFabien Parent#include <dt-bindings/interrupt-controller/irq.h> 11*6ff94537SFabien Parent#include <dt-bindings/phy/phy.h> 12*6ff94537SFabien Parent 13*6ff94537SFabien Parent/ { 14*6ff94537SFabien Parent compatible = "mediatek,mt8365"; 15*6ff94537SFabien Parent interrupt-parent = <&sysirq>; 16*6ff94537SFabien Parent #address-cells = <2>; 17*6ff94537SFabien Parent #size-cells = <2>; 18*6ff94537SFabien Parent 19*6ff94537SFabien Parent cpus { 20*6ff94537SFabien Parent #address-cells = <1>; 21*6ff94537SFabien Parent #size-cells = <0>; 22*6ff94537SFabien Parent 23*6ff94537SFabien Parent cpu-map { 24*6ff94537SFabien Parent cluster0 { 25*6ff94537SFabien Parent core0 { 26*6ff94537SFabien Parent cpu = <&cpu0>; 27*6ff94537SFabien Parent }; 28*6ff94537SFabien Parent core1 { 29*6ff94537SFabien Parent cpu = <&cpu1>; 30*6ff94537SFabien Parent }; 31*6ff94537SFabien Parent core2 { 32*6ff94537SFabien Parent cpu = <&cpu2>; 33*6ff94537SFabien Parent }; 34*6ff94537SFabien Parent core3 { 35*6ff94537SFabien Parent cpu = <&cpu3>; 36*6ff94537SFabien Parent }; 37*6ff94537SFabien Parent }; 38*6ff94537SFabien Parent }; 39*6ff94537SFabien Parent 40*6ff94537SFabien Parent cpu0: cpu@0 { 41*6ff94537SFabien Parent device_type = "cpu"; 42*6ff94537SFabien Parent compatible = "arm,cortex-a53"; 43*6ff94537SFabien Parent reg = <0x0>; 44*6ff94537SFabien Parent #cooling-cells = <2>; 45*6ff94537SFabien Parent enable-method = "psci"; 46*6ff94537SFabien Parent i-cache-size = <0x8000>; 47*6ff94537SFabien Parent i-cache-line-size = <64>; 48*6ff94537SFabien Parent i-cache-sets = <256>; 49*6ff94537SFabien Parent d-cache-size = <0x8000>; 50*6ff94537SFabien Parent d-cache-line-size = <64>; 51*6ff94537SFabien Parent d-cache-sets = <256>; 52*6ff94537SFabien Parent next-level-cache = <&l2>; 53*6ff94537SFabien Parent }; 54*6ff94537SFabien Parent 55*6ff94537SFabien Parent cpu1: cpu@1 { 56*6ff94537SFabien Parent device_type = "cpu"; 57*6ff94537SFabien Parent compatible = "arm,cortex-a53"; 58*6ff94537SFabien Parent reg = <0x1>; 59*6ff94537SFabien Parent #cooling-cells = <2>; 60*6ff94537SFabien Parent enable-method = "psci"; 61*6ff94537SFabien Parent i-cache-size = <0x8000>; 62*6ff94537SFabien Parent i-cache-line-size = <64>; 63*6ff94537SFabien Parent i-cache-sets = <256>; 64*6ff94537SFabien Parent d-cache-size = <0x8000>; 65*6ff94537SFabien Parent d-cache-line-size = <64>; 66*6ff94537SFabien Parent d-cache-sets = <256>; 67*6ff94537SFabien Parent next-level-cache = <&l2>; 68*6ff94537SFabien Parent }; 69*6ff94537SFabien Parent 70*6ff94537SFabien Parent cpu2: cpu@2 { 71*6ff94537SFabien Parent device_type = "cpu"; 72*6ff94537SFabien Parent compatible = "arm,cortex-a53"; 73*6ff94537SFabien Parent reg = <0x2>; 74*6ff94537SFabien Parent #cooling-cells = <2>; 75*6ff94537SFabien Parent enable-method = "psci"; 76*6ff94537SFabien Parent i-cache-size = <0x8000>; 77*6ff94537SFabien Parent i-cache-line-size = <64>; 78*6ff94537SFabien Parent i-cache-sets = <256>; 79*6ff94537SFabien Parent d-cache-size = <0x8000>; 80*6ff94537SFabien Parent d-cache-line-size = <64>; 81*6ff94537SFabien Parent d-cache-sets = <256>; 82*6ff94537SFabien Parent next-level-cache = <&l2>; 83*6ff94537SFabien Parent }; 84*6ff94537SFabien Parent 85*6ff94537SFabien Parent cpu3: cpu@3 { 86*6ff94537SFabien Parent device_type = "cpu"; 87*6ff94537SFabien Parent compatible = "arm,cortex-a53"; 88*6ff94537SFabien Parent reg = <0x3>; 89*6ff94537SFabien Parent #cooling-cells = <2>; 90*6ff94537SFabien Parent enable-method = "psci"; 91*6ff94537SFabien Parent i-cache-size = <0x8000>; 92*6ff94537SFabien Parent i-cache-line-size = <64>; 93*6ff94537SFabien Parent i-cache-sets = <256>; 94*6ff94537SFabien Parent d-cache-size = <0x8000>; 95*6ff94537SFabien Parent d-cache-line-size = <64>; 96*6ff94537SFabien Parent d-cache-sets = <256>; 97*6ff94537SFabien Parent next-level-cache = <&l2>; 98*6ff94537SFabien Parent }; 99*6ff94537SFabien Parent 100*6ff94537SFabien Parent l2: l2-cache { 101*6ff94537SFabien Parent compatible = "cache"; 102*6ff94537SFabien Parent cache-level = <2>; 103*6ff94537SFabien Parent cache-size = <0x80000>; 104*6ff94537SFabien Parent cache-line-size = <64>; 105*6ff94537SFabien Parent cache-sets = <512>; 106*6ff94537SFabien Parent cache-unified; 107*6ff94537SFabien Parent }; 108*6ff94537SFabien Parent }; 109*6ff94537SFabien Parent 110*6ff94537SFabien Parent clk26m: oscillator { 111*6ff94537SFabien Parent compatible = "fixed-clock"; 112*6ff94537SFabien Parent #clock-cells = <0>; 113*6ff94537SFabien Parent clock-frequency = <26000000>; 114*6ff94537SFabien Parent clock-output-names = "clk26m"; 115*6ff94537SFabien Parent }; 116*6ff94537SFabien Parent 117*6ff94537SFabien Parent psci { 118*6ff94537SFabien Parent compatible = "arm,psci-1.0"; 119*6ff94537SFabien Parent method = "smc"; 120*6ff94537SFabien Parent }; 121*6ff94537SFabien Parent 122*6ff94537SFabien Parent soc { 123*6ff94537SFabien Parent #address-cells = <2>; 124*6ff94537SFabien Parent #size-cells = <2>; 125*6ff94537SFabien Parent compatible = "simple-bus"; 126*6ff94537SFabien Parent ranges; 127*6ff94537SFabien Parent 128*6ff94537SFabien Parent gic: interrupt-controller@c000000 { 129*6ff94537SFabien Parent compatible = "arm,gic-v3"; 130*6ff94537SFabien Parent #interrupt-cells = <3>; 131*6ff94537SFabien Parent interrupt-parent = <&gic>; 132*6ff94537SFabien Parent interrupt-controller; 133*6ff94537SFabien Parent reg = <0 0x0c000000 0 0x10000>, /* GICD */ 134*6ff94537SFabien Parent <0 0x0c080000 0 0x80000>, /* GICR */ 135*6ff94537SFabien Parent <0 0x0c400000 0 0x2000>, /* GICC */ 136*6ff94537SFabien Parent <0 0x0c410000 0 0x1000>, /* GICH */ 137*6ff94537SFabien Parent <0 0x0c420000 0 0x2000>; /* GICV */ 138*6ff94537SFabien Parent 139*6ff94537SFabien Parent interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 140*6ff94537SFabien Parent }; 141*6ff94537SFabien Parent 142*6ff94537SFabien Parent topckgen: syscon@10000000 { 143*6ff94537SFabien Parent compatible = "mediatek,mt8365-topckgen", "syscon"; 144*6ff94537SFabien Parent reg = <0 0x10000000 0 0x1000>; 145*6ff94537SFabien Parent #clock-cells = <1>; 146*6ff94537SFabien Parent }; 147*6ff94537SFabien Parent 148*6ff94537SFabien Parent infracfg: syscon@10001000 { 149*6ff94537SFabien Parent compatible = "mediatek,mt8365-infracfg", "syscon"; 150*6ff94537SFabien Parent reg = <0 0x10001000 0 0x1000>; 151*6ff94537SFabien Parent #clock-cells = <1>; 152*6ff94537SFabien Parent }; 153*6ff94537SFabien Parent 154*6ff94537SFabien Parent pericfg: syscon@10003000 { 155*6ff94537SFabien Parent compatible = "mediatek,mt8365-pericfg", "syscon"; 156*6ff94537SFabien Parent reg = <0 0x10003000 0 0x1000>; 157*6ff94537SFabien Parent #clock-cells = <1>; 158*6ff94537SFabien Parent }; 159*6ff94537SFabien Parent 160*6ff94537SFabien Parent syscfg_pctl: syscfg-pctl@10005000 { 161*6ff94537SFabien Parent compatible = "mediatek,mt8365-syscfg", "syscon"; 162*6ff94537SFabien Parent reg = <0 0x10005000 0 0x1000>; 163*6ff94537SFabien Parent }; 164*6ff94537SFabien Parent 165*6ff94537SFabien Parent pio: pinctrl@1000b000 { 166*6ff94537SFabien Parent compatible = "mediatek,mt8365-pinctrl"; 167*6ff94537SFabien Parent reg = <0 0x1000b000 0 0x1000>; 168*6ff94537SFabien Parent mediatek,pctl-regmap = <&syscfg_pctl>; 169*6ff94537SFabien Parent gpio-controller; 170*6ff94537SFabien Parent #gpio-cells = <2>; 171*6ff94537SFabien Parent interrupt-controller; 172*6ff94537SFabien Parent #interrupt-cells = <2>; 173*6ff94537SFabien Parent interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 174*6ff94537SFabien Parent }; 175*6ff94537SFabien Parent 176*6ff94537SFabien Parent apmixedsys: syscon@1000c000 { 177*6ff94537SFabien Parent compatible = "mediatek,mt8365-apmixedsys", "syscon"; 178*6ff94537SFabien Parent reg = <0 0x1000c000 0 0x1000>; 179*6ff94537SFabien Parent #clock-cells = <1>; 180*6ff94537SFabien Parent }; 181*6ff94537SFabien Parent 182*6ff94537SFabien Parent keypad: keypad@10010000 { 183*6ff94537SFabien Parent compatible = "mediatek,mt6779-keypad"; 184*6ff94537SFabien Parent reg = <0 0x10010000 0 0x1000>; 185*6ff94537SFabien Parent wakeup-source; 186*6ff94537SFabien Parent interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 187*6ff94537SFabien Parent clocks = <&clk26m>; 188*6ff94537SFabien Parent clock-names = "kpd"; 189*6ff94537SFabien Parent status = "disabled"; 190*6ff94537SFabien Parent }; 191*6ff94537SFabien Parent 192*6ff94537SFabien Parent mcucfg: syscon@10200000 { 193*6ff94537SFabien Parent compatible = "mediatek,mt8365-mcucfg", "syscon"; 194*6ff94537SFabien Parent reg = <0 0x10200000 0 0x2000>; 195*6ff94537SFabien Parent #clock-cells = <1>; 196*6ff94537SFabien Parent }; 197*6ff94537SFabien Parent 198*6ff94537SFabien Parent sysirq: interrupt-controller@10200a80 { 199*6ff94537SFabien Parent compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 200*6ff94537SFabien Parent interrupt-controller; 201*6ff94537SFabien Parent #interrupt-cells = <3>; 202*6ff94537SFabien Parent interrupt-parent = <&gic>; 203*6ff94537SFabien Parent reg = <0 0x10200a80 0 0x20>; 204*6ff94537SFabien Parent }; 205*6ff94537SFabien Parent 206*6ff94537SFabien Parent infracfg_nao: infracfg@1020e000 { 207*6ff94537SFabien Parent compatible = "mediatek,mt8365-infracfg", "syscon"; 208*6ff94537SFabien Parent reg = <0 0x1020e000 0 0x1000>; 209*6ff94537SFabien Parent #clock-cells = <1>; 210*6ff94537SFabien Parent }; 211*6ff94537SFabien Parent 212*6ff94537SFabien Parent rng: rng@1020f000 { 213*6ff94537SFabien Parent compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 214*6ff94537SFabien Parent reg = <0 0x1020f000 0 0x100>; 215*6ff94537SFabien Parent clocks = <&infracfg CLK_IFR_TRNG>; 216*6ff94537SFabien Parent clock-names = "rng"; 217*6ff94537SFabien Parent }; 218*6ff94537SFabien Parent 219*6ff94537SFabien Parent apdma: dma-controller@11000280 { 220*6ff94537SFabien Parent compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 221*6ff94537SFabien Parent reg = <0 0x11000280 0 0x80>, 222*6ff94537SFabien Parent <0 0x11000300 0 0x80>, 223*6ff94537SFabien Parent <0 0x11000380 0 0x80>, 224*6ff94537SFabien Parent <0 0x11000400 0 0x80>, 225*6ff94537SFabien Parent <0 0x11000580 0 0x80>, 226*6ff94537SFabien Parent <0 0x11000600 0 0x80>; 227*6ff94537SFabien Parent interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 228*6ff94537SFabien Parent <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 229*6ff94537SFabien Parent <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 230*6ff94537SFabien Parent <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 231*6ff94537SFabien Parent <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 232*6ff94537SFabien Parent <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 233*6ff94537SFabien Parent dma-requests = <6>; 234*6ff94537SFabien Parent clocks = <&infracfg CLK_IFR_AP_DMA>; 235*6ff94537SFabien Parent clock-names = "apdma"; 236*6ff94537SFabien Parent #dma-cells = <1>; 237*6ff94537SFabien Parent }; 238*6ff94537SFabien Parent 239*6ff94537SFabien Parent uart0: serial@11002000 { 240*6ff94537SFabien Parent compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 241*6ff94537SFabien Parent reg = <0 0x11002000 0 0x1000>; 242*6ff94537SFabien Parent interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 243*6ff94537SFabien Parent clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 244*6ff94537SFabien Parent clock-names = "baud", "bus"; 245*6ff94537SFabien Parent dmas = <&apdma 0>, <&apdma 1>; 246*6ff94537SFabien Parent dma-names = "tx", "rx"; 247*6ff94537SFabien Parent status = "disabled"; 248*6ff94537SFabien Parent }; 249*6ff94537SFabien Parent 250*6ff94537SFabien Parent uart1: serial@11003000 { 251*6ff94537SFabien Parent compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 252*6ff94537SFabien Parent reg = <0 0x11003000 0 0x1000>; 253*6ff94537SFabien Parent interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 254*6ff94537SFabien Parent clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 255*6ff94537SFabien Parent clock-names = "baud", "bus"; 256*6ff94537SFabien Parent dmas = <&apdma 2>, <&apdma 3>; 257*6ff94537SFabien Parent dma-names = "tx", "rx"; 258*6ff94537SFabien Parent status = "disabled"; 259*6ff94537SFabien Parent }; 260*6ff94537SFabien Parent 261*6ff94537SFabien Parent uart2: serial@11004000 { 262*6ff94537SFabien Parent compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 263*6ff94537SFabien Parent reg = <0 0x11004000 0 0x1000>; 264*6ff94537SFabien Parent interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 265*6ff94537SFabien Parent clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 266*6ff94537SFabien Parent clock-names = "baud", "bus"; 267*6ff94537SFabien Parent dmas = <&apdma 4>, <&apdma 5>; 268*6ff94537SFabien Parent dma-names = "tx", "rx"; 269*6ff94537SFabien Parent status = "disabled"; 270*6ff94537SFabien Parent }; 271*6ff94537SFabien Parent 272*6ff94537SFabien Parent pwm: pwm@11006000 { 273*6ff94537SFabien Parent compatible = "mediatek,mt8365-pwm"; 274*6ff94537SFabien Parent reg = <0 0x11006000 0 0x1000>; 275*6ff94537SFabien Parent #pwm-cells = <2>; 276*6ff94537SFabien Parent interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 277*6ff94537SFabien Parent clocks = <&infracfg CLK_IFR_PWM_HCLK>, 278*6ff94537SFabien Parent <&infracfg CLK_IFR_PWM>, 279*6ff94537SFabien Parent <&infracfg CLK_IFR_PWM1>, 280*6ff94537SFabien Parent <&infracfg CLK_IFR_PWM2>, 281*6ff94537SFabien Parent <&infracfg CLK_IFR_PWM3>; 282*6ff94537SFabien Parent clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 283*6ff94537SFabien Parent }; 284*6ff94537SFabien Parent 285*6ff94537SFabien Parent spi: spi@1100a000 { 286*6ff94537SFabien Parent compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 287*6ff94537SFabien Parent reg = <0 0x1100a000 0 0x100>; 288*6ff94537SFabien Parent #address-cells = <1>; 289*6ff94537SFabien Parent #size-cells = <0>; 290*6ff94537SFabien Parent interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 291*6ff94537SFabien Parent clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 292*6ff94537SFabien Parent <&topckgen CLK_TOP_SPI_SEL>, 293*6ff94537SFabien Parent <&infracfg CLK_IFR_SPI0>; 294*6ff94537SFabien Parent clock-names = "parent-clk", "sel-clk", "spi-clk"; 295*6ff94537SFabien Parent status = "disabled"; 296*6ff94537SFabien Parent }; 297*6ff94537SFabien Parent 298*6ff94537SFabien Parent ssusb: usb@11201000 { 299*6ff94537SFabien Parent compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 300*6ff94537SFabien Parent reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 301*6ff94537SFabien Parent reg-names = "mac", "ippc"; 302*6ff94537SFabien Parent interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 303*6ff94537SFabien Parent phys = <&u2port0 PHY_TYPE_USB2>, 304*6ff94537SFabien Parent <&u2port1 PHY_TYPE_USB2>; 305*6ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 306*6ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_REF>, 307*6ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_SYS>, 308*6ff94537SFabien Parent <&infracfg CLK_IFR_ICUSB>; 309*6ff94537SFabien Parent clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 310*6ff94537SFabien Parent #address-cells = <2>; 311*6ff94537SFabien Parent #size-cells = <2>; 312*6ff94537SFabien Parent ranges; 313*6ff94537SFabien Parent status = "disabled"; 314*6ff94537SFabien Parent 315*6ff94537SFabien Parent usb_host: usb@11200000 { 316*6ff94537SFabien Parent compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 317*6ff94537SFabien Parent reg = <0 0x11200000 0 0x1000>; 318*6ff94537SFabien Parent reg-names = "mac"; 319*6ff94537SFabien Parent interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 320*6ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 321*6ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_REF>, 322*6ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_SYS>, 323*6ff94537SFabien Parent <&infracfg CLK_IFR_ICUSB>, 324*6ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_XHCI>; 325*6ff94537SFabien Parent clock-names = "sys_ck", "ref_ck", "mcu_ck", 326*6ff94537SFabien Parent "dma_ck", "xhci_ck"; 327*6ff94537SFabien Parent status = "disabled"; 328*6ff94537SFabien Parent }; 329*6ff94537SFabien Parent }; 330*6ff94537SFabien Parent 331*6ff94537SFabien Parent u3phy: t-phy@11cc0000 { 332*6ff94537SFabien Parent compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 333*6ff94537SFabien Parent #address-cells = <1>; 334*6ff94537SFabien Parent #size-cells = <1>; 335*6ff94537SFabien Parent ranges = <0 0 0x11cc0000 0x9000>; 336*6ff94537SFabien Parent 337*6ff94537SFabien Parent u2port0: usb-phy@0 { 338*6ff94537SFabien Parent reg = <0x0 0x400>; 339*6ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 340*6ff94537SFabien Parent <&topckgen CLK_TOP_USB20_48M_EN>; 341*6ff94537SFabien Parent clock-names = "ref", "da_ref"; 342*6ff94537SFabien Parent #phy-cells = <1>; 343*6ff94537SFabien Parent }; 344*6ff94537SFabien Parent 345*6ff94537SFabien Parent u2port1: usb-phy@1000 { 346*6ff94537SFabien Parent reg = <0x1000 0x400>; 347*6ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 348*6ff94537SFabien Parent <&topckgen CLK_TOP_USB20_48M_EN>; 349*6ff94537SFabien Parent clock-names = "ref", "da_ref"; 350*6ff94537SFabien Parent #phy-cells = <1>; 351*6ff94537SFabien Parent }; 352*6ff94537SFabien Parent }; 353*6ff94537SFabien Parent }; 354*6ff94537SFabien Parent 355*6ff94537SFabien Parent timer { 356*6ff94537SFabien Parent compatible = "arm,armv8-timer"; 357*6ff94537SFabien Parent interrupt-parent = <&gic>; 358*6ff94537SFabien Parent interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 359*6ff94537SFabien Parent <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 360*6ff94537SFabien Parent <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 361*6ff94537SFabien Parent <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 362*6ff94537SFabien Parent }; 363*6ff94537SFabien Parent 364*6ff94537SFabien Parent system_clk: dummy13m { 365*6ff94537SFabien Parent compatible = "fixed-clock"; 366*6ff94537SFabien Parent clock-frequency = <13000000>; 367*6ff94537SFabien Parent #clock-cells = <0>; 368*6ff94537SFabien Parent }; 369*6ff94537SFabien Parent 370*6ff94537SFabien Parent systimer: timer@10017000 { 371*6ff94537SFabien Parent compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 372*6ff94537SFabien Parent reg = <0 0x10017000 0 0x100>; 373*6ff94537SFabien Parent interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 374*6ff94537SFabien Parent clocks = <&system_clk>; 375*6ff94537SFabien Parent clock-names = "clk13m"; 376*6ff94537SFabien Parent }; 377*6ff94537SFabien Parent}; 378