16ff94537SFabien Parent// SPDX-License-Identifier: (GPL-2.0 OR MIT) 26ff94537SFabien Parent/* 36ff94537SFabien Parent * (C) 2018 MediaTek Inc. 46ff94537SFabien Parent * Copyright (C) 2022 BayLibre SAS 56ff94537SFabien Parent * Fabien Parent <fparent@baylibre.com> 66ff94537SFabien Parent * Bernhard Rosenkränzer <bero@baylibre.com> 76ff94537SFabien Parent */ 86ff94537SFabien Parent#include <dt-bindings/clock/mediatek,mt8365-clk.h> 96ff94537SFabien Parent#include <dt-bindings/interrupt-controller/arm-gic.h> 106ff94537SFabien Parent#include <dt-bindings/interrupt-controller/irq.h> 116ff94537SFabien Parent#include <dt-bindings/phy/phy.h> 126ff94537SFabien Parent 136ff94537SFabien Parent/ { 146ff94537SFabien Parent compatible = "mediatek,mt8365"; 156ff94537SFabien Parent interrupt-parent = <&sysirq>; 166ff94537SFabien Parent #address-cells = <2>; 176ff94537SFabien Parent #size-cells = <2>; 186ff94537SFabien Parent 196ff94537SFabien Parent cpus { 206ff94537SFabien Parent #address-cells = <1>; 216ff94537SFabien Parent #size-cells = <0>; 226ff94537SFabien Parent 23*27205cecSAlexandre Mergnat cluster0_opp: opp-table-0 { 24*27205cecSAlexandre Mergnat compatible = "operating-points-v2"; 25*27205cecSAlexandre Mergnat opp-shared; 26*27205cecSAlexandre Mergnat 27*27205cecSAlexandre Mergnat opp-850000000 { 28*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <850000000>; 29*27205cecSAlexandre Mergnat opp-microvolt = <650000>; 30*27205cecSAlexandre Mergnat }; 31*27205cecSAlexandre Mergnat 32*27205cecSAlexandre Mergnat opp-918000000 { 33*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <918000000>; 34*27205cecSAlexandre Mergnat opp-microvolt = <668750>; 35*27205cecSAlexandre Mergnat }; 36*27205cecSAlexandre Mergnat 37*27205cecSAlexandre Mergnat opp-987000000 { 38*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <987000000>; 39*27205cecSAlexandre Mergnat opp-microvolt = <687500>; 40*27205cecSAlexandre Mergnat }; 41*27205cecSAlexandre Mergnat 42*27205cecSAlexandre Mergnat opp-1056000000 { 43*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1056000000>; 44*27205cecSAlexandre Mergnat opp-microvolt = <706250>; 45*27205cecSAlexandre Mergnat }; 46*27205cecSAlexandre Mergnat 47*27205cecSAlexandre Mergnat opp-1125000000 { 48*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1125000000>; 49*27205cecSAlexandre Mergnat opp-microvolt = <725000>; 50*27205cecSAlexandre Mergnat }; 51*27205cecSAlexandre Mergnat 52*27205cecSAlexandre Mergnat opp-1216000000 { 53*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1216000000>; 54*27205cecSAlexandre Mergnat opp-microvolt = <750000>; 55*27205cecSAlexandre Mergnat }; 56*27205cecSAlexandre Mergnat 57*27205cecSAlexandre Mergnat opp-1308000000 { 58*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1308000000>; 59*27205cecSAlexandre Mergnat opp-microvolt = <775000>; 60*27205cecSAlexandre Mergnat }; 61*27205cecSAlexandre Mergnat 62*27205cecSAlexandre Mergnat opp-1400000000 { 63*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1400000000>; 64*27205cecSAlexandre Mergnat opp-microvolt = <800000>; 65*27205cecSAlexandre Mergnat }; 66*27205cecSAlexandre Mergnat 67*27205cecSAlexandre Mergnat opp-1466000000 { 68*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1466000000>; 69*27205cecSAlexandre Mergnat opp-microvolt = <825000>; 70*27205cecSAlexandre Mergnat }; 71*27205cecSAlexandre Mergnat 72*27205cecSAlexandre Mergnat opp-1533000000 { 73*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1533000000>; 74*27205cecSAlexandre Mergnat opp-microvolt = <850000>; 75*27205cecSAlexandre Mergnat }; 76*27205cecSAlexandre Mergnat 77*27205cecSAlexandre Mergnat opp-1633000000 { 78*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1633000000>; 79*27205cecSAlexandre Mergnat opp-microvolt = <887500>; 80*27205cecSAlexandre Mergnat }; 81*27205cecSAlexandre Mergnat 82*27205cecSAlexandre Mergnat opp-1700000000 { 83*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1700000000>; 84*27205cecSAlexandre Mergnat opp-microvolt = <912500>; 85*27205cecSAlexandre Mergnat }; 86*27205cecSAlexandre Mergnat 87*27205cecSAlexandre Mergnat opp-1767000000 { 88*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1767000000>; 89*27205cecSAlexandre Mergnat opp-microvolt = <937500>; 90*27205cecSAlexandre Mergnat }; 91*27205cecSAlexandre Mergnat 92*27205cecSAlexandre Mergnat opp-1834000000 { 93*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1834000000>; 94*27205cecSAlexandre Mergnat opp-microvolt = <962500>; 95*27205cecSAlexandre Mergnat }; 96*27205cecSAlexandre Mergnat 97*27205cecSAlexandre Mergnat opp-1917000000 { 98*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <1917000000>; 99*27205cecSAlexandre Mergnat opp-microvolt = <993750>; 100*27205cecSAlexandre Mergnat }; 101*27205cecSAlexandre Mergnat 102*27205cecSAlexandre Mergnat opp-2001000000 { 103*27205cecSAlexandre Mergnat opp-hz = /bits/ 64 <2001000000>; 104*27205cecSAlexandre Mergnat opp-microvolt = <1025000>; 105*27205cecSAlexandre Mergnat }; 106*27205cecSAlexandre Mergnat }; 107*27205cecSAlexandre Mergnat 1086ff94537SFabien Parent cpu-map { 1096ff94537SFabien Parent cluster0 { 1106ff94537SFabien Parent core0 { 1116ff94537SFabien Parent cpu = <&cpu0>; 1126ff94537SFabien Parent }; 1136ff94537SFabien Parent core1 { 1146ff94537SFabien Parent cpu = <&cpu1>; 1156ff94537SFabien Parent }; 1166ff94537SFabien Parent core2 { 1176ff94537SFabien Parent cpu = <&cpu2>; 1186ff94537SFabien Parent }; 1196ff94537SFabien Parent core3 { 1206ff94537SFabien Parent cpu = <&cpu3>; 1216ff94537SFabien Parent }; 1226ff94537SFabien Parent }; 1236ff94537SFabien Parent }; 1246ff94537SFabien Parent 1256ff94537SFabien Parent cpu0: cpu@0 { 1266ff94537SFabien Parent device_type = "cpu"; 1276ff94537SFabien Parent compatible = "arm,cortex-a53"; 1286ff94537SFabien Parent reg = <0x0>; 1296ff94537SFabien Parent #cooling-cells = <2>; 1306ff94537SFabien Parent enable-method = "psci"; 1316ff94537SFabien Parent i-cache-size = <0x8000>; 1326ff94537SFabien Parent i-cache-line-size = <64>; 1336ff94537SFabien Parent i-cache-sets = <256>; 1346ff94537SFabien Parent d-cache-size = <0x8000>; 1356ff94537SFabien Parent d-cache-line-size = <64>; 1366ff94537SFabien Parent d-cache-sets = <256>; 1376ff94537SFabien Parent next-level-cache = <&l2>; 138*27205cecSAlexandre Mergnat clocks = <&mcucfg CLK_MCU_BUS_SEL>, 139*27205cecSAlexandre Mergnat <&apmixedsys CLK_APMIXED_MAINPLL>; 140*27205cecSAlexandre Mergnat clock-names = "cpu", "intermediate"; 141*27205cecSAlexandre Mergnat operating-points-v2 = <&cluster0_opp>; 1426ff94537SFabien Parent }; 1436ff94537SFabien Parent 1446ff94537SFabien Parent cpu1: cpu@1 { 1456ff94537SFabien Parent device_type = "cpu"; 1466ff94537SFabien Parent compatible = "arm,cortex-a53"; 1476ff94537SFabien Parent reg = <0x1>; 1486ff94537SFabien Parent #cooling-cells = <2>; 1496ff94537SFabien Parent enable-method = "psci"; 1506ff94537SFabien Parent i-cache-size = <0x8000>; 1516ff94537SFabien Parent i-cache-line-size = <64>; 1526ff94537SFabien Parent i-cache-sets = <256>; 1536ff94537SFabien Parent d-cache-size = <0x8000>; 1546ff94537SFabien Parent d-cache-line-size = <64>; 1556ff94537SFabien Parent d-cache-sets = <256>; 1566ff94537SFabien Parent next-level-cache = <&l2>; 157*27205cecSAlexandre Mergnat clocks = <&mcucfg CLK_MCU_BUS_SEL>, 158*27205cecSAlexandre Mergnat <&apmixedsys CLK_APMIXED_MAINPLL>; 159*27205cecSAlexandre Mergnat clock-names = "cpu", "intermediate", "armpll"; 160*27205cecSAlexandre Mergnat operating-points-v2 = <&cluster0_opp>; 1616ff94537SFabien Parent }; 1626ff94537SFabien Parent 1636ff94537SFabien Parent cpu2: cpu@2 { 1646ff94537SFabien Parent device_type = "cpu"; 1656ff94537SFabien Parent compatible = "arm,cortex-a53"; 1666ff94537SFabien Parent reg = <0x2>; 1676ff94537SFabien Parent #cooling-cells = <2>; 1686ff94537SFabien Parent enable-method = "psci"; 1696ff94537SFabien Parent i-cache-size = <0x8000>; 1706ff94537SFabien Parent i-cache-line-size = <64>; 1716ff94537SFabien Parent i-cache-sets = <256>; 1726ff94537SFabien Parent d-cache-size = <0x8000>; 1736ff94537SFabien Parent d-cache-line-size = <64>; 1746ff94537SFabien Parent d-cache-sets = <256>; 1756ff94537SFabien Parent next-level-cache = <&l2>; 176*27205cecSAlexandre Mergnat clocks = <&mcucfg CLK_MCU_BUS_SEL>, 177*27205cecSAlexandre Mergnat <&apmixedsys CLK_APMIXED_MAINPLL>; 178*27205cecSAlexandre Mergnat clock-names = "cpu", "intermediate", "armpll"; 179*27205cecSAlexandre Mergnat operating-points-v2 = <&cluster0_opp>; 1806ff94537SFabien Parent }; 1816ff94537SFabien Parent 1826ff94537SFabien Parent cpu3: cpu@3 { 1836ff94537SFabien Parent device_type = "cpu"; 1846ff94537SFabien Parent compatible = "arm,cortex-a53"; 1856ff94537SFabien Parent reg = <0x3>; 1866ff94537SFabien Parent #cooling-cells = <2>; 1876ff94537SFabien Parent enable-method = "psci"; 1886ff94537SFabien Parent i-cache-size = <0x8000>; 1896ff94537SFabien Parent i-cache-line-size = <64>; 1906ff94537SFabien Parent i-cache-sets = <256>; 1916ff94537SFabien Parent d-cache-size = <0x8000>; 1926ff94537SFabien Parent d-cache-line-size = <64>; 1936ff94537SFabien Parent d-cache-sets = <256>; 1946ff94537SFabien Parent next-level-cache = <&l2>; 195*27205cecSAlexandre Mergnat clocks = <&mcucfg CLK_MCU_BUS_SEL>, 196*27205cecSAlexandre Mergnat <&apmixedsys CLK_APMIXED_MAINPLL>; 197*27205cecSAlexandre Mergnat clock-names = "cpu", "intermediate", "armpll"; 198*27205cecSAlexandre Mergnat operating-points-v2 = <&cluster0_opp>; 1996ff94537SFabien Parent }; 2006ff94537SFabien Parent 2016ff94537SFabien Parent l2: l2-cache { 2026ff94537SFabien Parent compatible = "cache"; 2036ff94537SFabien Parent cache-level = <2>; 2046ff94537SFabien Parent cache-size = <0x80000>; 2056ff94537SFabien Parent cache-line-size = <64>; 2066ff94537SFabien Parent cache-sets = <512>; 2076ff94537SFabien Parent cache-unified; 2086ff94537SFabien Parent }; 2096ff94537SFabien Parent }; 2106ff94537SFabien Parent 2116ff94537SFabien Parent clk26m: oscillator { 2126ff94537SFabien Parent compatible = "fixed-clock"; 2136ff94537SFabien Parent #clock-cells = <0>; 2146ff94537SFabien Parent clock-frequency = <26000000>; 2156ff94537SFabien Parent clock-output-names = "clk26m"; 2166ff94537SFabien Parent }; 2176ff94537SFabien Parent 2186ff94537SFabien Parent psci { 2196ff94537SFabien Parent compatible = "arm,psci-1.0"; 2206ff94537SFabien Parent method = "smc"; 2216ff94537SFabien Parent }; 2226ff94537SFabien Parent 2236ff94537SFabien Parent soc { 2246ff94537SFabien Parent #address-cells = <2>; 2256ff94537SFabien Parent #size-cells = <2>; 2266ff94537SFabien Parent compatible = "simple-bus"; 2276ff94537SFabien Parent ranges; 2286ff94537SFabien Parent 2296ff94537SFabien Parent gic: interrupt-controller@c000000 { 2306ff94537SFabien Parent compatible = "arm,gic-v3"; 2316ff94537SFabien Parent #interrupt-cells = <3>; 2326ff94537SFabien Parent interrupt-parent = <&gic>; 2336ff94537SFabien Parent interrupt-controller; 2346ff94537SFabien Parent reg = <0 0x0c000000 0 0x10000>, /* GICD */ 2356ff94537SFabien Parent <0 0x0c080000 0 0x80000>, /* GICR */ 2366ff94537SFabien Parent <0 0x0c400000 0 0x2000>, /* GICC */ 2376ff94537SFabien Parent <0 0x0c410000 0 0x1000>, /* GICH */ 2386ff94537SFabien Parent <0 0x0c420000 0 0x2000>; /* GICV */ 2396ff94537SFabien Parent 2406ff94537SFabien Parent interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2416ff94537SFabien Parent }; 2426ff94537SFabien Parent 2436ff94537SFabien Parent topckgen: syscon@10000000 { 2446ff94537SFabien Parent compatible = "mediatek,mt8365-topckgen", "syscon"; 2456ff94537SFabien Parent reg = <0 0x10000000 0 0x1000>; 2466ff94537SFabien Parent #clock-cells = <1>; 2476ff94537SFabien Parent }; 2486ff94537SFabien Parent 2496ff94537SFabien Parent infracfg: syscon@10001000 { 2506ff94537SFabien Parent compatible = "mediatek,mt8365-infracfg", "syscon"; 2516ff94537SFabien Parent reg = <0 0x10001000 0 0x1000>; 2526ff94537SFabien Parent #clock-cells = <1>; 2536ff94537SFabien Parent }; 2546ff94537SFabien Parent 2556ff94537SFabien Parent pericfg: syscon@10003000 { 2566ff94537SFabien Parent compatible = "mediatek,mt8365-pericfg", "syscon"; 2576ff94537SFabien Parent reg = <0 0x10003000 0 0x1000>; 2586ff94537SFabien Parent #clock-cells = <1>; 2596ff94537SFabien Parent }; 2606ff94537SFabien Parent 2616ff94537SFabien Parent syscfg_pctl: syscfg-pctl@10005000 { 2626ff94537SFabien Parent compatible = "mediatek,mt8365-syscfg", "syscon"; 2636ff94537SFabien Parent reg = <0 0x10005000 0 0x1000>; 2646ff94537SFabien Parent }; 2656ff94537SFabien Parent 266751ec3daSAlexandre Mergnat watchdog: watchdog@10007000 { 267751ec3daSAlexandre Mergnat compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 268751ec3daSAlexandre Mergnat reg = <0 0x10007000 0 0x100>; 269751ec3daSAlexandre Mergnat #reset-cells = <1>; 270751ec3daSAlexandre Mergnat }; 271751ec3daSAlexandre Mergnat 2726ff94537SFabien Parent pio: pinctrl@1000b000 { 2736ff94537SFabien Parent compatible = "mediatek,mt8365-pinctrl"; 2746ff94537SFabien Parent reg = <0 0x1000b000 0 0x1000>; 2756ff94537SFabien Parent mediatek,pctl-regmap = <&syscfg_pctl>; 2766ff94537SFabien Parent gpio-controller; 2776ff94537SFabien Parent #gpio-cells = <2>; 2786ff94537SFabien Parent interrupt-controller; 2796ff94537SFabien Parent #interrupt-cells = <2>; 2806ff94537SFabien Parent interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2816ff94537SFabien Parent }; 2826ff94537SFabien Parent 2836ff94537SFabien Parent apmixedsys: syscon@1000c000 { 2846ff94537SFabien Parent compatible = "mediatek,mt8365-apmixedsys", "syscon"; 2856ff94537SFabien Parent reg = <0 0x1000c000 0 0x1000>; 2866ff94537SFabien Parent #clock-cells = <1>; 2876ff94537SFabien Parent }; 2886ff94537SFabien Parent 289a00d1c91SAlexandre Mergnat pwrap: pwrap@1000d000 { 290a00d1c91SAlexandre Mergnat compatible = "mediatek,mt8365-pwrap"; 291a00d1c91SAlexandre Mergnat reg = <0 0x1000d000 0 0x1000>; 292a00d1c91SAlexandre Mergnat reg-names = "pwrap"; 293a00d1c91SAlexandre Mergnat interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 294a00d1c91SAlexandre Mergnat clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 295a00d1c91SAlexandre Mergnat <&infracfg CLK_IFR_PMIC_AP>, 296a00d1c91SAlexandre Mergnat <&infracfg CLK_IFR_PWRAP_SYS>, 297a00d1c91SAlexandre Mergnat <&infracfg CLK_IFR_PWRAP_TMR>; 298a00d1c91SAlexandre Mergnat clock-names = "spi", "wrap", "sys", "tmr"; 299a00d1c91SAlexandre Mergnat }; 300a00d1c91SAlexandre Mergnat 3016ff94537SFabien Parent keypad: keypad@10010000 { 3026ff94537SFabien Parent compatible = "mediatek,mt6779-keypad"; 3036ff94537SFabien Parent reg = <0 0x10010000 0 0x1000>; 3046ff94537SFabien Parent wakeup-source; 3056ff94537SFabien Parent interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 3066ff94537SFabien Parent clocks = <&clk26m>; 3076ff94537SFabien Parent clock-names = "kpd"; 3086ff94537SFabien Parent status = "disabled"; 3096ff94537SFabien Parent }; 3106ff94537SFabien Parent 3116ff94537SFabien Parent mcucfg: syscon@10200000 { 3126ff94537SFabien Parent compatible = "mediatek,mt8365-mcucfg", "syscon"; 3136ff94537SFabien Parent reg = <0 0x10200000 0 0x2000>; 3146ff94537SFabien Parent #clock-cells = <1>; 3156ff94537SFabien Parent }; 3166ff94537SFabien Parent 3176ff94537SFabien Parent sysirq: interrupt-controller@10200a80 { 3186ff94537SFabien Parent compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 3196ff94537SFabien Parent interrupt-controller; 3206ff94537SFabien Parent #interrupt-cells = <3>; 3216ff94537SFabien Parent interrupt-parent = <&gic>; 3226ff94537SFabien Parent reg = <0 0x10200a80 0 0x20>; 3236ff94537SFabien Parent }; 3246ff94537SFabien Parent 3256ff94537SFabien Parent infracfg_nao: infracfg@1020e000 { 3266ff94537SFabien Parent compatible = "mediatek,mt8365-infracfg", "syscon"; 3276ff94537SFabien Parent reg = <0 0x1020e000 0 0x1000>; 3286ff94537SFabien Parent #clock-cells = <1>; 3296ff94537SFabien Parent }; 3306ff94537SFabien Parent 3316ff94537SFabien Parent rng: rng@1020f000 { 3326ff94537SFabien Parent compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 3336ff94537SFabien Parent reg = <0 0x1020f000 0 0x100>; 3346ff94537SFabien Parent clocks = <&infracfg CLK_IFR_TRNG>; 3356ff94537SFabien Parent clock-names = "rng"; 3366ff94537SFabien Parent }; 3376ff94537SFabien Parent 3386ff94537SFabien Parent apdma: dma-controller@11000280 { 3396ff94537SFabien Parent compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 3406ff94537SFabien Parent reg = <0 0x11000280 0 0x80>, 3416ff94537SFabien Parent <0 0x11000300 0 0x80>, 3426ff94537SFabien Parent <0 0x11000380 0 0x80>, 3436ff94537SFabien Parent <0 0x11000400 0 0x80>, 3446ff94537SFabien Parent <0 0x11000580 0 0x80>, 3456ff94537SFabien Parent <0 0x11000600 0 0x80>; 3466ff94537SFabien Parent interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 3476ff94537SFabien Parent <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 3486ff94537SFabien Parent <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 3496ff94537SFabien Parent <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 3506ff94537SFabien Parent <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 3516ff94537SFabien Parent <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 3526ff94537SFabien Parent dma-requests = <6>; 3536ff94537SFabien Parent clocks = <&infracfg CLK_IFR_AP_DMA>; 3546ff94537SFabien Parent clock-names = "apdma"; 3556ff94537SFabien Parent #dma-cells = <1>; 3566ff94537SFabien Parent }; 3576ff94537SFabien Parent 3586ff94537SFabien Parent uart0: serial@11002000 { 3596ff94537SFabien Parent compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 3606ff94537SFabien Parent reg = <0 0x11002000 0 0x1000>; 3616ff94537SFabien Parent interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 3626ff94537SFabien Parent clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 3636ff94537SFabien Parent clock-names = "baud", "bus"; 3646ff94537SFabien Parent dmas = <&apdma 0>, <&apdma 1>; 3656ff94537SFabien Parent dma-names = "tx", "rx"; 3666ff94537SFabien Parent status = "disabled"; 3676ff94537SFabien Parent }; 3686ff94537SFabien Parent 3696ff94537SFabien Parent uart1: serial@11003000 { 3706ff94537SFabien Parent compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 3716ff94537SFabien Parent reg = <0 0x11003000 0 0x1000>; 3726ff94537SFabien Parent interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 3736ff94537SFabien Parent clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 3746ff94537SFabien Parent clock-names = "baud", "bus"; 3756ff94537SFabien Parent dmas = <&apdma 2>, <&apdma 3>; 3766ff94537SFabien Parent dma-names = "tx", "rx"; 3776ff94537SFabien Parent status = "disabled"; 3786ff94537SFabien Parent }; 3796ff94537SFabien Parent 3806ff94537SFabien Parent uart2: serial@11004000 { 3816ff94537SFabien Parent compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 3826ff94537SFabien Parent reg = <0 0x11004000 0 0x1000>; 3836ff94537SFabien Parent interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 3846ff94537SFabien Parent clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 3856ff94537SFabien Parent clock-names = "baud", "bus"; 3866ff94537SFabien Parent dmas = <&apdma 4>, <&apdma 5>; 3876ff94537SFabien Parent dma-names = "tx", "rx"; 3886ff94537SFabien Parent status = "disabled"; 3896ff94537SFabien Parent }; 3906ff94537SFabien Parent 3916ff94537SFabien Parent pwm: pwm@11006000 { 3926ff94537SFabien Parent compatible = "mediatek,mt8365-pwm"; 3936ff94537SFabien Parent reg = <0 0x11006000 0 0x1000>; 3946ff94537SFabien Parent #pwm-cells = <2>; 3956ff94537SFabien Parent interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 3966ff94537SFabien Parent clocks = <&infracfg CLK_IFR_PWM_HCLK>, 3976ff94537SFabien Parent <&infracfg CLK_IFR_PWM>, 3986ff94537SFabien Parent <&infracfg CLK_IFR_PWM1>, 3996ff94537SFabien Parent <&infracfg CLK_IFR_PWM2>, 4006ff94537SFabien Parent <&infracfg CLK_IFR_PWM3>; 4016ff94537SFabien Parent clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 4026ff94537SFabien Parent }; 4036ff94537SFabien Parent 404dbf17e13SAlexandre Mergnat i2c0: i2c@11007000 { 405dbf17e13SAlexandre Mergnat compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 406dbf17e13SAlexandre Mergnat reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 407dbf17e13SAlexandre Mergnat interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 408dbf17e13SAlexandre Mergnat clock-div = <1>; 409dbf17e13SAlexandre Mergnat clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 410dbf17e13SAlexandre Mergnat clock-names = "main", "dma"; 411dbf17e13SAlexandre Mergnat #address-cells = <1>; 412dbf17e13SAlexandre Mergnat #size-cells = <0>; 413dbf17e13SAlexandre Mergnat status = "disabled"; 414dbf17e13SAlexandre Mergnat }; 415dbf17e13SAlexandre Mergnat 416dbf17e13SAlexandre Mergnat i2c1: i2c@11008000 { 417dbf17e13SAlexandre Mergnat compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 418dbf17e13SAlexandre Mergnat reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 419dbf17e13SAlexandre Mergnat interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 420dbf17e13SAlexandre Mergnat clock-div = <1>; 421dbf17e13SAlexandre Mergnat clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 422dbf17e13SAlexandre Mergnat clock-names = "main", "dma"; 423dbf17e13SAlexandre Mergnat #address-cells = <1>; 424dbf17e13SAlexandre Mergnat #size-cells = <0>; 425dbf17e13SAlexandre Mergnat status = "disabled"; 426dbf17e13SAlexandre Mergnat }; 427dbf17e13SAlexandre Mergnat 428dbf17e13SAlexandre Mergnat i2c2: i2c@11009000 { 429dbf17e13SAlexandre Mergnat compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 430dbf17e13SAlexandre Mergnat reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 431dbf17e13SAlexandre Mergnat interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 432dbf17e13SAlexandre Mergnat clock-div = <1>; 433dbf17e13SAlexandre Mergnat clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 434dbf17e13SAlexandre Mergnat clock-names = "main", "dma"; 435dbf17e13SAlexandre Mergnat #address-cells = <1>; 436dbf17e13SAlexandre Mergnat #size-cells = <0>; 437dbf17e13SAlexandre Mergnat status = "disabled"; 438dbf17e13SAlexandre Mergnat }; 439dbf17e13SAlexandre Mergnat 4406ff94537SFabien Parent spi: spi@1100a000 { 4416ff94537SFabien Parent compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 4426ff94537SFabien Parent reg = <0 0x1100a000 0 0x100>; 4436ff94537SFabien Parent #address-cells = <1>; 4446ff94537SFabien Parent #size-cells = <0>; 4456ff94537SFabien Parent interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 4466ff94537SFabien Parent clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 4476ff94537SFabien Parent <&topckgen CLK_TOP_SPI_SEL>, 4486ff94537SFabien Parent <&infracfg CLK_IFR_SPI0>; 4496ff94537SFabien Parent clock-names = "parent-clk", "sel-clk", "spi-clk"; 4506ff94537SFabien Parent status = "disabled"; 4516ff94537SFabien Parent }; 4526ff94537SFabien Parent 453dbf17e13SAlexandre Mergnat i2c3: i2c@1100f000 { 454dbf17e13SAlexandre Mergnat compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 455dbf17e13SAlexandre Mergnat reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 456dbf17e13SAlexandre Mergnat interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 457dbf17e13SAlexandre Mergnat clock-div = <1>; 458dbf17e13SAlexandre Mergnat clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 459dbf17e13SAlexandre Mergnat clock-names = "main", "dma"; 460dbf17e13SAlexandre Mergnat #address-cells = <1>; 461dbf17e13SAlexandre Mergnat #size-cells = <0>; 462dbf17e13SAlexandre Mergnat status = "disabled"; 463dbf17e13SAlexandre Mergnat }; 464dbf17e13SAlexandre Mergnat 4656ff94537SFabien Parent ssusb: usb@11201000 { 4666ff94537SFabien Parent compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 4676ff94537SFabien Parent reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 4686ff94537SFabien Parent reg-names = "mac", "ippc"; 4696ff94537SFabien Parent interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 4706ff94537SFabien Parent phys = <&u2port0 PHY_TYPE_USB2>, 4716ff94537SFabien Parent <&u2port1 PHY_TYPE_USB2>; 4726ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 4736ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_REF>, 4746ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_SYS>, 4756ff94537SFabien Parent <&infracfg CLK_IFR_ICUSB>; 4766ff94537SFabien Parent clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 4776ff94537SFabien Parent #address-cells = <2>; 4786ff94537SFabien Parent #size-cells = <2>; 4796ff94537SFabien Parent ranges; 4806ff94537SFabien Parent status = "disabled"; 4816ff94537SFabien Parent 4826ff94537SFabien Parent usb_host: usb@11200000 { 4836ff94537SFabien Parent compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 4846ff94537SFabien Parent reg = <0 0x11200000 0 0x1000>; 4856ff94537SFabien Parent reg-names = "mac"; 4866ff94537SFabien Parent interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 4876ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 4886ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_REF>, 4896ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_SYS>, 4906ff94537SFabien Parent <&infracfg CLK_IFR_ICUSB>, 4916ff94537SFabien Parent <&infracfg CLK_IFR_SSUSB_XHCI>; 4926ff94537SFabien Parent clock-names = "sys_ck", "ref_ck", "mcu_ck", 4936ff94537SFabien Parent "dma_ck", "xhci_ck"; 4946ff94537SFabien Parent status = "disabled"; 4956ff94537SFabien Parent }; 4966ff94537SFabien Parent }; 4976ff94537SFabien Parent 4988b5db516SAlexandre Mergnat mmc0: mmc@11230000 { 4998b5db516SAlexandre Mergnat compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 5008b5db516SAlexandre Mergnat reg = <0 0x11230000 0 0x1000>, 5018b5db516SAlexandre Mergnat <0 0x11cd0000 0 0x1000>; 5028b5db516SAlexandre Mergnat interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 5038b5db516SAlexandre Mergnat clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 5048b5db516SAlexandre Mergnat <&infracfg CLK_IFR_MSDC0_HCLK>, 5058b5db516SAlexandre Mergnat <&infracfg CLK_IFR_MSDC0_SRC>; 5068b5db516SAlexandre Mergnat clock-names = "source", "hclk", "source_cg"; 5078b5db516SAlexandre Mergnat status = "disabled"; 5088b5db516SAlexandre Mergnat }; 5098b5db516SAlexandre Mergnat 5108b5db516SAlexandre Mergnat mmc1: mmc@11240000 { 5118b5db516SAlexandre Mergnat compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 5128b5db516SAlexandre Mergnat reg = <0 0x11240000 0 0x1000>, 5138b5db516SAlexandre Mergnat <0 0x11c90000 0 0x1000>; 5148b5db516SAlexandre Mergnat interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 5158b5db516SAlexandre Mergnat clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 5168b5db516SAlexandre Mergnat <&infracfg CLK_IFR_MSDC1_HCLK>, 5178b5db516SAlexandre Mergnat <&infracfg CLK_IFR_MSDC1_SRC>; 5188b5db516SAlexandre Mergnat clock-names = "source", "hclk", "source_cg"; 5198b5db516SAlexandre Mergnat status = "disabled"; 5208b5db516SAlexandre Mergnat }; 5218b5db516SAlexandre Mergnat 5228b5db516SAlexandre Mergnat mmc2: mmc@11250000 { 5238b5db516SAlexandre Mergnat compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 5248b5db516SAlexandre Mergnat reg = <0 0x11250000 0 0x1000>, 5258b5db516SAlexandre Mergnat <0 0x11c60000 0 0x1000>; 5268b5db516SAlexandre Mergnat interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 5278b5db516SAlexandre Mergnat clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 5288b5db516SAlexandre Mergnat <&infracfg CLK_IFR_MSDC2_HCLK>, 5298b5db516SAlexandre Mergnat <&infracfg CLK_IFR_MSDC2_SRC>, 5308b5db516SAlexandre Mergnat <&infracfg CLK_IFR_MSDC2_BK>, 5318b5db516SAlexandre Mergnat <&infracfg CLK_IFR_AP_MSDC0>; 5328b5db516SAlexandre Mergnat clock-names = "source", "hclk", "source_cg", 5338b5db516SAlexandre Mergnat "bus_clk", "sys_cg"; 5348b5db516SAlexandre Mergnat status = "disabled"; 5358b5db516SAlexandre Mergnat }; 5368b5db516SAlexandre Mergnat 53791e217d4SAlexandre Mergnat ethernet: ethernet@112a0000 { 53891e217d4SAlexandre Mergnat compatible = "mediatek,mt8365-eth"; 53991e217d4SAlexandre Mergnat reg = <0 0x112a0000 0 0x1000>; 54091e217d4SAlexandre Mergnat mediatek,pericfg = <&infracfg>; 54191e217d4SAlexandre Mergnat interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 54291e217d4SAlexandre Mergnat clocks = <&topckgen CLK_TOP_ETH_SEL>, 54391e217d4SAlexandre Mergnat <&infracfg CLK_IFR_NIC_AXI>, 54491e217d4SAlexandre Mergnat <&infracfg CLK_IFR_NIC_SLV_AXI>; 54591e217d4SAlexandre Mergnat clock-names = "core", "reg", "trans"; 54691e217d4SAlexandre Mergnat status = "disabled"; 54791e217d4SAlexandre Mergnat }; 54891e217d4SAlexandre Mergnat 5496ff94537SFabien Parent u3phy: t-phy@11cc0000 { 5506ff94537SFabien Parent compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 5516ff94537SFabien Parent #address-cells = <1>; 5526ff94537SFabien Parent #size-cells = <1>; 5536ff94537SFabien Parent ranges = <0 0 0x11cc0000 0x9000>; 5546ff94537SFabien Parent 5556ff94537SFabien Parent u2port0: usb-phy@0 { 5566ff94537SFabien Parent reg = <0x0 0x400>; 5576ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 5586ff94537SFabien Parent <&topckgen CLK_TOP_USB20_48M_EN>; 5596ff94537SFabien Parent clock-names = "ref", "da_ref"; 5606ff94537SFabien Parent #phy-cells = <1>; 5616ff94537SFabien Parent }; 5626ff94537SFabien Parent 5636ff94537SFabien Parent u2port1: usb-phy@1000 { 5646ff94537SFabien Parent reg = <0x1000 0x400>; 5656ff94537SFabien Parent clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 5666ff94537SFabien Parent <&topckgen CLK_TOP_USB20_48M_EN>; 5676ff94537SFabien Parent clock-names = "ref", "da_ref"; 5686ff94537SFabien Parent #phy-cells = <1>; 5696ff94537SFabien Parent }; 5706ff94537SFabien Parent }; 5716ff94537SFabien Parent }; 5726ff94537SFabien Parent 5736ff94537SFabien Parent timer { 5746ff94537SFabien Parent compatible = "arm,armv8-timer"; 5756ff94537SFabien Parent interrupt-parent = <&gic>; 5766ff94537SFabien Parent interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5776ff94537SFabien Parent <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5786ff94537SFabien Parent <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5796ff94537SFabien Parent <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5806ff94537SFabien Parent }; 5816ff94537SFabien Parent 5826ff94537SFabien Parent system_clk: dummy13m { 5836ff94537SFabien Parent compatible = "fixed-clock"; 5846ff94537SFabien Parent clock-frequency = <13000000>; 5856ff94537SFabien Parent #clock-cells = <0>; 5866ff94537SFabien Parent }; 5876ff94537SFabien Parent 5886ff94537SFabien Parent systimer: timer@10017000 { 5896ff94537SFabien Parent compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 5906ff94537SFabien Parent reg = <0 0x10017000 0 0x100>; 5916ff94537SFabien Parent interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 5926ff94537SFabien Parent clocks = <&system_clk>; 5936ff94537SFabien Parent clock-names = "clk13m"; 5946ff94537SFabien Parent }; 5956ff94537SFabien Parent}; 596