1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors:
5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
14#include "mt8365.dtsi"
15#include "mt6357.dtsi"
16
17/ {
18	model = "MediaTek MT8365 Open Platform EVK";
19	compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	chosen {
26		stdout-path = "serial0:921600n8";
27	};
28
29	firmware {
30		optee {
31			compatible = "linaro,optee-tz";
32			method = "smc";
33		};
34	};
35
36	gpio-keys {
37		compatible = "gpio-keys";
38		pinctrl-names = "default";
39		pinctrl-0 = <&gpio_keys>;
40
41		key-volume-up {
42			gpios = <&pio 24 GPIO_ACTIVE_LOW>;
43			label = "volume_up";
44			linux,code = <KEY_VOLUMEUP>;
45			wakeup-source;
46			debounce-interval = <15>;
47		};
48	};
49
50	memory@40000000 {
51		device_type = "memory";
52		reg = <0 0x40000000 0 0xc0000000>;
53	};
54
55	usb_otg_vbus: regulator-0 {
56		compatible = "regulator-fixed";
57		regulator-name = "otg_vbus";
58		regulator-min-microvolt = <5000000>;
59		regulator-max-microvolt = <5000000>;
60		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
61		enable-active-high;
62	};
63
64	reserved-memory {
65		#address-cells = <2>;
66		#size-cells = <2>;
67		ranges;
68
69		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
70		bl31_secmon_reserved: secmon@43000000 {
71			no-map;
72			reg = <0 0x43000000 0 0x30000>;
73		};
74
75		/* 12 MiB reserved for OP-TEE (BL32)
76		 * +-----------------------+ 0x43e0_0000
77		 * |      SHMEM 2MiB       |
78		 * +-----------------------+ 0x43c0_0000
79		 * |        | TA_RAM  8MiB |
80		 * + TZDRAM +--------------+ 0x4340_0000
81		 * |        | TEE_RAM 2MiB |
82		 * +-----------------------+ 0x4320_0000
83		 */
84		optee_reserved: optee@43200000 {
85			no-map;
86			reg = <0 0x43200000 0 0x00c00000>;
87		};
88	};
89};
90
91&i2c0 {
92	clock-frequency = <100000>;
93	pinctrl-0 = <&i2c0_pins>;
94	pinctrl-names = "default";
95	status = "okay";
96};
97
98&mt6357_pmic {
99	interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
100	interrupt-controller;
101	#interrupt-cells = <2>;
102};
103
104&pio {
105	gpio_keys: gpio-keys-pins {
106		pins {
107			pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
108			bias-pull-up;
109			input-enable;
110		};
111	};
112
113	i2c0_pins: i2c0-pins {
114		pins {
115			pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
116				 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
117			bias-pull-up;
118		};
119	};
120
121	uart0_pins: uart0-pins {
122		pins {
123			pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
124				 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
125		};
126	};
127
128	uart1_pins: uart1-pins {
129		pins {
130			pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
131				 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
132		};
133	};
134
135	uart2_pins: uart2-pins {
136		pins {
137			pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
138				 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
139		};
140	};
141
142	usb_pins: usb-pins {
143		id-pins {
144			pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
145			input-enable;
146			bias-pull-up;
147		};
148
149		usb0-vbus-pins {
150			pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
151			output-high;
152		};
153
154		usb1-vbus-pins {
155			pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
156			output-high;
157		};
158	};
159
160	pwm_pins: pwm-pins {
161		pins {
162			pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
163				 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
164		};
165	};
166};
167
168&pwm {
169	pinctrl-0 = <&pwm_pins>;
170	pinctrl-names = "default";
171	status = "okay";
172};
173
174&uart0 {
175	pinctrl-0 = <&uart0_pins>;
176	pinctrl-names = "default";
177	status = "okay";
178};
179
180&uart1 {
181	pinctrl-0 = <&uart1_pins>;
182	pinctrl-names = "default";
183	status = "okay";
184};
185
186&uart2 {
187	pinctrl-0 = <&uart2_pins>;
188	pinctrl-names = "default";
189	status = "okay";
190};
191