1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors:
5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
14#include "mt8365.dtsi"
15#include "mt6357.dtsi"
16
17/ {
18	model = "MediaTek MT8365 Open Platform EVK";
19	compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	chosen {
26		stdout-path = "serial0:921600n8";
27	};
28
29	firmware {
30		optee {
31			compatible = "linaro,optee-tz";
32			method = "smc";
33		};
34	};
35
36	gpio-keys {
37		compatible = "gpio-keys";
38		pinctrl-names = "default";
39		pinctrl-0 = <&gpio_keys>;
40
41		key-volume-up {
42			gpios = <&pio 24 GPIO_ACTIVE_LOW>;
43			label = "volume_up";
44			linux,code = <KEY_VOLUMEUP>;
45			wakeup-source;
46			debounce-interval = <15>;
47		};
48	};
49
50	memory@40000000 {
51		device_type = "memory";
52		reg = <0 0x40000000 0 0xc0000000>;
53	};
54
55	usb_otg_vbus: regulator-0 {
56		compatible = "regulator-fixed";
57		regulator-name = "otg_vbus";
58		regulator-min-microvolt = <5000000>;
59		regulator-max-microvolt = <5000000>;
60		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
61		enable-active-high;
62	};
63
64	reserved-memory {
65		#address-cells = <2>;
66		#size-cells = <2>;
67		ranges;
68
69		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
70		bl31_secmon_reserved: secmon@43000000 {
71			no-map;
72			reg = <0 0x43000000 0 0x30000>;
73		};
74
75		/* 12 MiB reserved for OP-TEE (BL32)
76		 * +-----------------------+ 0x43e0_0000
77		 * |      SHMEM 2MiB       |
78		 * +-----------------------+ 0x43c0_0000
79		 * |        | TA_RAM  8MiB |
80		 * + TZDRAM +--------------+ 0x4340_0000
81		 * |        | TEE_RAM 2MiB |
82		 * +-----------------------+ 0x4320_0000
83		 */
84		optee_reserved: optee@43200000 {
85			no-map;
86			reg = <0 0x43200000 0 0x00c00000>;
87		};
88	};
89};
90
91&ethernet {
92	pinctrl-0 = <&ethernet_pins>;
93	pinctrl-names = "default";
94	phy-handle = <&eth_phy>;
95	phy-mode = "rmii";
96	/*
97	 * Ethernet and HDMI (DSI0) are sharing pins.
98	 * Only one can be enabled at a time and require the physical switch
99	 * SW2101 to be set on LAN position
100	 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
101	 */
102	status = "disabled";
103
104	mdio {
105		#address-cells = <1>;
106		#size-cells = <0>;
107
108		eth_phy: ethernet-phy@0 {
109			reg = <0>;
110		};
111	};
112};
113
114&i2c0 {
115	clock-frequency = <100000>;
116	pinctrl-0 = <&i2c0_pins>;
117	pinctrl-names = "default";
118	status = "okay";
119};
120
121&mmc0 {
122	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
123	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
124	bus-width = <8>;
125	cap-mmc-highspeed;
126	cap-mmc-hw-reset;
127	hs400-ds-delay = <0x12012>;
128	max-frequency = <200000000>;
129	mmc-hs200-1_8v;
130	mmc-hs400-1_8v;
131	no-sd;
132	no-sdio;
133	non-removable;
134	pinctrl-0 = <&mmc0_default_pins>;
135	pinctrl-1 = <&mmc0_uhs_pins>;
136	pinctrl-names = "default", "state_uhs";
137	vmmc-supply = <&mt6357_vemc_reg>;
138	vqmmc-supply = <&mt6357_vio18_reg>;
139	status = "okay";
140};
141
142&mmc1 {
143	bus-width = <4>;
144	cap-sd-highspeed;
145	cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
146	max-frequency = <200000000>;
147	pinctrl-0 = <&mmc1_default_pins>;
148	pinctrl-1 = <&mmc1_uhs_pins>;
149	pinctrl-names = "default", "state_uhs";
150	sd-uhs-sdr104;
151	sd-uhs-sdr50;
152	vmmc-supply = <&mt6357_vmch_reg>;
153	vqmmc-supply = <&mt6357_vmc_reg>;
154	status = "okay";
155};
156
157&mt6357_pmic {
158	interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
159	interrupt-controller;
160	#interrupt-cells = <2>;
161};
162
163&pio {
164	ethernet_pins: ethernet-pins {
165		phy_reset_pins {
166			pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
167		};
168
169		rmii_pins {
170			pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
171				 <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
172				 <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
173				 <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
174				 <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
175				 <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
176				 <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
177				 <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
178				 <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
179				 <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
180				 <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
181				 <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
182				 <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
183				 <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
184				 <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
185				 <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
186		};
187	};
188
189	gpio_keys: gpio-keys-pins {
190		pins {
191			pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
192			bias-pull-up;
193			input-enable;
194		};
195	};
196
197	i2c0_pins: i2c0-pins {
198		pins {
199			pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
200				 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
201			bias-pull-up;
202		};
203	};
204
205	mmc0_default_pins: mmc0-default-pins {
206		clk-pins {
207			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
208			bias-pull-down;
209		};
210
211		cmd-dat-pins {
212			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
213				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
214				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
215				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
216				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
217				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
218				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
219				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
220				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
221			input-enable;
222			bias-pull-up;
223		};
224
225		rst-pins {
226			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
227			bias-pull-up;
228		};
229	};
230
231	mmc0_uhs_pins: mmc0-uhs-pins {
232		clk-pins {
233			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
234			drive-strength = <MTK_DRIVE_10mA>;
235			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
236		};
237
238		cmd-dat-pins {
239			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
240				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
241				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
242				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
243				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
244				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
245				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
246				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
247				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
248			input-enable;
249			drive-strength = <MTK_DRIVE_10mA>;
250			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
251		};
252
253		ds-pins {
254			pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
255			drive-strength = <MTK_DRIVE_10mA>;
256			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
257		};
258
259		rst-pins {
260			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
261			drive-strength = <MTK_DRIVE_10mA>;
262			bias-pull-up;
263		};
264	};
265
266	mmc1_default_pins: mmc1-default-pins {
267		cd-pins {
268			pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
269			bias-pull-up;
270		};
271
272		clk-pins {
273			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
274			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
275		};
276
277		cmd-dat-pins {
278			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
279				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
280				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
281				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
282				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
283			input-enable;
284			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
285		};
286	};
287
288	mmc1_uhs_pins: mmc1-uhs-pins {
289		clk-pins {
290			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
291			drive-strength = <MTK_DRIVE_8mA>;
292			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
293		};
294
295		cmd-dat-pins {
296			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
297				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
298				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
299				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
300				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
301			input-enable;
302			drive-strength = <MTK_DRIVE_6mA>;
303			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
304		};
305	};
306
307	uart0_pins: uart0-pins {
308		pins {
309			pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
310				 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
311		};
312	};
313
314	uart1_pins: uart1-pins {
315		pins {
316			pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
317				 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
318		};
319	};
320
321	uart2_pins: uart2-pins {
322		pins {
323			pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
324				 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
325		};
326	};
327
328	usb_pins: usb-pins {
329		id-pins {
330			pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
331			input-enable;
332			bias-pull-up;
333		};
334
335		usb0-vbus-pins {
336			pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
337			output-high;
338		};
339
340		usb1-vbus-pins {
341			pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
342			output-high;
343		};
344	};
345
346	pwm_pins: pwm-pins {
347		pins {
348			pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
349				 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
350		};
351	};
352};
353
354&pwm {
355	pinctrl-0 = <&pwm_pins>;
356	pinctrl-names = "default";
357	status = "okay";
358};
359
360&ssusb {
361	dr_mode = "otg";
362	maximum-speed = "high-speed";
363	pinctrl-0 = <&usb_pins>;
364	pinctrl-names = "default";
365	usb-role-switch;
366	vusb33-supply = <&mt6357_vusb33_reg>;
367	status = "okay";
368
369	connector {
370		compatible = "gpio-usb-b-connector", "usb-b-connector";
371		id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
372		type = "micro";
373		vbus-supply = <&usb_otg_vbus>;
374	};
375};
376
377&usb_host {
378	vusb33-supply = <&mt6357_vusb33_reg>;
379	status = "okay";
380};
381
382&uart0 {
383	pinctrl-0 = <&uart0_pins>;
384	pinctrl-names = "default";
385	status = "okay";
386};
387
388&uart1 {
389	pinctrl-0 = <&uart1_pins>;
390	pinctrl-names = "default";
391	status = "okay";
392};
393
394&uart2 {
395	pinctrl-0 = <&uart2_pins>;
396	pinctrl-names = "default";
397	status = "okay";
398};
399