1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2021-2022 BayLibre, SAS. 4 * Authors: 5 * Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/pinctrl/mt8365-pinfunc.h> 14#include "mt8365.dtsi" 15#include "mt6357.dtsi" 16 17/ { 18 model = "MediaTek MT8365 Open Platform EVK"; 19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; 20 21 aliases { 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:921600n8"; 27 }; 28 29 firmware { 30 optee { 31 compatible = "linaro,optee-tz"; 32 method = "smc"; 33 }; 34 }; 35 36 gpio-keys { 37 compatible = "gpio-keys"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&gpio_keys>; 40 41 key-volume-up { 42 gpios = <&pio 24 GPIO_ACTIVE_LOW>; 43 label = "volume_up"; 44 linux,code = <KEY_VOLUMEUP>; 45 wakeup-source; 46 debounce-interval = <15>; 47 }; 48 }; 49 50 memory@40000000 { 51 device_type = "memory"; 52 reg = <0 0x40000000 0 0xc0000000>; 53 }; 54 55 usb_otg_vbus: regulator-0 { 56 compatible = "regulator-fixed"; 57 regulator-name = "otg_vbus"; 58 regulator-min-microvolt = <5000000>; 59 regulator-max-microvolt = <5000000>; 60 gpio = <&pio 16 GPIO_ACTIVE_HIGH>; 61 enable-active-high; 62 }; 63 64 reserved-memory { 65 #address-cells = <2>; 66 #size-cells = <2>; 67 ranges; 68 69 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 70 bl31_secmon_reserved: secmon@43000000 { 71 no-map; 72 reg = <0 0x43000000 0 0x30000>; 73 }; 74 75 /* 12 MiB reserved for OP-TEE (BL32) 76 * +-----------------------+ 0x43e0_0000 77 * | SHMEM 2MiB | 78 * +-----------------------+ 0x43c0_0000 79 * | | TA_RAM 8MiB | 80 * + TZDRAM +--------------+ 0x4340_0000 81 * | | TEE_RAM 2MiB | 82 * +-----------------------+ 0x4320_0000 83 */ 84 optee_reserved: optee@43200000 { 85 no-map; 86 reg = <0 0x43200000 0 0x00c00000>; 87 }; 88 }; 89}; 90 91&i2c0 { 92 clock-frequency = <100000>; 93 pinctrl-0 = <&i2c0_pins>; 94 pinctrl-names = "default"; 95 status = "okay"; 96}; 97 98&mmc0 { 99 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; 100 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; 101 bus-width = <8>; 102 cap-mmc-highspeed; 103 cap-mmc-hw-reset; 104 hs400-ds-delay = <0x12012>; 105 max-frequency = <200000000>; 106 mmc-hs200-1_8v; 107 mmc-hs400-1_8v; 108 no-sd; 109 no-sdio; 110 non-removable; 111 pinctrl-0 = <&mmc0_default_pins>; 112 pinctrl-1 = <&mmc0_uhs_pins>; 113 pinctrl-names = "default", "state_uhs"; 114 vmmc-supply = <&mt6357_vemc_reg>; 115 vqmmc-supply = <&mt6357_vio18_reg>; 116 status = "okay"; 117}; 118 119&mmc1 { 120 bus-width = <4>; 121 cap-sd-highspeed; 122 cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>; 123 max-frequency = <200000000>; 124 pinctrl-0 = <&mmc1_default_pins>; 125 pinctrl-1 = <&mmc1_uhs_pins>; 126 pinctrl-names = "default", "state_uhs"; 127 sd-uhs-sdr104; 128 sd-uhs-sdr50; 129 vmmc-supply = <&mt6357_vmch_reg>; 130 vqmmc-supply = <&mt6357_vmc_reg>; 131 status = "okay"; 132}; 133 134&mt6357_pmic { 135 interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>; 136 interrupt-controller; 137 #interrupt-cells = <2>; 138}; 139 140&pio { 141 gpio_keys: gpio-keys-pins { 142 pins { 143 pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>; 144 bias-pull-up; 145 input-enable; 146 }; 147 }; 148 149 i2c0_pins: i2c0-pins { 150 pins { 151 pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>, 152 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>; 153 bias-pull-up; 154 }; 155 }; 156 157 mmc0_default_pins: mmc0-default-pins { 158 clk-pins { 159 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>; 160 bias-pull-down; 161 }; 162 163 cmd-dat-pins { 164 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 165 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 166 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>, 167 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>, 168 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>, 169 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>, 170 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>, 171 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>, 172 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>; 173 input-enable; 174 bias-pull-up; 175 }; 176 177 rst-pins { 178 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>; 179 bias-pull-up; 180 }; 181 }; 182 183 mmc0_uhs_pins: mmc0-uhs-pins { 184 clk-pins { 185 pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>; 186 drive-strength = <MTK_DRIVE_10mA>; 187 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 188 }; 189 190 cmd-dat-pins { 191 pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 192 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 193 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>, 194 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>, 195 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>, 196 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>, 197 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>, 198 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>, 199 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>; 200 input-enable; 201 drive-strength = <MTK_DRIVE_10mA>; 202 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 203 }; 204 205 ds-pins { 206 pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>; 207 drive-strength = <MTK_DRIVE_10mA>; 208 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 209 }; 210 211 rst-pins { 212 pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>; 213 drive-strength = <MTK_DRIVE_10mA>; 214 bias-pull-up; 215 }; 216 }; 217 218 mmc1_default_pins: mmc1-default-pins { 219 cd-pins { 220 pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>; 221 bias-pull-up; 222 }; 223 224 clk-pins { 225 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>; 226 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 227 }; 228 229 cmd-dat-pins { 230 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 231 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 232 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>, 233 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>, 234 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>; 235 input-enable; 236 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 237 }; 238 }; 239 240 mmc1_uhs_pins: mmc1-uhs-pins { 241 clk-pins { 242 pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>; 243 drive-strength = <MTK_DRIVE_8mA>; 244 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 245 }; 246 247 cmd-dat-pins { 248 pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 249 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 250 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>, 251 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>, 252 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>; 253 input-enable; 254 drive-strength = <MTK_DRIVE_6mA>; 255 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 256 }; 257 }; 258 259 uart0_pins: uart0-pins { 260 pins { 261 pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>, 262 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>; 263 }; 264 }; 265 266 uart1_pins: uart1-pins { 267 pins { 268 pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>, 269 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>; 270 }; 271 }; 272 273 uart2_pins: uart2-pins { 274 pins { 275 pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>, 276 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>; 277 }; 278 }; 279 280 usb_pins: usb-pins { 281 id-pins { 282 pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>; 283 input-enable; 284 bias-pull-up; 285 }; 286 287 usb0-vbus-pins { 288 pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>; 289 output-high; 290 }; 291 292 usb1-vbus-pins { 293 pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>; 294 output-high; 295 }; 296 }; 297 298 pwm_pins: pwm-pins { 299 pins { 300 pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>, 301 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>; 302 }; 303 }; 304}; 305 306&pwm { 307 pinctrl-0 = <&pwm_pins>; 308 pinctrl-names = "default"; 309 status = "okay"; 310}; 311 312&ssusb { 313 dr_mode = "otg"; 314 maximum-speed = "high-speed"; 315 pinctrl-0 = <&usb_pins>; 316 pinctrl-names = "default"; 317 usb-role-switch; 318 vusb33-supply = <&mt6357_vusb33_reg>; 319 status = "okay"; 320 321 connector { 322 compatible = "gpio-usb-b-connector", "usb-b-connector"; 323 id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>; 324 type = "micro"; 325 vbus-supply = <&usb_otg_vbus>; 326 }; 327}; 328 329&usb_host { 330 vusb33-supply = <&mt6357_vusb33_reg>; 331 status = "okay"; 332}; 333 334&uart0 { 335 pinctrl-0 = <&uart0_pins>; 336 pinctrl-names = "default"; 337 status = "okay"; 338}; 339 340&uart1 { 341 pinctrl-0 = <&uart1_pins>; 342 pinctrl-names = "default"; 343 status = "okay"; 344}; 345 346&uart2 { 347 pinctrl-0 = <&uart2_pins>; 348 pinctrl-names = "default"; 349 status = "okay"; 350}; 351