1*6ff94537SFabien Parent// SPDX-License-Identifier: GPL-2.0 2*6ff94537SFabien Parent/* 3*6ff94537SFabien Parent * Copyright (c) 2021-2022 BayLibre, SAS. 4*6ff94537SFabien Parent * Authors: 5*6ff94537SFabien Parent * Fabien Parent <fparent@baylibre.com> 6*6ff94537SFabien Parent * Bernhard Rosenkränzer <bero@baylibre.com> 7*6ff94537SFabien Parent */ 8*6ff94537SFabien Parent 9*6ff94537SFabien Parent/dts-v1/; 10*6ff94537SFabien Parent 11*6ff94537SFabien Parent#include <dt-bindings/gpio/gpio.h> 12*6ff94537SFabien Parent#include <dt-bindings/input/input.h> 13*6ff94537SFabien Parent#include <dt-bindings/pinctrl/mt8365-pinfunc.h> 14*6ff94537SFabien Parent#include "mt8365.dtsi" 15*6ff94537SFabien Parent 16*6ff94537SFabien Parent/ { 17*6ff94537SFabien Parent model = "MediaTek MT8365 Open Platform EVK"; 18*6ff94537SFabien Parent compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; 19*6ff94537SFabien Parent 20*6ff94537SFabien Parent aliases { 21*6ff94537SFabien Parent serial0 = &uart0; 22*6ff94537SFabien Parent }; 23*6ff94537SFabien Parent 24*6ff94537SFabien Parent chosen { 25*6ff94537SFabien Parent stdout-path = "serial0:921600n8"; 26*6ff94537SFabien Parent }; 27*6ff94537SFabien Parent 28*6ff94537SFabien Parent firmware { 29*6ff94537SFabien Parent optee { 30*6ff94537SFabien Parent compatible = "linaro,optee-tz"; 31*6ff94537SFabien Parent method = "smc"; 32*6ff94537SFabien Parent }; 33*6ff94537SFabien Parent }; 34*6ff94537SFabien Parent 35*6ff94537SFabien Parent gpio-keys { 36*6ff94537SFabien Parent compatible = "gpio-keys"; 37*6ff94537SFabien Parent pinctrl-names = "default"; 38*6ff94537SFabien Parent pinctrl-0 = <&gpio_keys>; 39*6ff94537SFabien Parent 40*6ff94537SFabien Parent key-volume-up { 41*6ff94537SFabien Parent gpios = <&pio 24 GPIO_ACTIVE_LOW>; 42*6ff94537SFabien Parent label = "volume_up"; 43*6ff94537SFabien Parent linux,code = <KEY_VOLUMEUP>; 44*6ff94537SFabien Parent wakeup-source; 45*6ff94537SFabien Parent debounce-interval = <15>; 46*6ff94537SFabien Parent }; 47*6ff94537SFabien Parent }; 48*6ff94537SFabien Parent 49*6ff94537SFabien Parent memory@40000000 { 50*6ff94537SFabien Parent device_type = "memory"; 51*6ff94537SFabien Parent reg = <0 0x40000000 0 0xc0000000>; 52*6ff94537SFabien Parent }; 53*6ff94537SFabien Parent 54*6ff94537SFabien Parent usb_otg_vbus: regulator-0 { 55*6ff94537SFabien Parent compatible = "regulator-fixed"; 56*6ff94537SFabien Parent regulator-name = "otg_vbus"; 57*6ff94537SFabien Parent regulator-min-microvolt = <5000000>; 58*6ff94537SFabien Parent regulator-max-microvolt = <5000000>; 59*6ff94537SFabien Parent gpio = <&pio 16 GPIO_ACTIVE_HIGH>; 60*6ff94537SFabien Parent enable-active-high; 61*6ff94537SFabien Parent }; 62*6ff94537SFabien Parent 63*6ff94537SFabien Parent reserved-memory { 64*6ff94537SFabien Parent #address-cells = <2>; 65*6ff94537SFabien Parent #size-cells = <2>; 66*6ff94537SFabien Parent ranges; 67*6ff94537SFabien Parent 68*6ff94537SFabien Parent /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ 69*6ff94537SFabien Parent bl31_secmon_reserved: secmon@43000000 { 70*6ff94537SFabien Parent no-map; 71*6ff94537SFabien Parent reg = <0 0x43000000 0 0x20000>; 72*6ff94537SFabien Parent }; 73*6ff94537SFabien Parent 74*6ff94537SFabien Parent /* 12 MiB reserved for OP-TEE (BL32) 75*6ff94537SFabien Parent * +-----------------------+ 0x43e0_0000 76*6ff94537SFabien Parent * | SHMEM 2MiB | 77*6ff94537SFabien Parent * +-----------------------+ 0x43c0_0000 78*6ff94537SFabien Parent * | | TA_RAM 8MiB | 79*6ff94537SFabien Parent * + TZDRAM +--------------+ 0x4340_0000 80*6ff94537SFabien Parent * | | TEE_RAM 2MiB | 81*6ff94537SFabien Parent * +-----------------------+ 0x4320_0000 82*6ff94537SFabien Parent */ 83*6ff94537SFabien Parent optee_reserved: optee@43200000 { 84*6ff94537SFabien Parent no-map; 85*6ff94537SFabien Parent reg = <0 0x43200000 0 0x00c00000>; 86*6ff94537SFabien Parent }; 87*6ff94537SFabien Parent }; 88*6ff94537SFabien Parent}; 89*6ff94537SFabien Parent 90*6ff94537SFabien Parent&pio { 91*6ff94537SFabien Parent gpio_keys: gpio-keys-pins { 92*6ff94537SFabien Parent pins { 93*6ff94537SFabien Parent pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>; 94*6ff94537SFabien Parent bias-pull-up; 95*6ff94537SFabien Parent input-enable; 96*6ff94537SFabien Parent }; 97*6ff94537SFabien Parent }; 98*6ff94537SFabien Parent 99*6ff94537SFabien Parent uart0_pins: uart0-pins { 100*6ff94537SFabien Parent pins { 101*6ff94537SFabien Parent pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>, 102*6ff94537SFabien Parent <MT8365_PIN_36_UTXD0__FUNC_UTXD0>; 103*6ff94537SFabien Parent }; 104*6ff94537SFabien Parent }; 105*6ff94537SFabien Parent 106*6ff94537SFabien Parent uart1_pins: uart1-pins { 107*6ff94537SFabien Parent pins { 108*6ff94537SFabien Parent pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>, 109*6ff94537SFabien Parent <MT8365_PIN_38_UTXD1__FUNC_UTXD1>; 110*6ff94537SFabien Parent }; 111*6ff94537SFabien Parent }; 112*6ff94537SFabien Parent 113*6ff94537SFabien Parent uart2_pins: uart2-pins { 114*6ff94537SFabien Parent pins { 115*6ff94537SFabien Parent pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>, 116*6ff94537SFabien Parent <MT8365_PIN_40_UTXD2__FUNC_UTXD2>; 117*6ff94537SFabien Parent }; 118*6ff94537SFabien Parent }; 119*6ff94537SFabien Parent 120*6ff94537SFabien Parent usb_pins: usb-pins { 121*6ff94537SFabien Parent id-pins { 122*6ff94537SFabien Parent pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>; 123*6ff94537SFabien Parent input-enable; 124*6ff94537SFabien Parent bias-pull-up; 125*6ff94537SFabien Parent }; 126*6ff94537SFabien Parent 127*6ff94537SFabien Parent usb0-vbus-pins { 128*6ff94537SFabien Parent pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>; 129*6ff94537SFabien Parent output-high; 130*6ff94537SFabien Parent }; 131*6ff94537SFabien Parent 132*6ff94537SFabien Parent usb1-vbus-pins { 133*6ff94537SFabien Parent pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>; 134*6ff94537SFabien Parent output-high; 135*6ff94537SFabien Parent }; 136*6ff94537SFabien Parent }; 137*6ff94537SFabien Parent 138*6ff94537SFabien Parent pwm_pins: pwm-pins { 139*6ff94537SFabien Parent pins { 140*6ff94537SFabien Parent pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>, 141*6ff94537SFabien Parent <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>; 142*6ff94537SFabien Parent }; 143*6ff94537SFabien Parent }; 144*6ff94537SFabien Parent}; 145*6ff94537SFabien Parent 146*6ff94537SFabien Parent&pwm { 147*6ff94537SFabien Parent pinctrl-0 = <&pwm_pins>; 148*6ff94537SFabien Parent pinctrl-names = "default"; 149*6ff94537SFabien Parent status = "okay"; 150*6ff94537SFabien Parent}; 151*6ff94537SFabien Parent 152*6ff94537SFabien Parent&uart0 { 153*6ff94537SFabien Parent pinctrl-0 = <&uart0_pins>; 154*6ff94537SFabien Parent pinctrl-names = "default"; 155*6ff94537SFabien Parent status = "okay"; 156*6ff94537SFabien Parent}; 157*6ff94537SFabien Parent 158*6ff94537SFabien Parent&uart1 { 159*6ff94537SFabien Parent pinctrl-0 = <&uart1_pins>; 160*6ff94537SFabien Parent pinctrl-names = "default"; 161*6ff94537SFabien Parent status = "okay"; 162*6ff94537SFabien Parent}; 163*6ff94537SFabien Parent 164*6ff94537SFabien Parent&uart2 { 165*6ff94537SFabien Parent pinctrl-0 = <&uart2_pins>; 166*6ff94537SFabien Parent pinctrl-names = "default"; 167*6ff94537SFabien Parent status = "okay"; 168*6ff94537SFabien Parent}; 169