1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 BayLibre, SAS. 4 * Author: Fabien Parent <fparent@baylibre.com> 5 */ 6/dts-v1/; 7 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 14#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> 15 16/ { 17 model = "MediaTek MT8195 demo board"; 18 compatible = "mediatek,mt8195-demo", "mediatek,mt8195"; 19 20 aliases { 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:921600n8"; 26 }; 27 28 firmware { 29 optee { 30 compatible = "linaro,optee-tz"; 31 method = "smc"; 32 }; 33 }; 34 35 gpio-keys { 36 compatible = "gpio-keys"; 37 input-name = "gpio-keys"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&gpio_keys_pins>; 40 41 key-0 { 42 gpios = <&pio 106 GPIO_ACTIVE_LOW>; 43 label = "volume_up"; 44 linux,code = <KEY_VOLUMEUP>; 45 wakeup-source; 46 debounce-interval = <15>; 47 }; 48 }; 49 50 memory@40000000 { 51 device_type = "memory"; 52 reg = <0 0x40000000 0 0x80000000>; 53 }; 54 55 reserved-memory { 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 60 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 61 bl31_secmon_reserved: secmon@54600000 { 62 no-map; 63 reg = <0 0x54600000 0x0 0x30000>; 64 }; 65 66 /* 12 MiB reserved for OP-TEE (BL32) 67 * +-----------------------+ 0x43e0_0000 68 * | SHMEM 2MiB | 69 * +-----------------------+ 0x43c0_0000 70 * | | TA_RAM 8MiB | 71 * + TZDRAM +--------------+ 0x4340_0000 72 * | | TEE_RAM 2MiB | 73 * +-----------------------+ 0x4320_0000 74 */ 75 optee_reserved: optee@43200000 { 76 no-map; 77 reg = <0 0x43200000 0 0x00c00000>; 78 }; 79 }; 80}; 81 82&i2c6 { 83 clock-frequency = <400000>; 84 pinctrl-0 = <&i2c6_pins>; 85 pinctrl-names = "default"; 86 status = "okay"; 87 88 mt6360: pmic@34 { 89 compatible = "mediatek,mt6360"; 90 reg = <0x34>; 91 interrupt-controller; 92 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; 93 interrupt-names = "IRQB"; 94 95 charger { 96 compatible = "mediatek,mt6360-chg"; 97 richtek,vinovp-microvolt = <14500000>; 98 99 otg_vbus_regulator: usb-otg-vbus-regulator { 100 regulator-compatible = "usb-otg-vbus"; 101 regulator-name = "usb-otg-vbus"; 102 regulator-min-microvolt = <4425000>; 103 regulator-max-microvolt = <5825000>; 104 }; 105 }; 106 107 regulator { 108 compatible = "mediatek,mt6360-regulator"; 109 LDO_VIN3-supply = <&mt6360_buck2>; 110 111 mt6360_buck1: buck1 { 112 regulator-compatible = "BUCK1"; 113 regulator-name = "mt6360,buck1"; 114 regulator-min-microvolt = <300000>; 115 regulator-max-microvolt = <1300000>; 116 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 117 MT6360_OPMODE_LP 118 MT6360_OPMODE_ULP>; 119 regulator-always-on; 120 }; 121 122 mt6360_buck2: buck2 { 123 regulator-compatible = "BUCK2"; 124 regulator-name = "mt6360,buck2"; 125 regulator-min-microvolt = <300000>; 126 regulator-max-microvolt = <1300000>; 127 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 128 MT6360_OPMODE_LP 129 MT6360_OPMODE_ULP>; 130 regulator-always-on; 131 }; 132 133 mt6360_ldo1: ldo1 { 134 regulator-compatible = "LDO1"; 135 regulator-name = "mt6360,ldo1"; 136 regulator-min-microvolt = <1200000>; 137 regulator-max-microvolt = <3600000>; 138 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 139 MT6360_OPMODE_LP>; 140 }; 141 142 mt6360_ldo2: ldo2 { 143 regulator-compatible = "LDO2"; 144 regulator-name = "mt6360,ldo2"; 145 regulator-min-microvolt = <1200000>; 146 regulator-max-microvolt = <3600000>; 147 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 148 MT6360_OPMODE_LP>; 149 }; 150 151 mt6360_ldo3: ldo3 { 152 regulator-compatible = "LDO3"; 153 regulator-name = "mt6360,ldo3"; 154 regulator-min-microvolt = <1200000>; 155 regulator-max-microvolt = <3600000>; 156 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 157 MT6360_OPMODE_LP>; 158 }; 159 160 mt6360_ldo5: ldo5 { 161 regulator-compatible = "LDO5"; 162 regulator-name = "mt6360,ldo5"; 163 regulator-min-microvolt = <2700000>; 164 regulator-max-microvolt = <3600000>; 165 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 166 MT6360_OPMODE_LP>; 167 }; 168 169 mt6360_ldo6: ldo6 { 170 regulator-compatible = "LDO6"; 171 regulator-name = "mt6360,ldo6"; 172 regulator-min-microvolt = <500000>; 173 regulator-max-microvolt = <2100000>; 174 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 175 MT6360_OPMODE_LP>; 176 }; 177 178 mt6360_ldo7: ldo7 { 179 regulator-compatible = "LDO7"; 180 regulator-name = "mt6360,ldo7"; 181 regulator-min-microvolt = <500000>; 182 regulator-max-microvolt = <2100000>; 183 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 184 MT6360_OPMODE_LP>; 185 regulator-always-on; 186 }; 187 }; 188 }; 189}; 190 191&mmc0 { 192 status = "okay"; 193 pinctrl-names = "default", "state_uhs"; 194 pinctrl-0 = <&mmc0_default_pins>; 195 pinctrl-1 = <&mmc0_uhs_pins>; 196 bus-width = <8>; 197 max-frequency = <200000000>; 198 cap-mmc-highspeed; 199 mmc-hs200-1_8v; 200 mmc-hs400-1_8v; 201 cap-mmc-hw-reset; 202 no-sdio; 203 no-sd; 204 hs400-ds-delay = <0x14c11>; 205 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 206 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 207 non-removable; 208}; 209 210&mmc1 { 211 pinctrl-names = "default", "state_uhs"; 212 pinctrl-0 = <&mmc1_default_pins>; 213 pinctrl-1 = <&mmc1_uhs_pins>; 214 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; 215 bus-width = <4>; 216 max-frequency = <200000000>; 217 cap-sd-highspeed; 218 sd-uhs-sdr50; 219 sd-uhs-sdr104; 220 vmmc-supply = <&mt6360_ldo5>; 221 vqmmc-supply = <&mt6360_ldo3>; 222 status = "okay"; 223}; 224 225&mt6359_vbbck_ldo_reg { 226 regulator-always-on; 227}; 228 229&mt6359_vcore_buck_reg { 230 regulator-always-on; 231}; 232 233&mt6359_vgpu11_buck_reg { 234 regulator-always-on; 235}; 236 237&mt6359_vproc1_buck_reg { 238 regulator-always-on; 239}; 240 241&mt6359_vproc2_buck_reg { 242 regulator-always-on; 243}; 244 245&mt6359_vpu_buck_reg { 246 regulator-always-on; 247}; 248 249&mt6359_vrf12_ldo_reg { 250 regulator-always-on; 251}; 252 253&mt6359_vsram_md_ldo_reg { 254 regulator-always-on; 255}; 256 257&mt6359_vsram_others_ldo_reg { 258 regulator-always-on; 259}; 260 261&pio { 262 gpio_keys_pins: gpio-keys-pins { 263 pins { 264 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; 265 input-enable; 266 }; 267 }; 268 269 i2c6_pins: i2c6-pins { 270 pins { 271 pinmux = <PINMUX_GPIO25__FUNC_SDA6>, 272 <PINMUX_GPIO26__FUNC_SCL6>; 273 bias-pull-up; 274 }; 275 }; 276 277 mmc0_default_pins: mmc0-default-pins { 278 pins-clk { 279 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 280 drive-strength = <MTK_DRIVE_6mA>; 281 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 282 }; 283 284 pins-cmd-dat { 285 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 286 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 287 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 288 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 289 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 290 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 291 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 292 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 293 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 294 input-enable; 295 drive-strength = <MTK_DRIVE_6mA>; 296 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 297 }; 298 299 pins-rst { 300 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 301 drive-strength = <MTK_DRIVE_6mA>; 302 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 303 }; 304 }; 305 306 mmc0_uhs_pins: mmc0-uhs-pins { 307 pins-clk { 308 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 309 drive-strength = <MTK_DRIVE_8mA>; 310 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 311 }; 312 313 pins-cmd-dat { 314 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 315 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 316 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 317 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 318 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 319 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 320 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 321 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 322 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 323 input-enable; 324 drive-strength = <MTK_DRIVE_8mA>; 325 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 326 }; 327 328 pins-ds { 329 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 330 drive-strength = <MTK_DRIVE_8mA>; 331 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 332 }; 333 334 pins-rst { 335 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 336 drive-strength = <MTK_DRIVE_8mA>; 337 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 338 }; 339 }; 340 341 mmc1_default_pins: mmc1-default-pins { 342 pins-clk { 343 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 344 drive-strength = <MTK_DRIVE_8mA>; 345 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 346 }; 347 348 pins-cmd-dat { 349 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 350 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 351 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 352 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 353 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 354 input-enable; 355 drive-strength = <MTK_DRIVE_8mA>; 356 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 357 }; 358 359 pins-insert { 360 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 361 bias-pull-up; 362 }; 363 }; 364 365 mmc1_uhs_pins: mmc1-uhs-pins { 366 pins-clk { 367 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 368 drive-strength = <MTK_DRIVE_8mA>; 369 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 370 }; 371 372 pins-cmd-dat { 373 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 374 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 375 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 376 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 377 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 378 input-enable; 379 drive-strength = <MTK_DRIVE_8mA>; 380 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 381 }; 382 }; 383 384 uart0_pins: uart0-pins { 385 pins { 386 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, 387 <PINMUX_GPIO99__FUNC_URXD0>; 388 }; 389 }; 390 391 uart1_pins: uart1-pins { 392 pins { 393 pinmux = <PINMUX_GPIO102__FUNC_UTXD1>, 394 <PINMUX_GPIO103__FUNC_URXD1>; 395 }; 396 }; 397}; 398 399 400&pmic { 401 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 402}; 403 404&uart0 { 405 pinctrl-names = "default"; 406 pinctrl-0 = <&uart0_pins>; 407 status = "okay"; 408}; 409 410&u3phy0 { 411 status = "okay"; 412}; 413 414&u3phy1 { 415 status = "okay"; 416}; 417 418&u3phy2 { 419 status = "okay"; 420}; 421 422&u3phy3 { 423 status = "okay"; 424}; 425 426&xhci0 { 427 vusb33-supply = <&mt6359_vusb_ldo_reg>; 428 vbus-supply = <&otg_vbus_regulator>; 429 status = "okay"; 430}; 431 432&xhci1 { 433 vusb33-supply = <&mt6359_vusb_ldo_reg>; 434 status = "okay"; 435}; 436 437&xhci2 { 438 vusb33-supply = <&mt6359_vusb_ldo_reg>; 439 status = "okay"; 440}; 441 442&xhci3 { 443 vusb33-supply = <&mt6359_vusb_ldo_reg>; 444 status = "okay"; 445}; 446