1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include "mt8195.dtsi" 8#include "mt6359.dtsi" 9 10/ { 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 serial0 = &uart0; 21 }; 22 23 chosen { 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 memory@40000000 { 28 device_type = "memory"; 29 reg = <0 0x40000000 0 0x80000000>; 30 }; 31 32 /* system wide LDO 3.3V power rail */ 33 pp3300_z5: regulator-pp3300-ldo-z5 { 34 compatible = "regulator-fixed"; 35 regulator-name = "pp3300_ldo_z5"; 36 regulator-always-on; 37 regulator-boot-on; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 vin-supply = <&ppvar_sys>; 41 }; 42 43 /* separately switched 3.3V power rail */ 44 pp3300_s3: regulator-pp3300-s3 { 45 compatible = "regulator-fixed"; 46 regulator-name = "pp3300_s3"; 47 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 48 regulator-always-on; 49 regulator-boot-on; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 vin-supply = <&pp3300_z2>; 53 }; 54 55 /* system wide 3.3V power rail */ 56 pp3300_z2: regulator-pp3300-z2 { 57 compatible = "regulator-fixed"; 58 regulator-name = "pp3300_z2"; 59 /* EN pin tied to pp4200_z2, which is controlled by EC */ 60 regulator-always-on; 61 regulator-boot-on; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 vin-supply = <&ppvar_sys>; 65 }; 66 67 /* system wide 4.2V power rail */ 68 pp4200_z2: regulator-pp4200-z2 { 69 compatible = "regulator-fixed"; 70 regulator-name = "pp4200_z2"; 71 /* controlled by EC */ 72 regulator-always-on; 73 regulator-boot-on; 74 regulator-min-microvolt = <4200000>; 75 regulator-max-microvolt = <4200000>; 76 vin-supply = <&ppvar_sys>; 77 }; 78 79 /* system wide switching 5.0V power rail */ 80 pp5000_s5: regulator-pp5000-s5 { 81 compatible = "regulator-fixed"; 82 regulator-name = "pp5000_s5"; 83 /* controlled by EC */ 84 regulator-always-on; 85 regulator-boot-on; 86 regulator-min-microvolt = <5000000>; 87 regulator-max-microvolt = <5000000>; 88 vin-supply = <&ppvar_sys>; 89 }; 90 91 /* system wide semi-regulated power rail from battery or USB */ 92 ppvar_sys: regulator-ppvar-sys { 93 compatible = "regulator-fixed"; 94 regulator-name = "ppvar_sys"; 95 regulator-always-on; 96 regulator-boot-on; 97 }; 98 99 usb_vbus: regulator-5v0-usb-vbus { 100 compatible = "regulator-fixed"; 101 regulator-name = "usb-vbus"; 102 regulator-min-microvolt = <5000000>; 103 regulator-max-microvolt = <5000000>; 104 enable-active-high; 105 regulator-always-on; 106 }; 107 108 reserved_memory: reserved-memory { 109 #address-cells = <2>; 110 #size-cells = <2>; 111 ranges; 112 113 scp_mem: memory@50000000 { 114 compatible = "shared-dma-pool"; 115 reg = <0 0x50000000 0 0x2900000>; 116 no-map; 117 }; 118 }; 119}; 120 121&i2c0 { 122 status = "okay"; 123 124 clock-frequency = <400000>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&i2c0_pins>; 127}; 128 129&i2c1 { 130 status = "okay"; 131 132 clock-frequency = <400000>; 133 i2c-scl-internal-delay-ns = <12500>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&i2c1_pins>; 136}; 137 138&i2c2 { 139 status = "okay"; 140 141 clock-frequency = <400000>; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&i2c2_pins>; 144}; 145 146&i2c3 { 147 status = "okay"; 148 149 clock-frequency = <400000>; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&i2c3_pins>; 152}; 153 154&i2c4 { 155 status = "okay"; 156 157 clock-frequency = <400000>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&i2c4_pins>; 160 161 ts_10: touchscreen@10 { 162 compatible = "hid-over-i2c"; 163 reg = <0x10>; 164 hid-descr-addr = <0x0001>; 165 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&touchscreen_pins>; 168 post-power-on-delay-ms = <10>; 169 vdd-supply = <&pp3300_s3>; 170 status = "disabled"; 171 }; 172}; 173 174&i2c5 { 175 status = "okay"; 176 177 clock-frequency = <400000>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&i2c5_pins>; 180}; 181 182&i2c7 { 183 status = "okay"; 184 185 clock-frequency = <400000>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&i2c7_pins>; 188 189 pmic@34 { 190 #interrupt-cells = <1>; 191 compatible = "mediatek,mt6360"; 192 reg = <0x34>; 193 interrupt-controller; 194 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 195 interrupt-names = "IRQB"; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&subpmic_default>; 198 wakeup-source; 199 }; 200}; 201 202&mmc0 { 203 status = "okay"; 204 205 bus-width = <8>; 206 cap-mmc-highspeed; 207 cap-mmc-hw-reset; 208 hs400-ds-delay = <0x14c11>; 209 max-frequency = <200000000>; 210 mmc-hs200-1_8v; 211 mmc-hs400-1_8v; 212 no-sdio; 213 no-sd; 214 non-removable; 215 pinctrl-names = "default", "state_uhs"; 216 pinctrl-0 = <&mmc0_pins_default>; 217 pinctrl-1 = <&mmc0_pins_uhs>; 218 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 219 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 220}; 221 222/* for CPU-L */ 223&mt6359_vcore_buck_reg { 224 regulator-always-on; 225}; 226 227/* for CORE */ 228&mt6359_vgpu11_buck_reg { 229 regulator-always-on; 230}; 231 232&mt6359_vgpu11_sshub_buck_reg { 233 regulator-always-on; 234 regulator-min-microvolt = <550000>; 235 regulator-max-microvolt = <550000>; 236}; 237 238/* for CORE SRAM */ 239&mt6359_vpu_buck_reg { 240 regulator-always-on; 241}; 242 243&mt6359_vrf12_ldo_reg { 244 regulator-always-on; 245}; 246 247/* for GPU SRAM */ 248&mt6359_vsram_others_ldo_reg { 249 regulator-always-on; 250 regulator-min-microvolt = <750000>; 251 regulator-max-microvolt = <750000>; 252}; 253 254&mt6359_vufs_ldo_reg { 255 regulator-always-on; 256}; 257 258&nor_flash { 259 status = "okay"; 260 261 pinctrl-names = "default"; 262 pinctrl-0 = <&nor_pins_default>; 263 264 flash@0 { 265 compatible = "jedec,spi-nor"; 266 reg = <0>; 267 spi-max-frequency = <52000000>; 268 spi-rx-bus-width = <2>; 269 spi-tx-bus-width = <2>; 270 }; 271}; 272 273&pio { 274 mediatek,rsel-resistance-in-si-unit; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pio_default>; 277 278 /* 144 lines */ 279 gpio-line-names = 280 "I2S_SPKR_MCLK", 281 "I2S_SPKR_DATAIN", 282 "I2S_SPKR_LRCK", 283 "I2S_SPKR_BCLK", 284 "EC_AP_INT_ODL", 285 /* 286 * AP_FLASH_WP_L is crossystem ABI. Schematics 287 * call it AP_FLASH_WP_ODL. 288 */ 289 "AP_FLASH_WP_L", 290 "TCHPAD_INT_ODL", 291 "EDP_HPD_1V8", 292 "AP_I2C_CAM_SDA", 293 "AP_I2C_CAM_SCL", 294 "AP_I2C_TCHPAD_SDA_1V8", 295 "AP_I2C_TCHPAD_SCL_1V8", 296 "AP_I2C_AUD_SDA", 297 "AP_I2C_AUD_SCL", 298 "AP_I2C_TPM_SDA_1V8", 299 "AP_I2C_TPM_SCL_1V8", 300 "AP_I2C_TCHSCR_SDA_1V8", 301 "AP_I2C_TCHSCR_SCL_1V8", 302 "EC_AP_HPD_OD", 303 "", 304 "PCIE_NVME_RST_L", 305 "PCIE_NVME_CLKREQ_ODL", 306 "PCIE_RST_1V8_L", 307 "PCIE_CLKREQ_1V8_ODL", 308 "PCIE_WAKE_1V8_ODL", 309 "CLK_24M_CAM0", 310 "CAM1_SEN_EN", 311 "AP_I2C_PWR_SCL_1V8", 312 "AP_I2C_PWR_SDA_1V8", 313 "AP_I2C_MISC_SCL", 314 "AP_I2C_MISC_SDA", 315 "EN_PP5000_HDMI_X", 316 "AP_HDMITX_HTPLG", 317 "", 318 "AP_HDMITX_SCL_1V8", 319 "AP_HDMITX_SDA_1V8", 320 "AP_RTC_CLK32K", 321 "AP_EC_WATCHDOG_L", 322 "SRCLKENA0", 323 "SRCLKENA1", 324 "PWRAP_SPI0_CS_L", 325 "PWRAP_SPI0_CK", 326 "PWRAP_SPI0_MOSI", 327 "PWRAP_SPI0_MISO", 328 "SPMI_SCL", 329 "SPMI_SDA", 330 "", 331 "", 332 "", 333 "I2S_HP_DATAIN", 334 "I2S_HP_MCLK", 335 "I2S_HP_BCK", 336 "I2S_HP_LRCK", 337 "I2S_HP_DATAOUT", 338 "SD_CD_ODL", 339 "EN_PP3300_DISP_X", 340 "TCHSCR_RST_1V8_L", 341 "TCHSCR_REPORT_DISABLE", 342 "EN_PP3300_WLAN_X", 343 "BT_KILL_1V8_L", 344 "I2S_SPKR_DATAOUT", 345 "WIFI_KILL_1V8_L", 346 "BEEP_ON", 347 "SCP_I2C_SENSOR_SCL_1V8", 348 "SCP_I2C_SENSOR_SDA_1V8", 349 "", 350 "", 351 "", 352 "", 353 "AUD_CLK_MOSI", 354 "AUD_SYNC_MOSI", 355 "AUD_DAT_MOSI0", 356 "AUD_DAT_MOSI1", 357 "AUD_DAT_MISO0", 358 "AUD_DAT_MISO1", 359 "AUD_DAT_MISO2", 360 "SCP_VREQ_VAO", 361 "AP_SPI_GSC_TPM_CLK", 362 "AP_SPI_GSC_TPM_MOSI", 363 "AP_SPI_GSC_TPM_CS_L", 364 "AP_SPI_GSC_TPM_MISO", 365 "EN_PP1000_CAM_X", 366 "AP_EDP_BKLTEN", 367 "", 368 "USB3_HUB_RST_L", 369 "", 370 "WLAN_ALERT_ODL", 371 "EC_IN_RW_ODL", 372 "GSC_AP_INT_ODL", 373 "HP_INT_ODL", 374 "CAM0_RST_L", 375 "CAM1_RST_L", 376 "TCHSCR_INT_1V8_L", 377 "CAM1_DET_L", 378 "RST_ALC1011_L", 379 "", 380 "", 381 "BL_PWM_1V8", 382 "UART_AP_TX_DBG_RX", 383 "UART_DBG_TX_AP_RX", 384 "EN_SPKR", 385 "AP_EC_WARM_RST_REQ", 386 "UART_SCP_TX_DBGCON_RX", 387 "UART_DBGCON_TX_SCP_RX", 388 "", 389 "", 390 "KPCOL0", 391 "", 392 "MT6315_GPU_INT", 393 "MT6315_PROC_BC_INT", 394 "SD_CMD", 395 "SD_CLK", 396 "SD_DAT0", 397 "SD_DAT1", 398 "SD_DAT2", 399 "SD_DAT3", 400 "EMMC_DAT7", 401 "EMMC_DAT6", 402 "EMMC_DAT5", 403 "EMMC_DAT4", 404 "EMMC_RSTB", 405 "EMMC_CMD", 406 "EMMC_CLK", 407 "EMMC_DAT3", 408 "EMMC_DAT2", 409 "EMMC_DAT1", 410 "EMMC_DAT0", 411 "EMMC_DSL", 412 "", 413 "", 414 "MT6360_INT_ODL", 415 "SCP_JTAG0_TRSTN", 416 "AP_SPI_EC_CS_L", 417 "AP_SPI_EC_CLK", 418 "AP_SPI_EC_MOSI", 419 "AP_SPI_EC_MISO", 420 "SCP_JTAG0_TMS", 421 "SCP_JTAG0_TCK", 422 "SCP_JTAG0_TDO", 423 "SCP_JTAG0_TDI", 424 "AP_SPI_FLASH_CS_L", 425 "AP_SPI_FLASH_CLK", 426 "AP_SPI_FLASH_MOSI", 427 "AP_SPI_FLASH_MISO"; 428 429 cros_ec_int: cros-ec-irq-default-pins { 430 pins-ec-ap-int-odl { 431 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 432 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 433 input-enable; 434 }; 435 }; 436 437 i2c0_pins: i2c0-default-pins { 438 pins-bus { 439 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 440 <PINMUX_GPIO9__FUNC_SCL0>; 441 bias-disable; 442 drive-strength-microamp = <1000>; 443 }; 444 }; 445 446 i2c1_pins: i2c1-default-pins { 447 pins-bus { 448 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 449 <PINMUX_GPIO11__FUNC_SCL1>; 450 bias-pull-up = <1000>; 451 drive-strength-microamp = <1000>; 452 }; 453 }; 454 455 i2c2_pins: i2c2-default-pins { 456 pins-bus { 457 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 458 <PINMUX_GPIO13__FUNC_SCL2>; 459 bias-disable; 460 drive-strength-microamp = <1000>; 461 }; 462 }; 463 464 i2c3_pins: i2c3-default-pins { 465 pins-bus { 466 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 467 <PINMUX_GPIO15__FUNC_SCL3>; 468 bias-pull-up = <1000>; 469 drive-strength-microamp = <1000>; 470 }; 471 }; 472 473 i2c4_pins: i2c4-default-pins { 474 pins-bus { 475 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 476 <PINMUX_GPIO17__FUNC_SCL4>; 477 bias-pull-up = <1000>; 478 drive-strength = <4>; 479 }; 480 }; 481 482 i2c5_pins: i2c5-default-pins { 483 pins-bus { 484 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 485 <PINMUX_GPIO30__FUNC_SDA5>; 486 bias-disable; 487 drive-strength-microamp = <1000>; 488 }; 489 }; 490 491 i2c7_pins: i2c7-default-pins { 492 pins-bus { 493 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 494 <PINMUX_GPIO28__FUNC_SDA7>; 495 bias-disable; 496 }; 497 }; 498 499 mmc0_pins_default: mmc0-default-pins { 500 pins-cmd-dat { 501 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 502 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 503 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 504 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 505 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 506 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 507 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 508 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 509 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 510 input-enable; 511 drive-strength = <6>; 512 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 513 }; 514 515 pins-clk { 516 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 517 drive-strength = <6>; 518 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 519 }; 520 521 pins-rst { 522 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 523 drive-strength = <6>; 524 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 525 }; 526 }; 527 528 mmc0_pins_uhs: mmc0-uhs-pins { 529 pins-cmd-dat { 530 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 531 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 532 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 533 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 534 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 535 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 536 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 537 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 538 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 539 input-enable; 540 drive-strength = <8>; 541 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 542 }; 543 544 pins-clk { 545 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 546 drive-strength = <8>; 547 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 548 }; 549 550 pins-ds { 551 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 552 drive-strength = <8>; 553 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 554 }; 555 556 pins-rst { 557 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 558 drive-strength = <8>; 559 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 560 }; 561 }; 562 563 nor_pins_default: nor-default-pins { 564 pins-ck-io { 565 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 566 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 567 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 568 drive-strength = <6>; 569 bias-pull-down; 570 }; 571 572 pins-cs { 573 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 574 drive-strength = <6>; 575 bias-pull-up; 576 }; 577 }; 578 579 pio_default: pio-default-pins { 580 pins-wifi-enable { 581 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 582 output-high; 583 drive-strength = <14>; 584 }; 585 586 pins-low-power-pd { 587 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 588 <PINMUX_GPIO26__FUNC_GPIO26>, 589 <PINMUX_GPIO46__FUNC_GPIO46>, 590 <PINMUX_GPIO47__FUNC_GPIO47>, 591 <PINMUX_GPIO48__FUNC_GPIO48>, 592 <PINMUX_GPIO65__FUNC_GPIO65>, 593 <PINMUX_GPIO66__FUNC_GPIO66>, 594 <PINMUX_GPIO67__FUNC_GPIO67>, 595 <PINMUX_GPIO68__FUNC_GPIO68>, 596 <PINMUX_GPIO128__FUNC_GPIO128>, 597 <PINMUX_GPIO129__FUNC_GPIO129>; 598 input-enable; 599 bias-pull-down; 600 }; 601 602 pins-low-power-pupd { 603 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 604 <PINMUX_GPIO78__FUNC_GPIO78>, 605 <PINMUX_GPIO79__FUNC_GPIO79>, 606 <PINMUX_GPIO80__FUNC_GPIO80>, 607 <PINMUX_GPIO83__FUNC_GPIO83>, 608 <PINMUX_GPIO85__FUNC_GPIO85>, 609 <PINMUX_GPIO90__FUNC_GPIO90>, 610 <PINMUX_GPIO91__FUNC_GPIO91>, 611 <PINMUX_GPIO93__FUNC_GPIO93>, 612 <PINMUX_GPIO94__FUNC_GPIO94>, 613 <PINMUX_GPIO95__FUNC_GPIO95>, 614 <PINMUX_GPIO96__FUNC_GPIO96>, 615 <PINMUX_GPIO104__FUNC_GPIO104>, 616 <PINMUX_GPIO105__FUNC_GPIO105>, 617 <PINMUX_GPIO107__FUNC_GPIO107>; 618 input-enable; 619 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 620 }; 621 }; 622 623 scp_pins: scp-default-pins { 624 pins-vreq { 625 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 626 bias-disable; 627 input-enable; 628 }; 629 }; 630 631 spi0_pins: spi0-default-pins { 632 pins-cs-mosi-clk { 633 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 634 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 635 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 636 bias-disable; 637 }; 638 639 pins-miso { 640 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 641 bias-pull-down; 642 }; 643 }; 644 645 subpmic_default: subpmic-default-pins { 646 subpmic_pin_irq: pins-subpmic-int-n { 647 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 648 input-enable; 649 bias-pull-up; 650 }; 651 }; 652 653 touchscreen_pins: touchscreen-default-pins { 654 pins-int-n { 655 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 656 input-enable; 657 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 658 }; 659 pins-rst { 660 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 661 output-high; 662 }; 663 pins-report-sw { 664 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 665 output-low; 666 }; 667 }; 668}; 669 670&pmic { 671 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 672}; 673 674&scp { 675 status = "okay"; 676 677 firmware-name = "mediatek/mt8195/scp.img"; 678 memory-region = <&scp_mem>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&scp_pins>; 681 682 cros-ec-rpmsg { 683 compatible = "google,cros-ec-rpmsg"; 684 mediatek,rpmsg-name = "cros-ec-rpmsg"; 685 }; 686}; 687 688&spi0 { 689 status = "okay"; 690 691 pinctrl-names = "default"; 692 pinctrl-0 = <&spi0_pins>; 693 mediatek,pad-select = <0>; 694 695 cros_ec: ec@0 { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 699 compatible = "google,cros-ec-spi"; 700 reg = <0>; 701 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&cros_ec_int>; 704 spi-max-frequency = <3000000>; 705 706 keyboard-backlight { 707 compatible = "google,cros-kbd-led-backlight"; 708 }; 709 710 i2c_tunnel: i2c-tunnel { 711 compatible = "google,cros-ec-i2c-tunnel"; 712 google,remote-bus = <0>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 }; 716 717 mt_pmic_vmc_ldo_reg: regulator@0 { 718 compatible = "google,cros-ec-regulator"; 719 reg = <0>; 720 regulator-name = "mt_pmic_vmc_ldo"; 721 regulator-min-microvolt = <1200000>; 722 regulator-max-microvolt = <3600000>; 723 }; 724 725 mt_pmic_vmch_ldo_reg: regulator@1 { 726 compatible = "google,cros-ec-regulator"; 727 reg = <1>; 728 regulator-name = "mt_pmic_vmch_ldo"; 729 regulator-min-microvolt = <2700000>; 730 regulator-max-microvolt = <3600000>; 731 }; 732 733 typec { 734 compatible = "google,cros-ec-typec"; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 738 usb_c0: connector@0 { 739 compatible = "usb-c-connector"; 740 reg = <0>; 741 power-role = "dual"; 742 data-role = "host"; 743 try-power-role = "source"; 744 }; 745 746 usb_c1: connector@1 { 747 compatible = "usb-c-connector"; 748 reg = <1>; 749 power-role = "dual"; 750 data-role = "host"; 751 try-power-role = "source"; 752 }; 753 }; 754 }; 755}; 756 757&u3phy0 { 758 status = "okay"; 759}; 760 761&u3phy1 { 762 status = "okay"; 763}; 764 765&u3phy2 { 766 status = "okay"; 767}; 768 769&u3phy3 { 770 status = "okay"; 771}; 772 773&uart0 { 774 status = "okay"; 775}; 776 777&xhci0 { 778 status = "okay"; 779 780 vusb33-supply = <&mt6359_vusb_ldo_reg>; 781 vbus-supply = <&usb_vbus>; 782}; 783 784&xhci1 { 785 status = "okay"; 786 787 vusb33-supply = <&mt6359_vusb_ldo_reg>; 788 vbus-supply = <&usb_vbus>; 789}; 790 791&xhci2 { 792 status = "okay"; 793 794 vusb33-supply = <&mt6359_vusb_ldo_reg>; 795 vbus-supply = <&usb_vbus>; 796}; 797 798&xhci3 { 799 status = "okay"; 800 801 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 802 usb2-lpm-disable; 803 vusb33-supply = <&mt6359_vusb_ldo_reg>; 804 vbus-supply = <&usb_vbus>; 805}; 806 807#include <arm/cros-ec-keyboard.dtsi> 808#include <arm/cros-ec-sbs.dtsi> 809