1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include "mt8195.dtsi" 8#include "mt6359.dtsi" 9 10/ { 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 serial0 = &uart0; 21 }; 22 23 chosen { 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 memory@40000000 { 28 device_type = "memory"; 29 reg = <0 0x40000000 0 0x80000000>; 30 }; 31 32 /* system wide LDO 3.3V power rail */ 33 pp3300_z5: regulator-pp3300-ldo-z5 { 34 compatible = "regulator-fixed"; 35 regulator-name = "pp3300_ldo_z5"; 36 regulator-always-on; 37 regulator-boot-on; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 vin-supply = <&ppvar_sys>; 41 }; 42 43 /* separately switched 3.3V power rail */ 44 pp3300_s3: regulator-pp3300-s3 { 45 compatible = "regulator-fixed"; 46 regulator-name = "pp3300_s3"; 47 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 48 regulator-always-on; 49 regulator-boot-on; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 vin-supply = <&pp3300_z2>; 53 }; 54 55 /* system wide 3.3V power rail */ 56 pp3300_z2: regulator-pp3300-z2 { 57 compatible = "regulator-fixed"; 58 regulator-name = "pp3300_z2"; 59 /* EN pin tied to pp4200_z2, which is controlled by EC */ 60 regulator-always-on; 61 regulator-boot-on; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 vin-supply = <&ppvar_sys>; 65 }; 66 67 /* system wide 4.2V power rail */ 68 pp4200_z2: regulator-pp4200-z2 { 69 compatible = "regulator-fixed"; 70 regulator-name = "pp4200_z2"; 71 /* controlled by EC */ 72 regulator-always-on; 73 regulator-boot-on; 74 regulator-min-microvolt = <4200000>; 75 regulator-max-microvolt = <4200000>; 76 vin-supply = <&ppvar_sys>; 77 }; 78 79 /* system wide switching 5.0V power rail */ 80 pp5000_s5: regulator-pp5000-s5 { 81 compatible = "regulator-fixed"; 82 regulator-name = "pp5000_s5"; 83 /* controlled by EC */ 84 regulator-always-on; 85 regulator-boot-on; 86 regulator-min-microvolt = <5000000>; 87 regulator-max-microvolt = <5000000>; 88 vin-supply = <&ppvar_sys>; 89 }; 90 91 /* system wide semi-regulated power rail from battery or USB */ 92 ppvar_sys: regulator-ppvar-sys { 93 compatible = "regulator-fixed"; 94 regulator-name = "ppvar_sys"; 95 regulator-always-on; 96 regulator-boot-on; 97 }; 98}; 99 100&i2c0 { 101 status = "okay"; 102 103 clock-frequency = <400000>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&i2c0_pins>; 106}; 107 108&i2c1 { 109 status = "okay"; 110 111 clock-frequency = <400000>; 112 i2c-scl-internal-delay-ns = <12500>; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&i2c1_pins>; 115}; 116 117&i2c2 { 118 status = "okay"; 119 120 clock-frequency = <400000>; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&i2c2_pins>; 123}; 124 125&i2c3 { 126 status = "okay"; 127 128 clock-frequency = <400000>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&i2c3_pins>; 131}; 132 133&i2c4 { 134 status = "okay"; 135 136 clock-frequency = <400000>; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&i2c4_pins>; 139}; 140 141&i2c5 { 142 status = "okay"; 143 144 clock-frequency = <400000>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&i2c5_pins>; 147}; 148 149&i2c7 { 150 status = "okay"; 151 152 clock-frequency = <400000>; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&i2c7_pins>; 155}; 156 157&mmc0 { 158 status = "okay"; 159 160 bus-width = <8>; 161 cap-mmc-highspeed; 162 cap-mmc-hw-reset; 163 hs400-ds-delay = <0x14c11>; 164 max-frequency = <200000000>; 165 mmc-hs200-1_8v; 166 mmc-hs400-1_8v; 167 no-sdio; 168 no-sd; 169 non-removable; 170 pinctrl-names = "default", "state_uhs"; 171 pinctrl-0 = <&mmc0_pins_default>; 172 pinctrl-1 = <&mmc0_pins_uhs>; 173 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 174 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 175}; 176 177/* for CPU-L */ 178&mt6359_vcore_buck_reg { 179 regulator-always-on; 180}; 181 182/* for CORE */ 183&mt6359_vgpu11_buck_reg { 184 regulator-always-on; 185}; 186 187&mt6359_vgpu11_sshub_buck_reg { 188 regulator-always-on; 189 regulator-min-microvolt = <550000>; 190 regulator-max-microvolt = <550000>; 191}; 192 193/* for CORE SRAM */ 194&mt6359_vpu_buck_reg { 195 regulator-always-on; 196}; 197 198&mt6359_vrf12_ldo_reg { 199 regulator-always-on; 200}; 201 202/* for GPU SRAM */ 203&mt6359_vsram_others_ldo_reg { 204 regulator-always-on; 205 regulator-min-microvolt = <750000>; 206 regulator-max-microvolt = <750000>; 207}; 208 209&mt6359_vufs_ldo_reg { 210 regulator-always-on; 211}; 212 213&pio { 214 mediatek,rsel-resistance-in-si-unit; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pio_default>; 217 218 /* 144 lines */ 219 gpio-line-names = 220 "I2S_SPKR_MCLK", 221 "I2S_SPKR_DATAIN", 222 "I2S_SPKR_LRCK", 223 "I2S_SPKR_BCLK", 224 "EC_AP_INT_ODL", 225 /* 226 * AP_FLASH_WP_L is crossystem ABI. Schematics 227 * call it AP_FLASH_WP_ODL. 228 */ 229 "AP_FLASH_WP_L", 230 "TCHPAD_INT_ODL", 231 "EDP_HPD_1V8", 232 "AP_I2C_CAM_SDA", 233 "AP_I2C_CAM_SCL", 234 "AP_I2C_TCHPAD_SDA_1V8", 235 "AP_I2C_TCHPAD_SCL_1V8", 236 "AP_I2C_AUD_SDA", 237 "AP_I2C_AUD_SCL", 238 "AP_I2C_TPM_SDA_1V8", 239 "AP_I2C_TPM_SCL_1V8", 240 "AP_I2C_TCHSCR_SDA_1V8", 241 "AP_I2C_TCHSCR_SCL_1V8", 242 "EC_AP_HPD_OD", 243 "", 244 "PCIE_NVME_RST_L", 245 "PCIE_NVME_CLKREQ_ODL", 246 "PCIE_RST_1V8_L", 247 "PCIE_CLKREQ_1V8_ODL", 248 "PCIE_WAKE_1V8_ODL", 249 "CLK_24M_CAM0", 250 "CAM1_SEN_EN", 251 "AP_I2C_PWR_SCL_1V8", 252 "AP_I2C_PWR_SDA_1V8", 253 "AP_I2C_MISC_SCL", 254 "AP_I2C_MISC_SDA", 255 "EN_PP5000_HDMI_X", 256 "AP_HDMITX_HTPLG", 257 "", 258 "AP_HDMITX_SCL_1V8", 259 "AP_HDMITX_SDA_1V8", 260 "AP_RTC_CLK32K", 261 "AP_EC_WATCHDOG_L", 262 "SRCLKENA0", 263 "SRCLKENA1", 264 "PWRAP_SPI0_CS_L", 265 "PWRAP_SPI0_CK", 266 "PWRAP_SPI0_MOSI", 267 "PWRAP_SPI0_MISO", 268 "SPMI_SCL", 269 "SPMI_SDA", 270 "", 271 "", 272 "", 273 "I2S_HP_DATAIN", 274 "I2S_HP_MCLK", 275 "I2S_HP_BCK", 276 "I2S_HP_LRCK", 277 "I2S_HP_DATAOUT", 278 "SD_CD_ODL", 279 "EN_PP3300_DISP_X", 280 "TCHSCR_RST_1V8_L", 281 "TCHSCR_REPORT_DISABLE", 282 "EN_PP3300_WLAN_X", 283 "BT_KILL_1V8_L", 284 "I2S_SPKR_DATAOUT", 285 "WIFI_KILL_1V8_L", 286 "BEEP_ON", 287 "SCP_I2C_SENSOR_SCL_1V8", 288 "SCP_I2C_SENSOR_SDA_1V8", 289 "", 290 "", 291 "", 292 "", 293 "AUD_CLK_MOSI", 294 "AUD_SYNC_MOSI", 295 "AUD_DAT_MOSI0", 296 "AUD_DAT_MOSI1", 297 "AUD_DAT_MISO0", 298 "AUD_DAT_MISO1", 299 "AUD_DAT_MISO2", 300 "SCP_VREQ_VAO", 301 "AP_SPI_GSC_TPM_CLK", 302 "AP_SPI_GSC_TPM_MOSI", 303 "AP_SPI_GSC_TPM_CS_L", 304 "AP_SPI_GSC_TPM_MISO", 305 "EN_PP1000_CAM_X", 306 "AP_EDP_BKLTEN", 307 "", 308 "USB3_HUB_RST_L", 309 "", 310 "WLAN_ALERT_ODL", 311 "EC_IN_RW_ODL", 312 "GSC_AP_INT_ODL", 313 "HP_INT_ODL", 314 "CAM0_RST_L", 315 "CAM1_RST_L", 316 "TCHSCR_INT_1V8_L", 317 "CAM1_DET_L", 318 "RST_ALC1011_L", 319 "", 320 "", 321 "BL_PWM_1V8", 322 "UART_AP_TX_DBG_RX", 323 "UART_DBG_TX_AP_RX", 324 "EN_SPKR", 325 "AP_EC_WARM_RST_REQ", 326 "UART_SCP_TX_DBGCON_RX", 327 "UART_DBGCON_TX_SCP_RX", 328 "", 329 "", 330 "KPCOL0", 331 "", 332 "MT6315_GPU_INT", 333 "MT6315_PROC_BC_INT", 334 "SD_CMD", 335 "SD_CLK", 336 "SD_DAT0", 337 "SD_DAT1", 338 "SD_DAT2", 339 "SD_DAT3", 340 "EMMC_DAT7", 341 "EMMC_DAT6", 342 "EMMC_DAT5", 343 "EMMC_DAT4", 344 "EMMC_RSTB", 345 "EMMC_CMD", 346 "EMMC_CLK", 347 "EMMC_DAT3", 348 "EMMC_DAT2", 349 "EMMC_DAT1", 350 "EMMC_DAT0", 351 "EMMC_DSL", 352 "", 353 "", 354 "MT6360_INT_ODL", 355 "SCP_JTAG0_TRSTN", 356 "AP_SPI_EC_CS_L", 357 "AP_SPI_EC_CLK", 358 "AP_SPI_EC_MOSI", 359 "AP_SPI_EC_MISO", 360 "SCP_JTAG0_TMS", 361 "SCP_JTAG0_TCK", 362 "SCP_JTAG0_TDO", 363 "SCP_JTAG0_TDI", 364 "AP_SPI_FLASH_CS_L", 365 "AP_SPI_FLASH_CLK", 366 "AP_SPI_FLASH_MOSI", 367 "AP_SPI_FLASH_MISO"; 368 369 i2c0_pins: i2c0-default-pins { 370 pins-bus { 371 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 372 <PINMUX_GPIO9__FUNC_SCL0>; 373 bias-disable; 374 drive-strength-microamp = <1000>; 375 }; 376 }; 377 378 i2c1_pins: i2c1-default-pins { 379 pins-bus { 380 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 381 <PINMUX_GPIO11__FUNC_SCL1>; 382 bias-pull-up = <1000>; 383 drive-strength-microamp = <1000>; 384 }; 385 }; 386 387 i2c2_pins: i2c2-default-pins { 388 pins-bus { 389 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 390 <PINMUX_GPIO13__FUNC_SCL2>; 391 bias-disable; 392 drive-strength-microamp = <1000>; 393 }; 394 }; 395 396 i2c3_pins: i2c3-default-pins { 397 pins-bus { 398 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 399 <PINMUX_GPIO15__FUNC_SCL3>; 400 bias-pull-up = <1000>; 401 drive-strength-microamp = <1000>; 402 }; 403 }; 404 405 i2c4_pins: i2c4-default-pins { 406 pins-bus { 407 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 408 <PINMUX_GPIO17__FUNC_SCL4>; 409 bias-pull-up = <1000>; 410 drive-strength = <4>; 411 }; 412 }; 413 414 i2c5_pins: i2c5-default-pins { 415 pins-bus { 416 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 417 <PINMUX_GPIO30__FUNC_SDA5>; 418 bias-disable; 419 drive-strength-microamp = <1000>; 420 }; 421 }; 422 423 i2c7_pins: i2c7-default-pins { 424 pins-bus { 425 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 426 <PINMUX_GPIO28__FUNC_SDA7>; 427 bias-disable; 428 }; 429 }; 430 431 mmc0_pins_default: mmc0-default-pins { 432 pins-cmd-dat { 433 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 434 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 435 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 436 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 437 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 438 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 439 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 440 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 441 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 442 input-enable; 443 drive-strength = <6>; 444 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 445 }; 446 447 pins-clk { 448 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 449 drive-strength = <6>; 450 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 451 }; 452 453 pins-rst { 454 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 455 drive-strength = <6>; 456 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 457 }; 458 }; 459 460 mmc0_pins_uhs: mmc0-uhs-pins { 461 pins-cmd-dat { 462 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 463 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 464 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 465 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 466 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 467 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 468 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 469 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 470 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 471 input-enable; 472 drive-strength = <8>; 473 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 474 }; 475 476 pins-clk { 477 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 478 drive-strength = <8>; 479 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 480 }; 481 482 pins-ds { 483 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 484 drive-strength = <8>; 485 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 486 }; 487 488 pins-rst { 489 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 490 drive-strength = <8>; 491 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 492 }; 493 }; 494 495 pio_default: pio-default-pins { 496 pins-wifi-enable { 497 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 498 output-high; 499 drive-strength = <14>; 500 }; 501 502 pins-low-power-pd { 503 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 504 <PINMUX_GPIO26__FUNC_GPIO26>, 505 <PINMUX_GPIO46__FUNC_GPIO46>, 506 <PINMUX_GPIO47__FUNC_GPIO47>, 507 <PINMUX_GPIO48__FUNC_GPIO48>, 508 <PINMUX_GPIO65__FUNC_GPIO65>, 509 <PINMUX_GPIO66__FUNC_GPIO66>, 510 <PINMUX_GPIO67__FUNC_GPIO67>, 511 <PINMUX_GPIO68__FUNC_GPIO68>, 512 <PINMUX_GPIO128__FUNC_GPIO128>, 513 <PINMUX_GPIO129__FUNC_GPIO129>; 514 input-enable; 515 bias-pull-down; 516 }; 517 518 pins-low-power-pupd { 519 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 520 <PINMUX_GPIO78__FUNC_GPIO78>, 521 <PINMUX_GPIO79__FUNC_GPIO79>, 522 <PINMUX_GPIO80__FUNC_GPIO80>, 523 <PINMUX_GPIO83__FUNC_GPIO83>, 524 <PINMUX_GPIO85__FUNC_GPIO85>, 525 <PINMUX_GPIO90__FUNC_GPIO90>, 526 <PINMUX_GPIO91__FUNC_GPIO91>, 527 <PINMUX_GPIO93__FUNC_GPIO93>, 528 <PINMUX_GPIO94__FUNC_GPIO94>, 529 <PINMUX_GPIO95__FUNC_GPIO95>, 530 <PINMUX_GPIO96__FUNC_GPIO96>, 531 <PINMUX_GPIO104__FUNC_GPIO104>, 532 <PINMUX_GPIO105__FUNC_GPIO105>, 533 <PINMUX_GPIO107__FUNC_GPIO107>; 534 input-enable; 535 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 536 }; 537 }; 538 539 spi0_pins: spi0-default-pins { 540 pins-cs-mosi-clk { 541 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 542 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 543 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 544 bias-disable; 545 }; 546 547 pins-miso { 548 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 549 bias-pull-down; 550 }; 551 }; 552}; 553 554&pmic { 555 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 556}; 557 558&spi0 { 559 status = "okay"; 560 561 pinctrl-names = "default"; 562 pinctrl-0 = <&spi0_pins>; 563 mediatek,pad-select = <0>; 564}; 565 566&uart0 { 567 status = "okay"; 568}; 569