1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include "mt8195.dtsi"
8#include "mt6359.dtsi"
9
10/ {
11	aliases {
12		i2c0 = &i2c0;
13		i2c1 = &i2c1;
14		i2c2 = &i2c2;
15		i2c3 = &i2c3;
16		i2c4 = &i2c4;
17		i2c5 = &i2c5;
18		i2c7 = &i2c7;
19		mmc0 = &mmc0;
20		serial0 = &uart0;
21	};
22
23	chosen {
24		stdout-path = "serial0:115200n8";
25	};
26
27	memory@40000000 {
28		device_type = "memory";
29		reg = <0 0x40000000 0 0x80000000>;
30	};
31
32	/* system wide LDO 3.3V power rail */
33	pp3300_z5: regulator-pp3300-ldo-z5 {
34		compatible = "regulator-fixed";
35		regulator-name = "pp3300_ldo_z5";
36		regulator-always-on;
37		regulator-boot-on;
38		regulator-min-microvolt = <3300000>;
39		regulator-max-microvolt = <3300000>;
40		vin-supply = <&ppvar_sys>;
41	};
42
43	/* separately switched 3.3V power rail */
44	pp3300_s3: regulator-pp3300-s3 {
45		compatible = "regulator-fixed";
46		regulator-name = "pp3300_s3";
47		/* automatically sequenced by PMIC EXT_PMIC_EN2 */
48		regulator-always-on;
49		regulator-boot-on;
50		regulator-min-microvolt = <3300000>;
51		regulator-max-microvolt = <3300000>;
52		vin-supply = <&pp3300_z2>;
53	};
54
55	/* system wide 3.3V power rail */
56	pp3300_z2: regulator-pp3300-z2 {
57		compatible = "regulator-fixed";
58		regulator-name = "pp3300_z2";
59		/* EN pin tied to pp4200_z2, which is controlled by EC */
60		regulator-always-on;
61		regulator-boot-on;
62		regulator-min-microvolt = <3300000>;
63		regulator-max-microvolt = <3300000>;
64		vin-supply = <&ppvar_sys>;
65	};
66
67	/* system wide 4.2V power rail */
68	pp4200_z2: regulator-pp4200-z2 {
69		compatible = "regulator-fixed";
70		regulator-name = "pp4200_z2";
71		/* controlled by EC */
72		regulator-always-on;
73		regulator-boot-on;
74		regulator-min-microvolt = <4200000>;
75		regulator-max-microvolt = <4200000>;
76		vin-supply = <&ppvar_sys>;
77	};
78
79	/* system wide switching 5.0V power rail */
80	pp5000_s5: regulator-pp5000-s5 {
81		compatible = "regulator-fixed";
82		regulator-name = "pp5000_s5";
83		/* controlled by EC */
84		regulator-always-on;
85		regulator-boot-on;
86		regulator-min-microvolt = <5000000>;
87		regulator-max-microvolt = <5000000>;
88		vin-supply = <&ppvar_sys>;
89	};
90
91	/* system wide semi-regulated power rail from battery or USB */
92	ppvar_sys: regulator-ppvar-sys {
93		compatible = "regulator-fixed";
94		regulator-name = "ppvar_sys";
95		regulator-always-on;
96		regulator-boot-on;
97	};
98
99	usb_vbus: regulator-5v0-usb-vbus {
100		compatible = "regulator-fixed";
101		regulator-name = "usb-vbus";
102		regulator-min-microvolt = <5000000>;
103		regulator-max-microvolt = <5000000>;
104		enable-active-high;
105		regulator-always-on;
106	};
107};
108
109&i2c0 {
110	status = "okay";
111
112	clock-frequency = <400000>;
113	pinctrl-names = "default";
114	pinctrl-0 = <&i2c0_pins>;
115};
116
117&i2c1 {
118	status = "okay";
119
120	clock-frequency = <400000>;
121	i2c-scl-internal-delay-ns = <12500>;
122	pinctrl-names = "default";
123	pinctrl-0 = <&i2c1_pins>;
124};
125
126&i2c2 {
127	status = "okay";
128
129	clock-frequency = <400000>;
130	pinctrl-names = "default";
131	pinctrl-0 = <&i2c2_pins>;
132};
133
134&i2c3 {
135	status = "okay";
136
137	clock-frequency = <400000>;
138	pinctrl-names = "default";
139	pinctrl-0 = <&i2c3_pins>;
140};
141
142&i2c4 {
143	status = "okay";
144
145	clock-frequency = <400000>;
146	pinctrl-names = "default";
147	pinctrl-0 = <&i2c4_pins>;
148};
149
150&i2c5 {
151	status = "okay";
152
153	clock-frequency = <400000>;
154	pinctrl-names = "default";
155	pinctrl-0 = <&i2c5_pins>;
156};
157
158&i2c7 {
159	status = "okay";
160
161	clock-frequency = <400000>;
162	pinctrl-names = "default";
163	pinctrl-0 = <&i2c7_pins>;
164
165	pmic@34 {
166		#interrupt-cells = <1>;
167		compatible = "mediatek,mt6360";
168		reg = <0x34>;
169		interrupt-controller;
170		interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>;
171		interrupt-names = "IRQB";
172		pinctrl-names = "default";
173		pinctrl-0 = <&subpmic_default>;
174		wakeup-source;
175	};
176};
177
178&mmc0 {
179	status = "okay";
180
181	bus-width = <8>;
182	cap-mmc-highspeed;
183	cap-mmc-hw-reset;
184	hs400-ds-delay = <0x14c11>;
185	max-frequency = <200000000>;
186	mmc-hs200-1_8v;
187	mmc-hs400-1_8v;
188	no-sdio;
189	no-sd;
190	non-removable;
191	pinctrl-names = "default", "state_uhs";
192	pinctrl-0 = <&mmc0_pins_default>;
193	pinctrl-1 = <&mmc0_pins_uhs>;
194	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
195	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
196};
197
198/* for CPU-L */
199&mt6359_vcore_buck_reg {
200	regulator-always-on;
201};
202
203/* for CORE */
204&mt6359_vgpu11_buck_reg {
205	regulator-always-on;
206};
207
208&mt6359_vgpu11_sshub_buck_reg {
209	regulator-always-on;
210	regulator-min-microvolt = <550000>;
211	regulator-max-microvolt = <550000>;
212};
213
214/* for CORE SRAM */
215&mt6359_vpu_buck_reg {
216	regulator-always-on;
217};
218
219&mt6359_vrf12_ldo_reg {
220	regulator-always-on;
221};
222
223/* for GPU SRAM */
224&mt6359_vsram_others_ldo_reg {
225	regulator-always-on;
226	regulator-min-microvolt = <750000>;
227	regulator-max-microvolt = <750000>;
228};
229
230&mt6359_vufs_ldo_reg {
231	regulator-always-on;
232};
233
234&nor_flash {
235	status = "okay";
236
237	pinctrl-names = "default";
238	pinctrl-0 = <&nor_pins_default>;
239
240	flash@0 {
241		compatible = "jedec,spi-nor";
242		reg = <0>;
243		spi-max-frequency = <52000000>;
244		spi-rx-bus-width = <2>;
245		spi-tx-bus-width = <2>;
246	};
247};
248
249&pio {
250	mediatek,rsel-resistance-in-si-unit;
251	pinctrl-names = "default";
252	pinctrl-0 = <&pio_default>;
253
254	/* 144 lines */
255	gpio-line-names =
256		"I2S_SPKR_MCLK",
257		"I2S_SPKR_DATAIN",
258		"I2S_SPKR_LRCK",
259		"I2S_SPKR_BCLK",
260		"EC_AP_INT_ODL",
261		/*
262		 * AP_FLASH_WP_L is crossystem ABI. Schematics
263		 * call it AP_FLASH_WP_ODL.
264		 */
265		"AP_FLASH_WP_L",
266		"TCHPAD_INT_ODL",
267		"EDP_HPD_1V8",
268		"AP_I2C_CAM_SDA",
269		"AP_I2C_CAM_SCL",
270		"AP_I2C_TCHPAD_SDA_1V8",
271		"AP_I2C_TCHPAD_SCL_1V8",
272		"AP_I2C_AUD_SDA",
273		"AP_I2C_AUD_SCL",
274		"AP_I2C_TPM_SDA_1V8",
275		"AP_I2C_TPM_SCL_1V8",
276		"AP_I2C_TCHSCR_SDA_1V8",
277		"AP_I2C_TCHSCR_SCL_1V8",
278		"EC_AP_HPD_OD",
279		"",
280		"PCIE_NVME_RST_L",
281		"PCIE_NVME_CLKREQ_ODL",
282		"PCIE_RST_1V8_L",
283		"PCIE_CLKREQ_1V8_ODL",
284		"PCIE_WAKE_1V8_ODL",
285		"CLK_24M_CAM0",
286		"CAM1_SEN_EN",
287		"AP_I2C_PWR_SCL_1V8",
288		"AP_I2C_PWR_SDA_1V8",
289		"AP_I2C_MISC_SCL",
290		"AP_I2C_MISC_SDA",
291		"EN_PP5000_HDMI_X",
292		"AP_HDMITX_HTPLG",
293		"",
294		"AP_HDMITX_SCL_1V8",
295		"AP_HDMITX_SDA_1V8",
296		"AP_RTC_CLK32K",
297		"AP_EC_WATCHDOG_L",
298		"SRCLKENA0",
299		"SRCLKENA1",
300		"PWRAP_SPI0_CS_L",
301		"PWRAP_SPI0_CK",
302		"PWRAP_SPI0_MOSI",
303		"PWRAP_SPI0_MISO",
304		"SPMI_SCL",
305		"SPMI_SDA",
306		"",
307		"",
308		"",
309		"I2S_HP_DATAIN",
310		"I2S_HP_MCLK",
311		"I2S_HP_BCK",
312		"I2S_HP_LRCK",
313		"I2S_HP_DATAOUT",
314		"SD_CD_ODL",
315		"EN_PP3300_DISP_X",
316		"TCHSCR_RST_1V8_L",
317		"TCHSCR_REPORT_DISABLE",
318		"EN_PP3300_WLAN_X",
319		"BT_KILL_1V8_L",
320		"I2S_SPKR_DATAOUT",
321		"WIFI_KILL_1V8_L",
322		"BEEP_ON",
323		"SCP_I2C_SENSOR_SCL_1V8",
324		"SCP_I2C_SENSOR_SDA_1V8",
325		"",
326		"",
327		"",
328		"",
329		"AUD_CLK_MOSI",
330		"AUD_SYNC_MOSI",
331		"AUD_DAT_MOSI0",
332		"AUD_DAT_MOSI1",
333		"AUD_DAT_MISO0",
334		"AUD_DAT_MISO1",
335		"AUD_DAT_MISO2",
336		"SCP_VREQ_VAO",
337		"AP_SPI_GSC_TPM_CLK",
338		"AP_SPI_GSC_TPM_MOSI",
339		"AP_SPI_GSC_TPM_CS_L",
340		"AP_SPI_GSC_TPM_MISO",
341		"EN_PP1000_CAM_X",
342		"AP_EDP_BKLTEN",
343		"",
344		"USB3_HUB_RST_L",
345		"",
346		"WLAN_ALERT_ODL",
347		"EC_IN_RW_ODL",
348		"GSC_AP_INT_ODL",
349		"HP_INT_ODL",
350		"CAM0_RST_L",
351		"CAM1_RST_L",
352		"TCHSCR_INT_1V8_L",
353		"CAM1_DET_L",
354		"RST_ALC1011_L",
355		"",
356		"",
357		"BL_PWM_1V8",
358		"UART_AP_TX_DBG_RX",
359		"UART_DBG_TX_AP_RX",
360		"EN_SPKR",
361		"AP_EC_WARM_RST_REQ",
362		"UART_SCP_TX_DBGCON_RX",
363		"UART_DBGCON_TX_SCP_RX",
364		"",
365		"",
366		"KPCOL0",
367		"",
368		"MT6315_GPU_INT",
369		"MT6315_PROC_BC_INT",
370		"SD_CMD",
371		"SD_CLK",
372		"SD_DAT0",
373		"SD_DAT1",
374		"SD_DAT2",
375		"SD_DAT3",
376		"EMMC_DAT7",
377		"EMMC_DAT6",
378		"EMMC_DAT5",
379		"EMMC_DAT4",
380		"EMMC_RSTB",
381		"EMMC_CMD",
382		"EMMC_CLK",
383		"EMMC_DAT3",
384		"EMMC_DAT2",
385		"EMMC_DAT1",
386		"EMMC_DAT0",
387		"EMMC_DSL",
388		"",
389		"",
390		"MT6360_INT_ODL",
391		"SCP_JTAG0_TRSTN",
392		"AP_SPI_EC_CS_L",
393		"AP_SPI_EC_CLK",
394		"AP_SPI_EC_MOSI",
395		"AP_SPI_EC_MISO",
396		"SCP_JTAG0_TMS",
397		"SCP_JTAG0_TCK",
398		"SCP_JTAG0_TDO",
399		"SCP_JTAG0_TDI",
400		"AP_SPI_FLASH_CS_L",
401		"AP_SPI_FLASH_CLK",
402		"AP_SPI_FLASH_MOSI",
403		"AP_SPI_FLASH_MISO";
404
405	i2c0_pins: i2c0-default-pins {
406		pins-bus {
407			pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
408				 <PINMUX_GPIO9__FUNC_SCL0>;
409			bias-disable;
410			drive-strength-microamp = <1000>;
411		};
412	};
413
414	i2c1_pins: i2c1-default-pins {
415		pins-bus {
416			pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
417				 <PINMUX_GPIO11__FUNC_SCL1>;
418			bias-pull-up = <1000>;
419			drive-strength-microamp = <1000>;
420		};
421	};
422
423	i2c2_pins: i2c2-default-pins {
424		pins-bus {
425			pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
426				 <PINMUX_GPIO13__FUNC_SCL2>;
427			bias-disable;
428			drive-strength-microamp = <1000>;
429		};
430	};
431
432	i2c3_pins: i2c3-default-pins {
433		pins-bus {
434			pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
435				 <PINMUX_GPIO15__FUNC_SCL3>;
436			bias-pull-up = <1000>;
437			drive-strength-microamp = <1000>;
438		};
439	};
440
441	i2c4_pins: i2c4-default-pins {
442		pins-bus {
443			pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
444				 <PINMUX_GPIO17__FUNC_SCL4>;
445			bias-pull-up = <1000>;
446			drive-strength = <4>;
447		};
448	};
449
450	i2c5_pins: i2c5-default-pins {
451		pins-bus {
452			pinmux = <PINMUX_GPIO29__FUNC_SCL5>,
453				 <PINMUX_GPIO30__FUNC_SDA5>;
454			bias-disable;
455			drive-strength-microamp = <1000>;
456		};
457	};
458
459	i2c7_pins: i2c7-default-pins {
460		pins-bus {
461			pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
462				 <PINMUX_GPIO28__FUNC_SDA7>;
463			bias-disable;
464		};
465	};
466
467	mmc0_pins_default: mmc0-default-pins {
468		pins-cmd-dat {
469			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
470				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
471				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
472				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
473				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
474				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
475				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
476				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
477				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
478			input-enable;
479			drive-strength = <6>;
480			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
481		};
482
483		pins-clk {
484			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
485			drive-strength = <6>;
486			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
487		};
488
489		pins-rst {
490			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
491			drive-strength = <6>;
492			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
493		};
494	};
495
496	mmc0_pins_uhs: mmc0-uhs-pins {
497		pins-cmd-dat {
498			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
499				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
500				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
501				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
502				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
503				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
504				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
505				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
506				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
507			input-enable;
508			drive-strength = <8>;
509			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
510		};
511
512		pins-clk {
513			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
514			drive-strength = <8>;
515			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
516		};
517
518		pins-ds {
519			pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
520			drive-strength = <8>;
521			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
522		};
523
524		pins-rst {
525			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
526			drive-strength = <8>;
527			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
528		};
529	};
530
531	nor_pins_default: nor-default-pins {
532		pins-ck-io {
533			pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
534				 <PINMUX_GPIO141__FUNC_SPINOR_CK>,
535				 <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
536			drive-strength = <6>;
537			bias-pull-down;
538		};
539
540		pins-cs {
541			pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>;
542			drive-strength = <6>;
543			bias-pull-up;
544		};
545	};
546
547	pio_default: pio-default-pins {
548		pins-wifi-enable {
549			pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
550			output-high;
551			drive-strength = <14>;
552		};
553
554		pins-low-power-pd {
555			pinmux = <PINMUX_GPIO25__FUNC_GPIO25>,
556				 <PINMUX_GPIO26__FUNC_GPIO26>,
557				 <PINMUX_GPIO46__FUNC_GPIO46>,
558				 <PINMUX_GPIO47__FUNC_GPIO47>,
559				 <PINMUX_GPIO48__FUNC_GPIO48>,
560				 <PINMUX_GPIO65__FUNC_GPIO65>,
561				 <PINMUX_GPIO66__FUNC_GPIO66>,
562				 <PINMUX_GPIO67__FUNC_GPIO67>,
563				 <PINMUX_GPIO68__FUNC_GPIO68>,
564				 <PINMUX_GPIO128__FUNC_GPIO128>,
565				 <PINMUX_GPIO129__FUNC_GPIO129>;
566			input-enable;
567			bias-pull-down;
568		};
569
570		pins-low-power-pupd {
571			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
572				 <PINMUX_GPIO78__FUNC_GPIO78>,
573				 <PINMUX_GPIO79__FUNC_GPIO79>,
574				 <PINMUX_GPIO80__FUNC_GPIO80>,
575				 <PINMUX_GPIO83__FUNC_GPIO83>,
576				 <PINMUX_GPIO85__FUNC_GPIO85>,
577				 <PINMUX_GPIO90__FUNC_GPIO90>,
578				 <PINMUX_GPIO91__FUNC_GPIO91>,
579				 <PINMUX_GPIO93__FUNC_GPIO93>,
580				 <PINMUX_GPIO94__FUNC_GPIO94>,
581				 <PINMUX_GPIO95__FUNC_GPIO95>,
582				 <PINMUX_GPIO96__FUNC_GPIO96>,
583				 <PINMUX_GPIO104__FUNC_GPIO104>,
584				 <PINMUX_GPIO105__FUNC_GPIO105>,
585				 <PINMUX_GPIO107__FUNC_GPIO107>;
586			input-enable;
587			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
588		};
589	};
590
591	spi0_pins: spi0-default-pins {
592		pins-cs-mosi-clk {
593			pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
594				 <PINMUX_GPIO134__FUNC_SPIM0_MO>,
595				 <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
596			bias-disable;
597		};
598
599		pins-miso {
600			pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
601			bias-pull-down;
602		};
603	};
604
605	subpmic_default: subpmic-default-pins {
606		subpmic_pin_irq: pins-subpmic-int-n {
607			pinmux = <PINMUX_GPIO130__FUNC_GPIO130>;
608			input-enable;
609			bias-pull-up;
610		};
611	};
612};
613
614&pmic {
615	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
616};
617
618&spi0 {
619	status = "okay";
620
621	pinctrl-names = "default";
622	pinctrl-0 = <&spi0_pins>;
623	mediatek,pad-select = <0>;
624};
625
626&u3phy0 {
627	status = "okay";
628};
629
630&u3phy1 {
631	status = "okay";
632};
633
634&u3phy2 {
635	status = "okay";
636};
637
638&u3phy3 {
639	status = "okay";
640};
641
642&uart0 {
643	status = "okay";
644};
645
646&xhci0 {
647	status = "okay";
648
649	vusb33-supply = <&mt6359_vusb_ldo_reg>;
650	vbus-supply = <&usb_vbus>;
651};
652
653&xhci1 {
654	status = "okay";
655
656	vusb33-supply = <&mt6359_vusb_ldo_reg>;
657	vbus-supply = <&usb_vbus>;
658};
659
660&xhci2 {
661	status = "okay";
662
663	vusb33-supply = <&mt6359_vusb_ldo_reg>;
664	vbus-supply = <&usb_vbus>;
665};
666
667&xhci3 {
668	status = "okay";
669
670	/* MT7921's USB Bluetooth has issues with USB2 LPM */
671	usb2-lpm-disable;
672	vusb33-supply = <&mt6359_vusb_ldo_reg>;
673	vbus-supply = <&usb_vbus>;
674};
675