1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include "mt8195.dtsi" 8#include "mt6359.dtsi" 9 10/ { 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 serial0 = &uart0; 21 }; 22 23 chosen { 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 memory@40000000 { 28 device_type = "memory"; 29 reg = <0 0x40000000 0 0x80000000>; 30 }; 31 32 /* system wide LDO 3.3V power rail */ 33 pp3300_z5: regulator-pp3300-ldo-z5 { 34 compatible = "regulator-fixed"; 35 regulator-name = "pp3300_ldo_z5"; 36 regulator-always-on; 37 regulator-boot-on; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 vin-supply = <&ppvar_sys>; 41 }; 42 43 /* separately switched 3.3V power rail */ 44 pp3300_s3: regulator-pp3300-s3 { 45 compatible = "regulator-fixed"; 46 regulator-name = "pp3300_s3"; 47 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 48 regulator-always-on; 49 regulator-boot-on; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 vin-supply = <&pp3300_z2>; 53 }; 54 55 /* system wide 3.3V power rail */ 56 pp3300_z2: regulator-pp3300-z2 { 57 compatible = "regulator-fixed"; 58 regulator-name = "pp3300_z2"; 59 /* EN pin tied to pp4200_z2, which is controlled by EC */ 60 regulator-always-on; 61 regulator-boot-on; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 vin-supply = <&ppvar_sys>; 65 }; 66 67 /* system wide 4.2V power rail */ 68 pp4200_z2: regulator-pp4200-z2 { 69 compatible = "regulator-fixed"; 70 regulator-name = "pp4200_z2"; 71 /* controlled by EC */ 72 regulator-always-on; 73 regulator-boot-on; 74 regulator-min-microvolt = <4200000>; 75 regulator-max-microvolt = <4200000>; 76 vin-supply = <&ppvar_sys>; 77 }; 78 79 /* system wide switching 5.0V power rail */ 80 pp5000_s5: regulator-pp5000-s5 { 81 compatible = "regulator-fixed"; 82 regulator-name = "pp5000_s5"; 83 /* controlled by EC */ 84 regulator-always-on; 85 regulator-boot-on; 86 regulator-min-microvolt = <5000000>; 87 regulator-max-microvolt = <5000000>; 88 vin-supply = <&ppvar_sys>; 89 }; 90 91 /* system wide semi-regulated power rail from battery or USB */ 92 ppvar_sys: regulator-ppvar-sys { 93 compatible = "regulator-fixed"; 94 regulator-name = "ppvar_sys"; 95 regulator-always-on; 96 regulator-boot-on; 97 }; 98 99 usb_vbus: regulator-5v0-usb-vbus { 100 compatible = "regulator-fixed"; 101 regulator-name = "usb-vbus"; 102 regulator-min-microvolt = <5000000>; 103 regulator-max-microvolt = <5000000>; 104 enable-active-high; 105 regulator-always-on; 106 }; 107}; 108 109&i2c0 { 110 status = "okay"; 111 112 clock-frequency = <400000>; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&i2c0_pins>; 115}; 116 117&i2c1 { 118 status = "okay"; 119 120 clock-frequency = <400000>; 121 i2c-scl-internal-delay-ns = <12500>; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&i2c1_pins>; 124}; 125 126&i2c2 { 127 status = "okay"; 128 129 clock-frequency = <400000>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&i2c2_pins>; 132}; 133 134&i2c3 { 135 status = "okay"; 136 137 clock-frequency = <400000>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&i2c3_pins>; 140}; 141 142&i2c4 { 143 status = "okay"; 144 145 clock-frequency = <400000>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&i2c4_pins>; 148}; 149 150&i2c5 { 151 status = "okay"; 152 153 clock-frequency = <400000>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&i2c5_pins>; 156}; 157 158&i2c7 { 159 status = "okay"; 160 161 clock-frequency = <400000>; 162 pinctrl-names = "default"; 163 pinctrl-0 = <&i2c7_pins>; 164}; 165 166&mmc0 { 167 status = "okay"; 168 169 bus-width = <8>; 170 cap-mmc-highspeed; 171 cap-mmc-hw-reset; 172 hs400-ds-delay = <0x14c11>; 173 max-frequency = <200000000>; 174 mmc-hs200-1_8v; 175 mmc-hs400-1_8v; 176 no-sdio; 177 no-sd; 178 non-removable; 179 pinctrl-names = "default", "state_uhs"; 180 pinctrl-0 = <&mmc0_pins_default>; 181 pinctrl-1 = <&mmc0_pins_uhs>; 182 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 183 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 184}; 185 186/* for CPU-L */ 187&mt6359_vcore_buck_reg { 188 regulator-always-on; 189}; 190 191/* for CORE */ 192&mt6359_vgpu11_buck_reg { 193 regulator-always-on; 194}; 195 196&mt6359_vgpu11_sshub_buck_reg { 197 regulator-always-on; 198 regulator-min-microvolt = <550000>; 199 regulator-max-microvolt = <550000>; 200}; 201 202/* for CORE SRAM */ 203&mt6359_vpu_buck_reg { 204 regulator-always-on; 205}; 206 207&mt6359_vrf12_ldo_reg { 208 regulator-always-on; 209}; 210 211/* for GPU SRAM */ 212&mt6359_vsram_others_ldo_reg { 213 regulator-always-on; 214 regulator-min-microvolt = <750000>; 215 regulator-max-microvolt = <750000>; 216}; 217 218&mt6359_vufs_ldo_reg { 219 regulator-always-on; 220}; 221 222&pio { 223 mediatek,rsel-resistance-in-si-unit; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pio_default>; 226 227 /* 144 lines */ 228 gpio-line-names = 229 "I2S_SPKR_MCLK", 230 "I2S_SPKR_DATAIN", 231 "I2S_SPKR_LRCK", 232 "I2S_SPKR_BCLK", 233 "EC_AP_INT_ODL", 234 /* 235 * AP_FLASH_WP_L is crossystem ABI. Schematics 236 * call it AP_FLASH_WP_ODL. 237 */ 238 "AP_FLASH_WP_L", 239 "TCHPAD_INT_ODL", 240 "EDP_HPD_1V8", 241 "AP_I2C_CAM_SDA", 242 "AP_I2C_CAM_SCL", 243 "AP_I2C_TCHPAD_SDA_1V8", 244 "AP_I2C_TCHPAD_SCL_1V8", 245 "AP_I2C_AUD_SDA", 246 "AP_I2C_AUD_SCL", 247 "AP_I2C_TPM_SDA_1V8", 248 "AP_I2C_TPM_SCL_1V8", 249 "AP_I2C_TCHSCR_SDA_1V8", 250 "AP_I2C_TCHSCR_SCL_1V8", 251 "EC_AP_HPD_OD", 252 "", 253 "PCIE_NVME_RST_L", 254 "PCIE_NVME_CLKREQ_ODL", 255 "PCIE_RST_1V8_L", 256 "PCIE_CLKREQ_1V8_ODL", 257 "PCIE_WAKE_1V8_ODL", 258 "CLK_24M_CAM0", 259 "CAM1_SEN_EN", 260 "AP_I2C_PWR_SCL_1V8", 261 "AP_I2C_PWR_SDA_1V8", 262 "AP_I2C_MISC_SCL", 263 "AP_I2C_MISC_SDA", 264 "EN_PP5000_HDMI_X", 265 "AP_HDMITX_HTPLG", 266 "", 267 "AP_HDMITX_SCL_1V8", 268 "AP_HDMITX_SDA_1V8", 269 "AP_RTC_CLK32K", 270 "AP_EC_WATCHDOG_L", 271 "SRCLKENA0", 272 "SRCLKENA1", 273 "PWRAP_SPI0_CS_L", 274 "PWRAP_SPI0_CK", 275 "PWRAP_SPI0_MOSI", 276 "PWRAP_SPI0_MISO", 277 "SPMI_SCL", 278 "SPMI_SDA", 279 "", 280 "", 281 "", 282 "I2S_HP_DATAIN", 283 "I2S_HP_MCLK", 284 "I2S_HP_BCK", 285 "I2S_HP_LRCK", 286 "I2S_HP_DATAOUT", 287 "SD_CD_ODL", 288 "EN_PP3300_DISP_X", 289 "TCHSCR_RST_1V8_L", 290 "TCHSCR_REPORT_DISABLE", 291 "EN_PP3300_WLAN_X", 292 "BT_KILL_1V8_L", 293 "I2S_SPKR_DATAOUT", 294 "WIFI_KILL_1V8_L", 295 "BEEP_ON", 296 "SCP_I2C_SENSOR_SCL_1V8", 297 "SCP_I2C_SENSOR_SDA_1V8", 298 "", 299 "", 300 "", 301 "", 302 "AUD_CLK_MOSI", 303 "AUD_SYNC_MOSI", 304 "AUD_DAT_MOSI0", 305 "AUD_DAT_MOSI1", 306 "AUD_DAT_MISO0", 307 "AUD_DAT_MISO1", 308 "AUD_DAT_MISO2", 309 "SCP_VREQ_VAO", 310 "AP_SPI_GSC_TPM_CLK", 311 "AP_SPI_GSC_TPM_MOSI", 312 "AP_SPI_GSC_TPM_CS_L", 313 "AP_SPI_GSC_TPM_MISO", 314 "EN_PP1000_CAM_X", 315 "AP_EDP_BKLTEN", 316 "", 317 "USB3_HUB_RST_L", 318 "", 319 "WLAN_ALERT_ODL", 320 "EC_IN_RW_ODL", 321 "GSC_AP_INT_ODL", 322 "HP_INT_ODL", 323 "CAM0_RST_L", 324 "CAM1_RST_L", 325 "TCHSCR_INT_1V8_L", 326 "CAM1_DET_L", 327 "RST_ALC1011_L", 328 "", 329 "", 330 "BL_PWM_1V8", 331 "UART_AP_TX_DBG_RX", 332 "UART_DBG_TX_AP_RX", 333 "EN_SPKR", 334 "AP_EC_WARM_RST_REQ", 335 "UART_SCP_TX_DBGCON_RX", 336 "UART_DBGCON_TX_SCP_RX", 337 "", 338 "", 339 "KPCOL0", 340 "", 341 "MT6315_GPU_INT", 342 "MT6315_PROC_BC_INT", 343 "SD_CMD", 344 "SD_CLK", 345 "SD_DAT0", 346 "SD_DAT1", 347 "SD_DAT2", 348 "SD_DAT3", 349 "EMMC_DAT7", 350 "EMMC_DAT6", 351 "EMMC_DAT5", 352 "EMMC_DAT4", 353 "EMMC_RSTB", 354 "EMMC_CMD", 355 "EMMC_CLK", 356 "EMMC_DAT3", 357 "EMMC_DAT2", 358 "EMMC_DAT1", 359 "EMMC_DAT0", 360 "EMMC_DSL", 361 "", 362 "", 363 "MT6360_INT_ODL", 364 "SCP_JTAG0_TRSTN", 365 "AP_SPI_EC_CS_L", 366 "AP_SPI_EC_CLK", 367 "AP_SPI_EC_MOSI", 368 "AP_SPI_EC_MISO", 369 "SCP_JTAG0_TMS", 370 "SCP_JTAG0_TCK", 371 "SCP_JTAG0_TDO", 372 "SCP_JTAG0_TDI", 373 "AP_SPI_FLASH_CS_L", 374 "AP_SPI_FLASH_CLK", 375 "AP_SPI_FLASH_MOSI", 376 "AP_SPI_FLASH_MISO"; 377 378 i2c0_pins: i2c0-default-pins { 379 pins-bus { 380 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 381 <PINMUX_GPIO9__FUNC_SCL0>; 382 bias-disable; 383 drive-strength-microamp = <1000>; 384 }; 385 }; 386 387 i2c1_pins: i2c1-default-pins { 388 pins-bus { 389 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 390 <PINMUX_GPIO11__FUNC_SCL1>; 391 bias-pull-up = <1000>; 392 drive-strength-microamp = <1000>; 393 }; 394 }; 395 396 i2c2_pins: i2c2-default-pins { 397 pins-bus { 398 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 399 <PINMUX_GPIO13__FUNC_SCL2>; 400 bias-disable; 401 drive-strength-microamp = <1000>; 402 }; 403 }; 404 405 i2c3_pins: i2c3-default-pins { 406 pins-bus { 407 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 408 <PINMUX_GPIO15__FUNC_SCL3>; 409 bias-pull-up = <1000>; 410 drive-strength-microamp = <1000>; 411 }; 412 }; 413 414 i2c4_pins: i2c4-default-pins { 415 pins-bus { 416 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 417 <PINMUX_GPIO17__FUNC_SCL4>; 418 bias-pull-up = <1000>; 419 drive-strength = <4>; 420 }; 421 }; 422 423 i2c5_pins: i2c5-default-pins { 424 pins-bus { 425 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 426 <PINMUX_GPIO30__FUNC_SDA5>; 427 bias-disable; 428 drive-strength-microamp = <1000>; 429 }; 430 }; 431 432 i2c7_pins: i2c7-default-pins { 433 pins-bus { 434 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 435 <PINMUX_GPIO28__FUNC_SDA7>; 436 bias-disable; 437 }; 438 }; 439 440 mmc0_pins_default: mmc0-default-pins { 441 pins-cmd-dat { 442 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 443 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 444 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 445 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 446 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 447 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 448 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 449 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 450 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 451 input-enable; 452 drive-strength = <6>; 453 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 454 }; 455 456 pins-clk { 457 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 458 drive-strength = <6>; 459 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 460 }; 461 462 pins-rst { 463 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 464 drive-strength = <6>; 465 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 466 }; 467 }; 468 469 mmc0_pins_uhs: mmc0-uhs-pins { 470 pins-cmd-dat { 471 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 472 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 473 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 474 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 475 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 476 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 477 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 478 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 479 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 480 input-enable; 481 drive-strength = <8>; 482 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 483 }; 484 485 pins-clk { 486 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 487 drive-strength = <8>; 488 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 489 }; 490 491 pins-ds { 492 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 493 drive-strength = <8>; 494 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 495 }; 496 497 pins-rst { 498 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 499 drive-strength = <8>; 500 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 501 }; 502 }; 503 504 pio_default: pio-default-pins { 505 pins-wifi-enable { 506 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 507 output-high; 508 drive-strength = <14>; 509 }; 510 511 pins-low-power-pd { 512 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 513 <PINMUX_GPIO26__FUNC_GPIO26>, 514 <PINMUX_GPIO46__FUNC_GPIO46>, 515 <PINMUX_GPIO47__FUNC_GPIO47>, 516 <PINMUX_GPIO48__FUNC_GPIO48>, 517 <PINMUX_GPIO65__FUNC_GPIO65>, 518 <PINMUX_GPIO66__FUNC_GPIO66>, 519 <PINMUX_GPIO67__FUNC_GPIO67>, 520 <PINMUX_GPIO68__FUNC_GPIO68>, 521 <PINMUX_GPIO128__FUNC_GPIO128>, 522 <PINMUX_GPIO129__FUNC_GPIO129>; 523 input-enable; 524 bias-pull-down; 525 }; 526 527 pins-low-power-pupd { 528 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 529 <PINMUX_GPIO78__FUNC_GPIO78>, 530 <PINMUX_GPIO79__FUNC_GPIO79>, 531 <PINMUX_GPIO80__FUNC_GPIO80>, 532 <PINMUX_GPIO83__FUNC_GPIO83>, 533 <PINMUX_GPIO85__FUNC_GPIO85>, 534 <PINMUX_GPIO90__FUNC_GPIO90>, 535 <PINMUX_GPIO91__FUNC_GPIO91>, 536 <PINMUX_GPIO93__FUNC_GPIO93>, 537 <PINMUX_GPIO94__FUNC_GPIO94>, 538 <PINMUX_GPIO95__FUNC_GPIO95>, 539 <PINMUX_GPIO96__FUNC_GPIO96>, 540 <PINMUX_GPIO104__FUNC_GPIO104>, 541 <PINMUX_GPIO105__FUNC_GPIO105>, 542 <PINMUX_GPIO107__FUNC_GPIO107>; 543 input-enable; 544 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 545 }; 546 }; 547 548 spi0_pins: spi0-default-pins { 549 pins-cs-mosi-clk { 550 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 551 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 552 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 553 bias-disable; 554 }; 555 556 pins-miso { 557 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 558 bias-pull-down; 559 }; 560 }; 561}; 562 563&pmic { 564 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 565}; 566 567&spi0 { 568 status = "okay"; 569 570 pinctrl-names = "default"; 571 pinctrl-0 = <&spi0_pins>; 572 mediatek,pad-select = <0>; 573}; 574 575&u3phy0 { 576 status = "okay"; 577}; 578 579&u3phy1 { 580 status = "okay"; 581}; 582 583&u3phy2 { 584 status = "okay"; 585}; 586 587&u3phy3 { 588 status = "okay"; 589}; 590 591&uart0 { 592 status = "okay"; 593}; 594 595&xhci0 { 596 status = "okay"; 597 598 vusb33-supply = <&mt6359_vusb_ldo_reg>; 599 vbus-supply = <&usb_vbus>; 600}; 601 602&xhci1 { 603 status = "okay"; 604 605 vusb33-supply = <&mt6359_vusb_ldo_reg>; 606 vbus-supply = <&usb_vbus>; 607}; 608 609&xhci2 { 610 status = "okay"; 611 612 vusb33-supply = <&mt6359_vusb_ldo_reg>; 613 vbus-supply = <&usb_vbus>; 614}; 615 616&xhci3 { 617 status = "okay"; 618 619 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 620 usb2-lpm-disable; 621 vusb33-supply = <&mt6359_vusb_ldo_reg>; 622 vbus-supply = <&usb_vbus>; 623}; 624