1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 reg = <0 0x40000000 0 0x80000000>; 32 }; 33 34 /* system wide LDO 3.3V power rail */ 35 pp3300_z5: regulator-pp3300-ldo-z5 { 36 compatible = "regulator-fixed"; 37 regulator-name = "pp3300_ldo_z5"; 38 regulator-always-on; 39 regulator-boot-on; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 vin-supply = <&ppvar_sys>; 43 }; 44 45 /* separately switched 3.3V power rail */ 46 pp3300_s3: regulator-pp3300-s3 { 47 compatible = "regulator-fixed"; 48 regulator-name = "pp3300_s3"; 49 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 50 regulator-always-on; 51 regulator-boot-on; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 vin-supply = <&pp3300_z2>; 55 }; 56 57 /* system wide 3.3V power rail */ 58 pp3300_z2: regulator-pp3300-z2 { 59 compatible = "regulator-fixed"; 60 regulator-name = "pp3300_z2"; 61 /* EN pin tied to pp4200_z2, which is controlled by EC */ 62 regulator-always-on; 63 regulator-boot-on; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 vin-supply = <&ppvar_sys>; 67 }; 68 69 /* system wide 4.2V power rail */ 70 pp4200_z2: regulator-pp4200-z2 { 71 compatible = "regulator-fixed"; 72 regulator-name = "pp4200_z2"; 73 /* controlled by EC */ 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <4200000>; 77 regulator-max-microvolt = <4200000>; 78 vin-supply = <&ppvar_sys>; 79 }; 80 81 /* system wide switching 5.0V power rail */ 82 pp5000_s5: regulator-pp5000-s5 { 83 compatible = "regulator-fixed"; 84 regulator-name = "pp5000_s5"; 85 /* controlled by EC */ 86 regulator-always-on; 87 regulator-boot-on; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 vin-supply = <&ppvar_sys>; 91 }; 92 93 /* system wide semi-regulated power rail from battery or USB */ 94 ppvar_sys: regulator-ppvar-sys { 95 compatible = "regulator-fixed"; 96 regulator-name = "ppvar_sys"; 97 regulator-always-on; 98 regulator-boot-on; 99 }; 100 101 usb_vbus: regulator-5v0-usb-vbus { 102 compatible = "regulator-fixed"; 103 regulator-name = "usb-vbus"; 104 regulator-min-microvolt = <5000000>; 105 regulator-max-microvolt = <5000000>; 106 enable-active-high; 107 regulator-always-on; 108 }; 109 110 reserved_memory: reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 scp_mem: memory@50000000 { 116 compatible = "shared-dma-pool"; 117 reg = <0 0x50000000 0 0x2900000>; 118 no-map; 119 }; 120 121 adsp_mem: memory@60000000 { 122 compatible = "shared-dma-pool"; 123 reg = <0 0x60000000 0 0xd80000>; 124 no-map; 125 }; 126 127 afe_mem: memory@60d80000 { 128 compatible = "shared-dma-pool"; 129 reg = <0 0x60d80000 0 0x100000>; 130 no-map; 131 }; 132 133 adsp_device_mem: memory@60e80000 { 134 compatible = "shared-dma-pool"; 135 reg = <0 0x60e80000 0 0x280000>; 136 no-map; 137 }; 138 }; 139}; 140 141&adsp { 142 status = "okay"; 143 144 memory-region = <&adsp_device_mem>, <&adsp_mem>; 145}; 146 147&afe { 148 status = "okay"; 149 150 mediatek,etdm-in2-cowork-source = <2>; 151 mediatek,etdm-out2-cowork-source = <0>; 152 memory-region = <&afe_mem>; 153}; 154 155&dp_intf0 { 156 status = "okay"; 157 158 port { 159 dp_intf0_out: endpoint { 160 remote-endpoint = <&edp_in>; 161 }; 162 }; 163}; 164 165&dp_intf1 { 166 status = "okay"; 167 168 port { 169 dp_intf1_out: endpoint { 170 remote-endpoint = <&dptx_in>; 171 }; 172 }; 173}; 174 175&edp_tx { 176 status = "okay"; 177 178 pinctrl-names = "default"; 179 pinctrl-0 = <&edptx_pins_default>; 180 181 ports { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 185 port@0 { 186 reg = <0>; 187 edp_in: endpoint { 188 remote-endpoint = <&dp_intf0_out>; 189 }; 190 }; 191 192 port@1 { 193 reg = <1>; 194 edp_out: endpoint { 195 data-lanes = <0 1 2 3>; 196 }; 197 }; 198 }; 199}; 200 201&dp_tx { 202 status = "okay"; 203 204 pinctrl-names = "default"; 205 pinctrl-0 = <&dptx_pin>; 206 207 ports { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 211 port@0 { 212 reg = <0>; 213 dptx_in: endpoint { 214 remote-endpoint = <&dp_intf1_out>; 215 }; 216 }; 217 218 port@1 { 219 reg = <1>; 220 dptx_out: endpoint { 221 data-lanes = <0 1 2 3>; 222 }; 223 }; 224 }; 225}; 226 227&i2c0 { 228 status = "okay"; 229 230 clock-frequency = <400000>; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&i2c0_pins>; 233}; 234 235&i2c1 { 236 status = "okay"; 237 238 clock-frequency = <400000>; 239 i2c-scl-internal-delay-ns = <12500>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&i2c1_pins>; 242 243 trackpad@15 { 244 compatible = "elan,ekth3000"; 245 reg = <0x15>; 246 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&trackpad_pins>; 249 vcc-supply = <&pp3300_s3>; 250 wakeup-source; 251 }; 252}; 253 254&i2c2 { 255 status = "okay"; 256 257 clock-frequency = <400000>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&i2c2_pins>; 260}; 261 262&i2c3 { 263 status = "okay"; 264 265 clock-frequency = <400000>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&i2c3_pins>; 268 269 tpm@50 { 270 compatible = "google,cr50"; 271 reg = <0x50>; 272 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&cr50_int>; 275 }; 276}; 277 278&i2c4 { 279 status = "okay"; 280 281 clock-frequency = <400000>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c4_pins>; 284 285 ts_10: touchscreen@10 { 286 compatible = "hid-over-i2c"; 287 reg = <0x10>; 288 hid-descr-addr = <0x0001>; 289 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&touchscreen_pins>; 292 post-power-on-delay-ms = <10>; 293 vdd-supply = <&pp3300_s3>; 294 status = "disabled"; 295 }; 296}; 297 298&i2c5 { 299 status = "okay"; 300 301 clock-frequency = <400000>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&i2c5_pins>; 304}; 305 306&i2c7 { 307 status = "okay"; 308 309 clock-frequency = <400000>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&i2c7_pins>; 312 313 pmic@34 { 314 #interrupt-cells = <1>; 315 compatible = "mediatek,mt6360"; 316 reg = <0x34>; 317 interrupt-controller; 318 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 319 interrupt-names = "IRQB"; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&subpmic_default>; 322 wakeup-source; 323 }; 324}; 325 326&mmc0 { 327 status = "okay"; 328 329 bus-width = <8>; 330 cap-mmc-highspeed; 331 cap-mmc-hw-reset; 332 hs400-ds-delay = <0x14c11>; 333 max-frequency = <200000000>; 334 mmc-hs200-1_8v; 335 mmc-hs400-1_8v; 336 no-sdio; 337 no-sd; 338 non-removable; 339 pinctrl-names = "default", "state_uhs"; 340 pinctrl-0 = <&mmc0_pins_default>; 341 pinctrl-1 = <&mmc0_pins_uhs>; 342 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 343 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 344}; 345 346&mmc1 { 347 status = "okay"; 348 349 bus-width = <4>; 350 cap-sd-highspeed; 351 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 352 max-frequency = <200000000>; 353 no-mmc; 354 no-sdio; 355 pinctrl-names = "default", "state_uhs"; 356 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 357 pinctrl-1 = <&mmc1_pins_default>; 358 sd-uhs-sdr50; 359 sd-uhs-sdr104; 360 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 361 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 362}; 363 364/* for CPU-L */ 365&mt6359_vcore_buck_reg { 366 regulator-always-on; 367}; 368 369/* for CORE */ 370&mt6359_vgpu11_buck_reg { 371 regulator-always-on; 372}; 373 374&mt6359_vgpu11_sshub_buck_reg { 375 regulator-always-on; 376 regulator-min-microvolt = <550000>; 377 regulator-max-microvolt = <550000>; 378}; 379 380/* for CORE SRAM */ 381&mt6359_vpu_buck_reg { 382 regulator-always-on; 383}; 384 385&mt6359_vrf12_ldo_reg { 386 regulator-always-on; 387}; 388 389/* for GPU SRAM */ 390&mt6359_vsram_others_ldo_reg { 391 regulator-always-on; 392 regulator-min-microvolt = <750000>; 393 regulator-max-microvolt = <750000>; 394}; 395 396&mt6359_vufs_ldo_reg { 397 regulator-always-on; 398}; 399 400&nor_flash { 401 status = "okay"; 402 403 pinctrl-names = "default"; 404 pinctrl-0 = <&nor_pins_default>; 405 406 flash@0 { 407 compatible = "jedec,spi-nor"; 408 reg = <0>; 409 spi-max-frequency = <52000000>; 410 spi-rx-bus-width = <2>; 411 spi-tx-bus-width = <2>; 412 }; 413}; 414 415&pio { 416 mediatek,rsel-resistance-in-si-unit; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pio_default>; 419 420 /* 144 lines */ 421 gpio-line-names = 422 "I2S_SPKR_MCLK", 423 "I2S_SPKR_DATAIN", 424 "I2S_SPKR_LRCK", 425 "I2S_SPKR_BCLK", 426 "EC_AP_INT_ODL", 427 /* 428 * AP_FLASH_WP_L is crossystem ABI. Schematics 429 * call it AP_FLASH_WP_ODL. 430 */ 431 "AP_FLASH_WP_L", 432 "TCHPAD_INT_ODL", 433 "EDP_HPD_1V8", 434 "AP_I2C_CAM_SDA", 435 "AP_I2C_CAM_SCL", 436 "AP_I2C_TCHPAD_SDA_1V8", 437 "AP_I2C_TCHPAD_SCL_1V8", 438 "AP_I2C_AUD_SDA", 439 "AP_I2C_AUD_SCL", 440 "AP_I2C_TPM_SDA_1V8", 441 "AP_I2C_TPM_SCL_1V8", 442 "AP_I2C_TCHSCR_SDA_1V8", 443 "AP_I2C_TCHSCR_SCL_1V8", 444 "EC_AP_HPD_OD", 445 "", 446 "PCIE_NVME_RST_L", 447 "PCIE_NVME_CLKREQ_ODL", 448 "PCIE_RST_1V8_L", 449 "PCIE_CLKREQ_1V8_ODL", 450 "PCIE_WAKE_1V8_ODL", 451 "CLK_24M_CAM0", 452 "CAM1_SEN_EN", 453 "AP_I2C_PWR_SCL_1V8", 454 "AP_I2C_PWR_SDA_1V8", 455 "AP_I2C_MISC_SCL", 456 "AP_I2C_MISC_SDA", 457 "EN_PP5000_HDMI_X", 458 "AP_HDMITX_HTPLG", 459 "", 460 "AP_HDMITX_SCL_1V8", 461 "AP_HDMITX_SDA_1V8", 462 "AP_RTC_CLK32K", 463 "AP_EC_WATCHDOG_L", 464 "SRCLKENA0", 465 "SRCLKENA1", 466 "PWRAP_SPI0_CS_L", 467 "PWRAP_SPI0_CK", 468 "PWRAP_SPI0_MOSI", 469 "PWRAP_SPI0_MISO", 470 "SPMI_SCL", 471 "SPMI_SDA", 472 "", 473 "", 474 "", 475 "I2S_HP_DATAIN", 476 "I2S_HP_MCLK", 477 "I2S_HP_BCK", 478 "I2S_HP_LRCK", 479 "I2S_HP_DATAOUT", 480 "SD_CD_ODL", 481 "EN_PP3300_DISP_X", 482 "TCHSCR_RST_1V8_L", 483 "TCHSCR_REPORT_DISABLE", 484 "EN_PP3300_WLAN_X", 485 "BT_KILL_1V8_L", 486 "I2S_SPKR_DATAOUT", 487 "WIFI_KILL_1V8_L", 488 "BEEP_ON", 489 "SCP_I2C_SENSOR_SCL_1V8", 490 "SCP_I2C_SENSOR_SDA_1V8", 491 "", 492 "", 493 "", 494 "", 495 "AUD_CLK_MOSI", 496 "AUD_SYNC_MOSI", 497 "AUD_DAT_MOSI0", 498 "AUD_DAT_MOSI1", 499 "AUD_DAT_MISO0", 500 "AUD_DAT_MISO1", 501 "AUD_DAT_MISO2", 502 "SCP_VREQ_VAO", 503 "AP_SPI_GSC_TPM_CLK", 504 "AP_SPI_GSC_TPM_MOSI", 505 "AP_SPI_GSC_TPM_CS_L", 506 "AP_SPI_GSC_TPM_MISO", 507 "EN_PP1000_CAM_X", 508 "AP_EDP_BKLTEN", 509 "", 510 "USB3_HUB_RST_L", 511 "", 512 "WLAN_ALERT_ODL", 513 "EC_IN_RW_ODL", 514 "GSC_AP_INT_ODL", 515 "HP_INT_ODL", 516 "CAM0_RST_L", 517 "CAM1_RST_L", 518 "TCHSCR_INT_1V8_L", 519 "CAM1_DET_L", 520 "RST_ALC1011_L", 521 "", 522 "", 523 "BL_PWM_1V8", 524 "UART_AP_TX_DBG_RX", 525 "UART_DBG_TX_AP_RX", 526 "EN_SPKR", 527 "AP_EC_WARM_RST_REQ", 528 "UART_SCP_TX_DBGCON_RX", 529 "UART_DBGCON_TX_SCP_RX", 530 "", 531 "", 532 "KPCOL0", 533 "", 534 "MT6315_GPU_INT", 535 "MT6315_PROC_BC_INT", 536 "SD_CMD", 537 "SD_CLK", 538 "SD_DAT0", 539 "SD_DAT1", 540 "SD_DAT2", 541 "SD_DAT3", 542 "EMMC_DAT7", 543 "EMMC_DAT6", 544 "EMMC_DAT5", 545 "EMMC_DAT4", 546 "EMMC_RSTB", 547 "EMMC_CMD", 548 "EMMC_CLK", 549 "EMMC_DAT3", 550 "EMMC_DAT2", 551 "EMMC_DAT1", 552 "EMMC_DAT0", 553 "EMMC_DSL", 554 "", 555 "", 556 "MT6360_INT_ODL", 557 "SCP_JTAG0_TRSTN", 558 "AP_SPI_EC_CS_L", 559 "AP_SPI_EC_CLK", 560 "AP_SPI_EC_MOSI", 561 "AP_SPI_EC_MISO", 562 "SCP_JTAG0_TMS", 563 "SCP_JTAG0_TCK", 564 "SCP_JTAG0_TDO", 565 "SCP_JTAG0_TDI", 566 "AP_SPI_FLASH_CS_L", 567 "AP_SPI_FLASH_CLK", 568 "AP_SPI_FLASH_MOSI", 569 "AP_SPI_FLASH_MISO"; 570 571 cr50_int: cr50-irq-default-pins { 572 pins-gsc-ap-int-odl { 573 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 574 input-enable; 575 }; 576 }; 577 578 cros_ec_int: cros-ec-irq-default-pins { 579 pins-ec-ap-int-odl { 580 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 581 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 582 input-enable; 583 }; 584 }; 585 586 edptx_pins_default: edptx-default-pins { 587 pins-cmd-dat { 588 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 589 bias-pull-up; 590 }; 591 }; 592 593 dptx_pin: dptx-default-pins { 594 pins-cmd-dat { 595 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 596 bias-pull-up; 597 }; 598 }; 599 600 i2c0_pins: i2c0-default-pins { 601 pins-bus { 602 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 603 <PINMUX_GPIO9__FUNC_SCL0>; 604 bias-disable; 605 drive-strength-microamp = <1000>; 606 }; 607 }; 608 609 i2c1_pins: i2c1-default-pins { 610 pins-bus { 611 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 612 <PINMUX_GPIO11__FUNC_SCL1>; 613 bias-pull-up = <1000>; 614 drive-strength-microamp = <1000>; 615 }; 616 }; 617 618 i2c2_pins: i2c2-default-pins { 619 pins-bus { 620 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 621 <PINMUX_GPIO13__FUNC_SCL2>; 622 bias-disable; 623 drive-strength-microamp = <1000>; 624 }; 625 }; 626 627 i2c3_pins: i2c3-default-pins { 628 pins-bus { 629 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 630 <PINMUX_GPIO15__FUNC_SCL3>; 631 bias-pull-up = <1000>; 632 drive-strength-microamp = <1000>; 633 }; 634 }; 635 636 i2c4_pins: i2c4-default-pins { 637 pins-bus { 638 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 639 <PINMUX_GPIO17__FUNC_SCL4>; 640 bias-pull-up = <1000>; 641 drive-strength = <4>; 642 }; 643 }; 644 645 i2c5_pins: i2c5-default-pins { 646 pins-bus { 647 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 648 <PINMUX_GPIO30__FUNC_SDA5>; 649 bias-disable; 650 drive-strength-microamp = <1000>; 651 }; 652 }; 653 654 i2c7_pins: i2c7-default-pins { 655 pins-bus { 656 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 657 <PINMUX_GPIO28__FUNC_SDA7>; 658 bias-disable; 659 }; 660 }; 661 662 mmc0_pins_default: mmc0-default-pins { 663 pins-cmd-dat { 664 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 665 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 666 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 667 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 668 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 669 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 670 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 671 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 672 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 673 input-enable; 674 drive-strength = <6>; 675 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 676 }; 677 678 pins-clk { 679 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 680 drive-strength = <6>; 681 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 682 }; 683 684 pins-rst { 685 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 686 drive-strength = <6>; 687 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 688 }; 689 }; 690 691 mmc0_pins_uhs: mmc0-uhs-pins { 692 pins-cmd-dat { 693 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 694 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 695 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 696 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 697 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 698 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 699 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 700 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 701 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 702 input-enable; 703 drive-strength = <8>; 704 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 705 }; 706 707 pins-clk { 708 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 709 drive-strength = <8>; 710 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 711 }; 712 713 pins-ds { 714 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 715 drive-strength = <8>; 716 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 717 }; 718 719 pins-rst { 720 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 721 drive-strength = <8>; 722 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 723 }; 724 }; 725 726 mmc1_pins_detect: mmc1-detect-pins { 727 pins-insert { 728 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 729 bias-pull-up; 730 }; 731 }; 732 733 mmc1_pins_default: mmc1-default-pins { 734 pins-cmd-dat { 735 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 736 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 737 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 738 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 739 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 740 input-enable; 741 drive-strength = <8>; 742 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 743 }; 744 745 pins-clk { 746 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 747 drive-strength = <8>; 748 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 749 }; 750 }; 751 752 nor_pins_default: nor-default-pins { 753 pins-ck-io { 754 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 755 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 756 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 757 drive-strength = <6>; 758 bias-pull-down; 759 }; 760 761 pins-cs { 762 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 763 drive-strength = <6>; 764 bias-pull-up; 765 }; 766 }; 767 768 pio_default: pio-default-pins { 769 pins-wifi-enable { 770 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 771 output-high; 772 drive-strength = <14>; 773 }; 774 775 pins-low-power-pd { 776 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 777 <PINMUX_GPIO26__FUNC_GPIO26>, 778 <PINMUX_GPIO46__FUNC_GPIO46>, 779 <PINMUX_GPIO47__FUNC_GPIO47>, 780 <PINMUX_GPIO48__FUNC_GPIO48>, 781 <PINMUX_GPIO65__FUNC_GPIO65>, 782 <PINMUX_GPIO66__FUNC_GPIO66>, 783 <PINMUX_GPIO67__FUNC_GPIO67>, 784 <PINMUX_GPIO68__FUNC_GPIO68>, 785 <PINMUX_GPIO128__FUNC_GPIO128>, 786 <PINMUX_GPIO129__FUNC_GPIO129>; 787 input-enable; 788 bias-pull-down; 789 }; 790 791 pins-low-power-pupd { 792 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 793 <PINMUX_GPIO78__FUNC_GPIO78>, 794 <PINMUX_GPIO79__FUNC_GPIO79>, 795 <PINMUX_GPIO80__FUNC_GPIO80>, 796 <PINMUX_GPIO83__FUNC_GPIO83>, 797 <PINMUX_GPIO85__FUNC_GPIO85>, 798 <PINMUX_GPIO90__FUNC_GPIO90>, 799 <PINMUX_GPIO91__FUNC_GPIO91>, 800 <PINMUX_GPIO93__FUNC_GPIO93>, 801 <PINMUX_GPIO94__FUNC_GPIO94>, 802 <PINMUX_GPIO95__FUNC_GPIO95>, 803 <PINMUX_GPIO96__FUNC_GPIO96>, 804 <PINMUX_GPIO104__FUNC_GPIO104>, 805 <PINMUX_GPIO105__FUNC_GPIO105>, 806 <PINMUX_GPIO107__FUNC_GPIO107>; 807 input-enable; 808 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 809 }; 810 }; 811 812 scp_pins: scp-default-pins { 813 pins-vreq { 814 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 815 bias-disable; 816 input-enable; 817 }; 818 }; 819 820 spi0_pins: spi0-default-pins { 821 pins-cs-mosi-clk { 822 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 823 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 824 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 825 bias-disable; 826 }; 827 828 pins-miso { 829 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 830 bias-pull-down; 831 }; 832 }; 833 834 subpmic_default: subpmic-default-pins { 835 subpmic_pin_irq: pins-subpmic-int-n { 836 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 837 input-enable; 838 bias-pull-up; 839 }; 840 }; 841 842 trackpad_pins: trackpad-default-pins { 843 pins-int-n { 844 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 845 input-enable; 846 bias-pull-up; 847 }; 848 }; 849 850 touchscreen_pins: touchscreen-default-pins { 851 pins-int-n { 852 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 853 input-enable; 854 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 855 }; 856 pins-rst { 857 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 858 output-high; 859 }; 860 pins-report-sw { 861 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 862 output-low; 863 }; 864 }; 865}; 866 867&pmic { 868 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 869}; 870 871&scp { 872 status = "okay"; 873 874 firmware-name = "mediatek/mt8195/scp.img"; 875 memory-region = <&scp_mem>; 876 pinctrl-names = "default"; 877 pinctrl-0 = <&scp_pins>; 878 879 cros-ec-rpmsg { 880 compatible = "google,cros-ec-rpmsg"; 881 mediatek,rpmsg-name = "cros-ec-rpmsg"; 882 }; 883}; 884 885&spi0 { 886 status = "okay"; 887 888 pinctrl-names = "default"; 889 pinctrl-0 = <&spi0_pins>; 890 mediatek,pad-select = <0>; 891 892 cros_ec: ec@0 { 893 #address-cells = <1>; 894 #size-cells = <0>; 895 896 compatible = "google,cros-ec-spi"; 897 reg = <0>; 898 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 899 pinctrl-names = "default"; 900 pinctrl-0 = <&cros_ec_int>; 901 spi-max-frequency = <3000000>; 902 903 keyboard-backlight { 904 compatible = "google,cros-kbd-led-backlight"; 905 }; 906 907 i2c_tunnel: i2c-tunnel { 908 compatible = "google,cros-ec-i2c-tunnel"; 909 google,remote-bus = <0>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 }; 913 914 mt_pmic_vmc_ldo_reg: regulator@0 { 915 compatible = "google,cros-ec-regulator"; 916 reg = <0>; 917 regulator-name = "mt_pmic_vmc_ldo"; 918 regulator-min-microvolt = <1200000>; 919 regulator-max-microvolt = <3600000>; 920 }; 921 922 mt_pmic_vmch_ldo_reg: regulator@1 { 923 compatible = "google,cros-ec-regulator"; 924 reg = <1>; 925 regulator-name = "mt_pmic_vmch_ldo"; 926 regulator-min-microvolt = <2700000>; 927 regulator-max-microvolt = <3600000>; 928 }; 929 930 typec { 931 compatible = "google,cros-ec-typec"; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 935 usb_c0: connector@0 { 936 compatible = "usb-c-connector"; 937 reg = <0>; 938 power-role = "dual"; 939 data-role = "host"; 940 try-power-role = "source"; 941 }; 942 943 usb_c1: connector@1 { 944 compatible = "usb-c-connector"; 945 reg = <1>; 946 power-role = "dual"; 947 data-role = "host"; 948 try-power-role = "source"; 949 }; 950 }; 951 }; 952}; 953 954&spmi { 955 #address-cells = <2>; 956 #size-cells = <0>; 957 958 mt6315@6 { 959 compatible = "mediatek,mt6315-regulator"; 960 reg = <0x6 SPMI_USID>; 961 962 regulators { 963 mt6315_6_vbuck1: vbuck1 { 964 regulator-compatible = "vbuck1"; 965 regulator-name = "Vbcpu"; 966 regulator-min-microvolt = <300000>; 967 regulator-max-microvolt = <1193750>; 968 regulator-enable-ramp-delay = <256>; 969 regulator-ramp-delay = <6250>; 970 regulator-allowed-modes = <0 1 2>; 971 regulator-always-on; 972 }; 973 }; 974 }; 975 976 mt6315@7 { 977 compatible = "mediatek,mt6315-regulator"; 978 reg = <0x7 SPMI_USID>; 979 980 regulators { 981 mt6315_7_vbuck1: vbuck1 { 982 regulator-compatible = "vbuck1"; 983 regulator-name = "Vgpu"; 984 regulator-min-microvolt = <625000>; 985 regulator-max-microvolt = <1193750>; 986 regulator-enable-ramp-delay = <256>; 987 regulator-ramp-delay = <6250>; 988 regulator-allowed-modes = <0 1 2>; 989 regulator-always-on; 990 }; 991 }; 992 }; 993}; 994 995&u3phy0 { 996 status = "okay"; 997}; 998 999&u3phy1 { 1000 status = "okay"; 1001}; 1002 1003&u3phy2 { 1004 status = "okay"; 1005}; 1006 1007&u3phy3 { 1008 status = "okay"; 1009}; 1010 1011&uart0 { 1012 status = "okay"; 1013}; 1014 1015&xhci0 { 1016 status = "okay"; 1017 1018 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1019 vbus-supply = <&usb_vbus>; 1020}; 1021 1022&xhci1 { 1023 status = "okay"; 1024 1025 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1026 vbus-supply = <&usb_vbus>; 1027}; 1028 1029&xhci2 { 1030 status = "okay"; 1031 1032 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1033 vbus-supply = <&usb_vbus>; 1034}; 1035 1036&xhci3 { 1037 status = "okay"; 1038 1039 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1040 usb2-lpm-disable; 1041 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1042 vbus-supply = <&usb_vbus>; 1043}; 1044 1045#include <arm/cros-ec-keyboard.dtsi> 1046#include <arm/cros-ec-sbs.dtsi> 1047 1048&keyboard_controller { 1049 function-row-physmap = < 1050 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1051 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1052 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1053 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1054 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1055 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1056 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1057 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1058 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1059 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1060 >; 1061 1062 linux,keymap = < 1063 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1064 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1065 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1066 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1067 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 1068 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 1069 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 1070 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1071 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1072 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1073 1074 CROS_STD_MAIN_KEYMAP 1075 >; 1076}; 1077