1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 reg = <0 0x40000000 0 0x80000000>; 32 }; 33 34 /* system wide LDO 3.3V power rail */ 35 pp3300_z5: regulator-pp3300-ldo-z5 { 36 compatible = "regulator-fixed"; 37 regulator-name = "pp3300_ldo_z5"; 38 regulator-always-on; 39 regulator-boot-on; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 vin-supply = <&ppvar_sys>; 43 }; 44 45 /* separately switched 3.3V power rail */ 46 pp3300_s3: regulator-pp3300-s3 { 47 compatible = "regulator-fixed"; 48 regulator-name = "pp3300_s3"; 49 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 50 regulator-always-on; 51 regulator-boot-on; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 vin-supply = <&pp3300_z2>; 55 }; 56 57 /* system wide 3.3V power rail */ 58 pp3300_z2: regulator-pp3300-z2 { 59 compatible = "regulator-fixed"; 60 regulator-name = "pp3300_z2"; 61 /* EN pin tied to pp4200_z2, which is controlled by EC */ 62 regulator-always-on; 63 regulator-boot-on; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 vin-supply = <&ppvar_sys>; 67 }; 68 69 /* system wide 4.2V power rail */ 70 pp4200_z2: regulator-pp4200-z2 { 71 compatible = "regulator-fixed"; 72 regulator-name = "pp4200_z2"; 73 /* controlled by EC */ 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <4200000>; 77 regulator-max-microvolt = <4200000>; 78 vin-supply = <&ppvar_sys>; 79 }; 80 81 /* system wide switching 5.0V power rail */ 82 pp5000_s5: regulator-pp5000-s5 { 83 compatible = "regulator-fixed"; 84 regulator-name = "pp5000_s5"; 85 /* controlled by EC */ 86 regulator-always-on; 87 regulator-boot-on; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 vin-supply = <&ppvar_sys>; 91 }; 92 93 /* system wide semi-regulated power rail from battery or USB */ 94 ppvar_sys: regulator-ppvar-sys { 95 compatible = "regulator-fixed"; 96 regulator-name = "ppvar_sys"; 97 regulator-always-on; 98 regulator-boot-on; 99 }; 100 101 usb_vbus: regulator-5v0-usb-vbus { 102 compatible = "regulator-fixed"; 103 regulator-name = "usb-vbus"; 104 regulator-min-microvolt = <5000000>; 105 regulator-max-microvolt = <5000000>; 106 enable-active-high; 107 regulator-always-on; 108 }; 109 110 reserved_memory: reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 scp_mem: memory@50000000 { 116 compatible = "shared-dma-pool"; 117 reg = <0 0x50000000 0 0x2900000>; 118 no-map; 119 }; 120 }; 121}; 122 123&dp_intf0 { 124 status = "okay"; 125 126 port { 127 dp_intf0_out: endpoint { 128 }; 129 }; 130}; 131 132&dp_intf1 { 133 status = "okay"; 134 135 port { 136 dp_intf1_out: endpoint { 137 }; 138 }; 139}; 140 141&i2c0 { 142 status = "okay"; 143 144 clock-frequency = <400000>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&i2c0_pins>; 147}; 148 149&i2c1 { 150 status = "okay"; 151 152 clock-frequency = <400000>; 153 i2c-scl-internal-delay-ns = <12500>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&i2c1_pins>; 156 157 trackpad@15 { 158 compatible = "elan,ekth3000"; 159 reg = <0x15>; 160 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&trackpad_pins>; 163 vcc-supply = <&pp3300_s3>; 164 wakeup-source; 165 }; 166}; 167 168&i2c2 { 169 status = "okay"; 170 171 clock-frequency = <400000>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&i2c2_pins>; 174}; 175 176&i2c3 { 177 status = "okay"; 178 179 clock-frequency = <400000>; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&i2c3_pins>; 182 183 tpm@50 { 184 compatible = "google,cr50"; 185 reg = <0x50>; 186 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&cr50_int>; 189 }; 190}; 191 192&i2c4 { 193 status = "okay"; 194 195 clock-frequency = <400000>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&i2c4_pins>; 198 199 ts_10: touchscreen@10 { 200 compatible = "hid-over-i2c"; 201 reg = <0x10>; 202 hid-descr-addr = <0x0001>; 203 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&touchscreen_pins>; 206 post-power-on-delay-ms = <10>; 207 vdd-supply = <&pp3300_s3>; 208 status = "disabled"; 209 }; 210}; 211 212&i2c5 { 213 status = "okay"; 214 215 clock-frequency = <400000>; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&i2c5_pins>; 218}; 219 220&i2c7 { 221 status = "okay"; 222 223 clock-frequency = <400000>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&i2c7_pins>; 226 227 pmic@34 { 228 #interrupt-cells = <1>; 229 compatible = "mediatek,mt6360"; 230 reg = <0x34>; 231 interrupt-controller; 232 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 233 interrupt-names = "IRQB"; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&subpmic_default>; 236 wakeup-source; 237 }; 238}; 239 240&mmc0 { 241 status = "okay"; 242 243 bus-width = <8>; 244 cap-mmc-highspeed; 245 cap-mmc-hw-reset; 246 hs400-ds-delay = <0x14c11>; 247 max-frequency = <200000000>; 248 mmc-hs200-1_8v; 249 mmc-hs400-1_8v; 250 no-sdio; 251 no-sd; 252 non-removable; 253 pinctrl-names = "default", "state_uhs"; 254 pinctrl-0 = <&mmc0_pins_default>; 255 pinctrl-1 = <&mmc0_pins_uhs>; 256 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 257 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 258}; 259 260&mmc1 { 261 status = "okay"; 262 263 bus-width = <4>; 264 cap-sd-highspeed; 265 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 266 max-frequency = <200000000>; 267 no-mmc; 268 no-sdio; 269 pinctrl-names = "default", "state_uhs"; 270 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 271 pinctrl-1 = <&mmc1_pins_default>; 272 sd-uhs-sdr50; 273 sd-uhs-sdr104; 274 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 275 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 276}; 277 278/* for CPU-L */ 279&mt6359_vcore_buck_reg { 280 regulator-always-on; 281}; 282 283/* for CORE */ 284&mt6359_vgpu11_buck_reg { 285 regulator-always-on; 286}; 287 288&mt6359_vgpu11_sshub_buck_reg { 289 regulator-always-on; 290 regulator-min-microvolt = <550000>; 291 regulator-max-microvolt = <550000>; 292}; 293 294/* for CORE SRAM */ 295&mt6359_vpu_buck_reg { 296 regulator-always-on; 297}; 298 299&mt6359_vrf12_ldo_reg { 300 regulator-always-on; 301}; 302 303/* for GPU SRAM */ 304&mt6359_vsram_others_ldo_reg { 305 regulator-always-on; 306 regulator-min-microvolt = <750000>; 307 regulator-max-microvolt = <750000>; 308}; 309 310&mt6359_vufs_ldo_reg { 311 regulator-always-on; 312}; 313 314&nor_flash { 315 status = "okay"; 316 317 pinctrl-names = "default"; 318 pinctrl-0 = <&nor_pins_default>; 319 320 flash@0 { 321 compatible = "jedec,spi-nor"; 322 reg = <0>; 323 spi-max-frequency = <52000000>; 324 spi-rx-bus-width = <2>; 325 spi-tx-bus-width = <2>; 326 }; 327}; 328 329&pio { 330 mediatek,rsel-resistance-in-si-unit; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&pio_default>; 333 334 /* 144 lines */ 335 gpio-line-names = 336 "I2S_SPKR_MCLK", 337 "I2S_SPKR_DATAIN", 338 "I2S_SPKR_LRCK", 339 "I2S_SPKR_BCLK", 340 "EC_AP_INT_ODL", 341 /* 342 * AP_FLASH_WP_L is crossystem ABI. Schematics 343 * call it AP_FLASH_WP_ODL. 344 */ 345 "AP_FLASH_WP_L", 346 "TCHPAD_INT_ODL", 347 "EDP_HPD_1V8", 348 "AP_I2C_CAM_SDA", 349 "AP_I2C_CAM_SCL", 350 "AP_I2C_TCHPAD_SDA_1V8", 351 "AP_I2C_TCHPAD_SCL_1V8", 352 "AP_I2C_AUD_SDA", 353 "AP_I2C_AUD_SCL", 354 "AP_I2C_TPM_SDA_1V8", 355 "AP_I2C_TPM_SCL_1V8", 356 "AP_I2C_TCHSCR_SDA_1V8", 357 "AP_I2C_TCHSCR_SCL_1V8", 358 "EC_AP_HPD_OD", 359 "", 360 "PCIE_NVME_RST_L", 361 "PCIE_NVME_CLKREQ_ODL", 362 "PCIE_RST_1V8_L", 363 "PCIE_CLKREQ_1V8_ODL", 364 "PCIE_WAKE_1V8_ODL", 365 "CLK_24M_CAM0", 366 "CAM1_SEN_EN", 367 "AP_I2C_PWR_SCL_1V8", 368 "AP_I2C_PWR_SDA_1V8", 369 "AP_I2C_MISC_SCL", 370 "AP_I2C_MISC_SDA", 371 "EN_PP5000_HDMI_X", 372 "AP_HDMITX_HTPLG", 373 "", 374 "AP_HDMITX_SCL_1V8", 375 "AP_HDMITX_SDA_1V8", 376 "AP_RTC_CLK32K", 377 "AP_EC_WATCHDOG_L", 378 "SRCLKENA0", 379 "SRCLKENA1", 380 "PWRAP_SPI0_CS_L", 381 "PWRAP_SPI0_CK", 382 "PWRAP_SPI0_MOSI", 383 "PWRAP_SPI0_MISO", 384 "SPMI_SCL", 385 "SPMI_SDA", 386 "", 387 "", 388 "", 389 "I2S_HP_DATAIN", 390 "I2S_HP_MCLK", 391 "I2S_HP_BCK", 392 "I2S_HP_LRCK", 393 "I2S_HP_DATAOUT", 394 "SD_CD_ODL", 395 "EN_PP3300_DISP_X", 396 "TCHSCR_RST_1V8_L", 397 "TCHSCR_REPORT_DISABLE", 398 "EN_PP3300_WLAN_X", 399 "BT_KILL_1V8_L", 400 "I2S_SPKR_DATAOUT", 401 "WIFI_KILL_1V8_L", 402 "BEEP_ON", 403 "SCP_I2C_SENSOR_SCL_1V8", 404 "SCP_I2C_SENSOR_SDA_1V8", 405 "", 406 "", 407 "", 408 "", 409 "AUD_CLK_MOSI", 410 "AUD_SYNC_MOSI", 411 "AUD_DAT_MOSI0", 412 "AUD_DAT_MOSI1", 413 "AUD_DAT_MISO0", 414 "AUD_DAT_MISO1", 415 "AUD_DAT_MISO2", 416 "SCP_VREQ_VAO", 417 "AP_SPI_GSC_TPM_CLK", 418 "AP_SPI_GSC_TPM_MOSI", 419 "AP_SPI_GSC_TPM_CS_L", 420 "AP_SPI_GSC_TPM_MISO", 421 "EN_PP1000_CAM_X", 422 "AP_EDP_BKLTEN", 423 "", 424 "USB3_HUB_RST_L", 425 "", 426 "WLAN_ALERT_ODL", 427 "EC_IN_RW_ODL", 428 "GSC_AP_INT_ODL", 429 "HP_INT_ODL", 430 "CAM0_RST_L", 431 "CAM1_RST_L", 432 "TCHSCR_INT_1V8_L", 433 "CAM1_DET_L", 434 "RST_ALC1011_L", 435 "", 436 "", 437 "BL_PWM_1V8", 438 "UART_AP_TX_DBG_RX", 439 "UART_DBG_TX_AP_RX", 440 "EN_SPKR", 441 "AP_EC_WARM_RST_REQ", 442 "UART_SCP_TX_DBGCON_RX", 443 "UART_DBGCON_TX_SCP_RX", 444 "", 445 "", 446 "KPCOL0", 447 "", 448 "MT6315_GPU_INT", 449 "MT6315_PROC_BC_INT", 450 "SD_CMD", 451 "SD_CLK", 452 "SD_DAT0", 453 "SD_DAT1", 454 "SD_DAT2", 455 "SD_DAT3", 456 "EMMC_DAT7", 457 "EMMC_DAT6", 458 "EMMC_DAT5", 459 "EMMC_DAT4", 460 "EMMC_RSTB", 461 "EMMC_CMD", 462 "EMMC_CLK", 463 "EMMC_DAT3", 464 "EMMC_DAT2", 465 "EMMC_DAT1", 466 "EMMC_DAT0", 467 "EMMC_DSL", 468 "", 469 "", 470 "MT6360_INT_ODL", 471 "SCP_JTAG0_TRSTN", 472 "AP_SPI_EC_CS_L", 473 "AP_SPI_EC_CLK", 474 "AP_SPI_EC_MOSI", 475 "AP_SPI_EC_MISO", 476 "SCP_JTAG0_TMS", 477 "SCP_JTAG0_TCK", 478 "SCP_JTAG0_TDO", 479 "SCP_JTAG0_TDI", 480 "AP_SPI_FLASH_CS_L", 481 "AP_SPI_FLASH_CLK", 482 "AP_SPI_FLASH_MOSI", 483 "AP_SPI_FLASH_MISO"; 484 485 cr50_int: cr50-irq-default-pins { 486 pins-gsc-ap-int-odl { 487 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 488 input-enable; 489 }; 490 }; 491 492 cros_ec_int: cros-ec-irq-default-pins { 493 pins-ec-ap-int-odl { 494 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 495 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 496 input-enable; 497 }; 498 }; 499 500 i2c0_pins: i2c0-default-pins { 501 pins-bus { 502 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 503 <PINMUX_GPIO9__FUNC_SCL0>; 504 bias-disable; 505 drive-strength-microamp = <1000>; 506 }; 507 }; 508 509 i2c1_pins: i2c1-default-pins { 510 pins-bus { 511 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 512 <PINMUX_GPIO11__FUNC_SCL1>; 513 bias-pull-up = <1000>; 514 drive-strength-microamp = <1000>; 515 }; 516 }; 517 518 i2c2_pins: i2c2-default-pins { 519 pins-bus { 520 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 521 <PINMUX_GPIO13__FUNC_SCL2>; 522 bias-disable; 523 drive-strength-microamp = <1000>; 524 }; 525 }; 526 527 i2c3_pins: i2c3-default-pins { 528 pins-bus { 529 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 530 <PINMUX_GPIO15__FUNC_SCL3>; 531 bias-pull-up = <1000>; 532 drive-strength-microamp = <1000>; 533 }; 534 }; 535 536 i2c4_pins: i2c4-default-pins { 537 pins-bus { 538 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 539 <PINMUX_GPIO17__FUNC_SCL4>; 540 bias-pull-up = <1000>; 541 drive-strength = <4>; 542 }; 543 }; 544 545 i2c5_pins: i2c5-default-pins { 546 pins-bus { 547 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 548 <PINMUX_GPIO30__FUNC_SDA5>; 549 bias-disable; 550 drive-strength-microamp = <1000>; 551 }; 552 }; 553 554 i2c7_pins: i2c7-default-pins { 555 pins-bus { 556 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 557 <PINMUX_GPIO28__FUNC_SDA7>; 558 bias-disable; 559 }; 560 }; 561 562 mmc0_pins_default: mmc0-default-pins { 563 pins-cmd-dat { 564 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 565 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 566 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 567 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 568 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 569 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 570 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 571 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 572 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 573 input-enable; 574 drive-strength = <6>; 575 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 576 }; 577 578 pins-clk { 579 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 580 drive-strength = <6>; 581 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 582 }; 583 584 pins-rst { 585 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 586 drive-strength = <6>; 587 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 588 }; 589 }; 590 591 mmc0_pins_uhs: mmc0-uhs-pins { 592 pins-cmd-dat { 593 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 594 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 595 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 596 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 597 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 598 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 599 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 600 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 601 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 602 input-enable; 603 drive-strength = <8>; 604 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 605 }; 606 607 pins-clk { 608 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 609 drive-strength = <8>; 610 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 611 }; 612 613 pins-ds { 614 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 615 drive-strength = <8>; 616 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 617 }; 618 619 pins-rst { 620 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 621 drive-strength = <8>; 622 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 623 }; 624 }; 625 626 mmc1_pins_detect: mmc1-detect-pins { 627 pins-insert { 628 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 629 bias-pull-up; 630 }; 631 }; 632 633 mmc1_pins_default: mmc1-default-pins { 634 pins-cmd-dat { 635 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 636 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 637 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 638 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 639 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 640 input-enable; 641 drive-strength = <8>; 642 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 643 }; 644 645 pins-clk { 646 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 647 drive-strength = <8>; 648 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 649 }; 650 }; 651 652 nor_pins_default: nor-default-pins { 653 pins-ck-io { 654 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 655 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 656 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 657 drive-strength = <6>; 658 bias-pull-down; 659 }; 660 661 pins-cs { 662 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 663 drive-strength = <6>; 664 bias-pull-up; 665 }; 666 }; 667 668 pio_default: pio-default-pins { 669 pins-wifi-enable { 670 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 671 output-high; 672 drive-strength = <14>; 673 }; 674 675 pins-low-power-pd { 676 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 677 <PINMUX_GPIO26__FUNC_GPIO26>, 678 <PINMUX_GPIO46__FUNC_GPIO46>, 679 <PINMUX_GPIO47__FUNC_GPIO47>, 680 <PINMUX_GPIO48__FUNC_GPIO48>, 681 <PINMUX_GPIO65__FUNC_GPIO65>, 682 <PINMUX_GPIO66__FUNC_GPIO66>, 683 <PINMUX_GPIO67__FUNC_GPIO67>, 684 <PINMUX_GPIO68__FUNC_GPIO68>, 685 <PINMUX_GPIO128__FUNC_GPIO128>, 686 <PINMUX_GPIO129__FUNC_GPIO129>; 687 input-enable; 688 bias-pull-down; 689 }; 690 691 pins-low-power-pupd { 692 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 693 <PINMUX_GPIO78__FUNC_GPIO78>, 694 <PINMUX_GPIO79__FUNC_GPIO79>, 695 <PINMUX_GPIO80__FUNC_GPIO80>, 696 <PINMUX_GPIO83__FUNC_GPIO83>, 697 <PINMUX_GPIO85__FUNC_GPIO85>, 698 <PINMUX_GPIO90__FUNC_GPIO90>, 699 <PINMUX_GPIO91__FUNC_GPIO91>, 700 <PINMUX_GPIO93__FUNC_GPIO93>, 701 <PINMUX_GPIO94__FUNC_GPIO94>, 702 <PINMUX_GPIO95__FUNC_GPIO95>, 703 <PINMUX_GPIO96__FUNC_GPIO96>, 704 <PINMUX_GPIO104__FUNC_GPIO104>, 705 <PINMUX_GPIO105__FUNC_GPIO105>, 706 <PINMUX_GPIO107__FUNC_GPIO107>; 707 input-enable; 708 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 709 }; 710 }; 711 712 scp_pins: scp-default-pins { 713 pins-vreq { 714 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 715 bias-disable; 716 input-enable; 717 }; 718 }; 719 720 spi0_pins: spi0-default-pins { 721 pins-cs-mosi-clk { 722 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 723 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 724 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 725 bias-disable; 726 }; 727 728 pins-miso { 729 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 730 bias-pull-down; 731 }; 732 }; 733 734 subpmic_default: subpmic-default-pins { 735 subpmic_pin_irq: pins-subpmic-int-n { 736 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 737 input-enable; 738 bias-pull-up; 739 }; 740 }; 741 742 trackpad_pins: trackpad-default-pins { 743 pins-int-n { 744 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 745 input-enable; 746 bias-pull-up; 747 }; 748 }; 749 750 touchscreen_pins: touchscreen-default-pins { 751 pins-int-n { 752 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 753 input-enable; 754 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 755 }; 756 pins-rst { 757 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 758 output-high; 759 }; 760 pins-report-sw { 761 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 762 output-low; 763 }; 764 }; 765}; 766 767&pmic { 768 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 769}; 770 771&scp { 772 status = "okay"; 773 774 firmware-name = "mediatek/mt8195/scp.img"; 775 memory-region = <&scp_mem>; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&scp_pins>; 778 779 cros-ec-rpmsg { 780 compatible = "google,cros-ec-rpmsg"; 781 mediatek,rpmsg-name = "cros-ec-rpmsg"; 782 }; 783}; 784 785&spi0 { 786 status = "okay"; 787 788 pinctrl-names = "default"; 789 pinctrl-0 = <&spi0_pins>; 790 mediatek,pad-select = <0>; 791 792 cros_ec: ec@0 { 793 #address-cells = <1>; 794 #size-cells = <0>; 795 796 compatible = "google,cros-ec-spi"; 797 reg = <0>; 798 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&cros_ec_int>; 801 spi-max-frequency = <3000000>; 802 803 keyboard-backlight { 804 compatible = "google,cros-kbd-led-backlight"; 805 }; 806 807 i2c_tunnel: i2c-tunnel { 808 compatible = "google,cros-ec-i2c-tunnel"; 809 google,remote-bus = <0>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 }; 813 814 mt_pmic_vmc_ldo_reg: regulator@0 { 815 compatible = "google,cros-ec-regulator"; 816 reg = <0>; 817 regulator-name = "mt_pmic_vmc_ldo"; 818 regulator-min-microvolt = <1200000>; 819 regulator-max-microvolt = <3600000>; 820 }; 821 822 mt_pmic_vmch_ldo_reg: regulator@1 { 823 compatible = "google,cros-ec-regulator"; 824 reg = <1>; 825 regulator-name = "mt_pmic_vmch_ldo"; 826 regulator-min-microvolt = <2700000>; 827 regulator-max-microvolt = <3600000>; 828 }; 829 830 typec { 831 compatible = "google,cros-ec-typec"; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 835 usb_c0: connector@0 { 836 compatible = "usb-c-connector"; 837 reg = <0>; 838 power-role = "dual"; 839 data-role = "host"; 840 try-power-role = "source"; 841 }; 842 843 usb_c1: connector@1 { 844 compatible = "usb-c-connector"; 845 reg = <1>; 846 power-role = "dual"; 847 data-role = "host"; 848 try-power-role = "source"; 849 }; 850 }; 851 }; 852}; 853 854&spmi { 855 #address-cells = <2>; 856 #size-cells = <0>; 857 858 mt6315@6 { 859 compatible = "mediatek,mt6315-regulator"; 860 reg = <0x6 SPMI_USID>; 861 862 regulators { 863 mt6315_6_vbuck1: vbuck1 { 864 regulator-compatible = "vbuck1"; 865 regulator-name = "Vbcpu"; 866 regulator-min-microvolt = <300000>; 867 regulator-max-microvolt = <1193750>; 868 regulator-enable-ramp-delay = <256>; 869 regulator-ramp-delay = <6250>; 870 regulator-allowed-modes = <0 1 2>; 871 regulator-always-on; 872 }; 873 }; 874 }; 875 876 mt6315@7 { 877 compatible = "mediatek,mt6315-regulator"; 878 reg = <0x7 SPMI_USID>; 879 880 regulators { 881 mt6315_7_vbuck1: vbuck1 { 882 regulator-compatible = "vbuck1"; 883 regulator-name = "Vgpu"; 884 regulator-min-microvolt = <625000>; 885 regulator-max-microvolt = <1193750>; 886 regulator-enable-ramp-delay = <256>; 887 regulator-ramp-delay = <6250>; 888 regulator-allowed-modes = <0 1 2>; 889 regulator-always-on; 890 }; 891 }; 892 }; 893}; 894 895&u3phy0 { 896 status = "okay"; 897}; 898 899&u3phy1 { 900 status = "okay"; 901}; 902 903&u3phy2 { 904 status = "okay"; 905}; 906 907&u3phy3 { 908 status = "okay"; 909}; 910 911&uart0 { 912 status = "okay"; 913}; 914 915&xhci0 { 916 status = "okay"; 917 918 vusb33-supply = <&mt6359_vusb_ldo_reg>; 919 vbus-supply = <&usb_vbus>; 920}; 921 922&xhci1 { 923 status = "okay"; 924 925 vusb33-supply = <&mt6359_vusb_ldo_reg>; 926 vbus-supply = <&usb_vbus>; 927}; 928 929&xhci2 { 930 status = "okay"; 931 932 vusb33-supply = <&mt6359_vusb_ldo_reg>; 933 vbus-supply = <&usb_vbus>; 934}; 935 936&xhci3 { 937 status = "okay"; 938 939 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 940 usb2-lpm-disable; 941 vusb33-supply = <&mt6359_vusb_ldo_reg>; 942 vbus-supply = <&usb_vbus>; 943}; 944 945#include <arm/cros-ec-keyboard.dtsi> 946#include <arm/cros-ec-sbs.dtsi> 947 948&keyboard_controller { 949 function-row-physmap = < 950 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 951 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 952 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 953 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 954 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 955 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 956 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 957 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 958 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 959 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 960 >; 961 962 linux,keymap = < 963 MATRIX_KEY(0x00, 0x02, KEY_BACK) 964 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 965 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 966 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 967 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 968 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 969 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 970 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 971 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 972 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 973 974 CROS_STD_MAIN_KEYMAP 975 >; 976}; 977