1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 reg = <0 0x40000000 0 0x80000000>; 32 }; 33 34 /* system wide LDO 3.3V power rail */ 35 pp3300_z5: regulator-pp3300-ldo-z5 { 36 compatible = "regulator-fixed"; 37 regulator-name = "pp3300_ldo_z5"; 38 regulator-always-on; 39 regulator-boot-on; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 vin-supply = <&ppvar_sys>; 43 }; 44 45 /* separately switched 3.3V power rail */ 46 pp3300_s3: regulator-pp3300-s3 { 47 compatible = "regulator-fixed"; 48 regulator-name = "pp3300_s3"; 49 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 50 regulator-always-on; 51 regulator-boot-on; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 vin-supply = <&pp3300_z2>; 55 }; 56 57 /* system wide 3.3V power rail */ 58 pp3300_z2: regulator-pp3300-z2 { 59 compatible = "regulator-fixed"; 60 regulator-name = "pp3300_z2"; 61 /* EN pin tied to pp4200_z2, which is controlled by EC */ 62 regulator-always-on; 63 regulator-boot-on; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 vin-supply = <&ppvar_sys>; 67 }; 68 69 /* system wide 4.2V power rail */ 70 pp4200_z2: regulator-pp4200-z2 { 71 compatible = "regulator-fixed"; 72 regulator-name = "pp4200_z2"; 73 /* controlled by EC */ 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <4200000>; 77 regulator-max-microvolt = <4200000>; 78 vin-supply = <&ppvar_sys>; 79 }; 80 81 /* system wide switching 5.0V power rail */ 82 pp5000_s5: regulator-pp5000-s5 { 83 compatible = "regulator-fixed"; 84 regulator-name = "pp5000_s5"; 85 /* controlled by EC */ 86 regulator-always-on; 87 regulator-boot-on; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 vin-supply = <&ppvar_sys>; 91 }; 92 93 /* system wide semi-regulated power rail from battery or USB */ 94 ppvar_sys: regulator-ppvar-sys { 95 compatible = "regulator-fixed"; 96 regulator-name = "ppvar_sys"; 97 regulator-always-on; 98 regulator-boot-on; 99 }; 100 101 usb_vbus: regulator-5v0-usb-vbus { 102 compatible = "regulator-fixed"; 103 regulator-name = "usb-vbus"; 104 regulator-min-microvolt = <5000000>; 105 regulator-max-microvolt = <5000000>; 106 enable-active-high; 107 regulator-always-on; 108 }; 109 110 reserved_memory: reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 scp_mem: memory@50000000 { 116 compatible = "shared-dma-pool"; 117 reg = <0 0x50000000 0 0x2900000>; 118 no-map; 119 }; 120 }; 121}; 122 123&dp_intf0 { 124 status = "okay"; 125 126 port { 127 dp_intf0_out: endpoint { 128 remote-endpoint = <&edp_in>; 129 }; 130 }; 131}; 132 133&dp_intf1 { 134 status = "okay"; 135 136 port { 137 dp_intf1_out: endpoint { 138 remote-endpoint = <&dptx_in>; 139 }; 140 }; 141}; 142 143&edp_tx { 144 status = "okay"; 145 146 pinctrl-names = "default"; 147 pinctrl-0 = <&edptx_pins_default>; 148 149 ports { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 port@0 { 154 reg = <0>; 155 edp_in: endpoint { 156 remote-endpoint = <&dp_intf0_out>; 157 }; 158 }; 159 160 port@1 { 161 reg = <1>; 162 edp_out: endpoint { 163 data-lanes = <0 1 2 3>; 164 }; 165 }; 166 }; 167}; 168 169&dp_tx { 170 status = "okay"; 171 172 pinctrl-names = "default"; 173 pinctrl-0 = <&dptx_pin>; 174 175 ports { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 179 port@0 { 180 reg = <0>; 181 dptx_in: endpoint { 182 remote-endpoint = <&dp_intf1_out>; 183 }; 184 }; 185 186 port@1 { 187 reg = <1>; 188 dptx_out: endpoint { 189 data-lanes = <0 1 2 3>; 190 }; 191 }; 192 }; 193}; 194 195&i2c0 { 196 status = "okay"; 197 198 clock-frequency = <400000>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&i2c0_pins>; 201}; 202 203&i2c1 { 204 status = "okay"; 205 206 clock-frequency = <400000>; 207 i2c-scl-internal-delay-ns = <12500>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&i2c1_pins>; 210 211 trackpad@15 { 212 compatible = "elan,ekth3000"; 213 reg = <0x15>; 214 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&trackpad_pins>; 217 vcc-supply = <&pp3300_s3>; 218 wakeup-source; 219 }; 220}; 221 222&i2c2 { 223 status = "okay"; 224 225 clock-frequency = <400000>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&i2c2_pins>; 228}; 229 230&i2c3 { 231 status = "okay"; 232 233 clock-frequency = <400000>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&i2c3_pins>; 236 237 tpm@50 { 238 compatible = "google,cr50"; 239 reg = <0x50>; 240 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&cr50_int>; 243 }; 244}; 245 246&i2c4 { 247 status = "okay"; 248 249 clock-frequency = <400000>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&i2c4_pins>; 252 253 ts_10: touchscreen@10 { 254 compatible = "hid-over-i2c"; 255 reg = <0x10>; 256 hid-descr-addr = <0x0001>; 257 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&touchscreen_pins>; 260 post-power-on-delay-ms = <10>; 261 vdd-supply = <&pp3300_s3>; 262 status = "disabled"; 263 }; 264}; 265 266&i2c5 { 267 status = "okay"; 268 269 clock-frequency = <400000>; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&i2c5_pins>; 272}; 273 274&i2c7 { 275 status = "okay"; 276 277 clock-frequency = <400000>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&i2c7_pins>; 280 281 pmic@34 { 282 #interrupt-cells = <1>; 283 compatible = "mediatek,mt6360"; 284 reg = <0x34>; 285 interrupt-controller; 286 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 287 interrupt-names = "IRQB"; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&subpmic_default>; 290 wakeup-source; 291 }; 292}; 293 294&mmc0 { 295 status = "okay"; 296 297 bus-width = <8>; 298 cap-mmc-highspeed; 299 cap-mmc-hw-reset; 300 hs400-ds-delay = <0x14c11>; 301 max-frequency = <200000000>; 302 mmc-hs200-1_8v; 303 mmc-hs400-1_8v; 304 no-sdio; 305 no-sd; 306 non-removable; 307 pinctrl-names = "default", "state_uhs"; 308 pinctrl-0 = <&mmc0_pins_default>; 309 pinctrl-1 = <&mmc0_pins_uhs>; 310 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 311 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 312}; 313 314&mmc1 { 315 status = "okay"; 316 317 bus-width = <4>; 318 cap-sd-highspeed; 319 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 320 max-frequency = <200000000>; 321 no-mmc; 322 no-sdio; 323 pinctrl-names = "default", "state_uhs"; 324 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 325 pinctrl-1 = <&mmc1_pins_default>; 326 sd-uhs-sdr50; 327 sd-uhs-sdr104; 328 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 329 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 330}; 331 332/* for CPU-L */ 333&mt6359_vcore_buck_reg { 334 regulator-always-on; 335}; 336 337/* for CORE */ 338&mt6359_vgpu11_buck_reg { 339 regulator-always-on; 340}; 341 342&mt6359_vgpu11_sshub_buck_reg { 343 regulator-always-on; 344 regulator-min-microvolt = <550000>; 345 regulator-max-microvolt = <550000>; 346}; 347 348/* for CORE SRAM */ 349&mt6359_vpu_buck_reg { 350 regulator-always-on; 351}; 352 353&mt6359_vrf12_ldo_reg { 354 regulator-always-on; 355}; 356 357/* for GPU SRAM */ 358&mt6359_vsram_others_ldo_reg { 359 regulator-always-on; 360 regulator-min-microvolt = <750000>; 361 regulator-max-microvolt = <750000>; 362}; 363 364&mt6359_vufs_ldo_reg { 365 regulator-always-on; 366}; 367 368&nor_flash { 369 status = "okay"; 370 371 pinctrl-names = "default"; 372 pinctrl-0 = <&nor_pins_default>; 373 374 flash@0 { 375 compatible = "jedec,spi-nor"; 376 reg = <0>; 377 spi-max-frequency = <52000000>; 378 spi-rx-bus-width = <2>; 379 spi-tx-bus-width = <2>; 380 }; 381}; 382 383&pio { 384 mediatek,rsel-resistance-in-si-unit; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pio_default>; 387 388 /* 144 lines */ 389 gpio-line-names = 390 "I2S_SPKR_MCLK", 391 "I2S_SPKR_DATAIN", 392 "I2S_SPKR_LRCK", 393 "I2S_SPKR_BCLK", 394 "EC_AP_INT_ODL", 395 /* 396 * AP_FLASH_WP_L is crossystem ABI. Schematics 397 * call it AP_FLASH_WP_ODL. 398 */ 399 "AP_FLASH_WP_L", 400 "TCHPAD_INT_ODL", 401 "EDP_HPD_1V8", 402 "AP_I2C_CAM_SDA", 403 "AP_I2C_CAM_SCL", 404 "AP_I2C_TCHPAD_SDA_1V8", 405 "AP_I2C_TCHPAD_SCL_1V8", 406 "AP_I2C_AUD_SDA", 407 "AP_I2C_AUD_SCL", 408 "AP_I2C_TPM_SDA_1V8", 409 "AP_I2C_TPM_SCL_1V8", 410 "AP_I2C_TCHSCR_SDA_1V8", 411 "AP_I2C_TCHSCR_SCL_1V8", 412 "EC_AP_HPD_OD", 413 "", 414 "PCIE_NVME_RST_L", 415 "PCIE_NVME_CLKREQ_ODL", 416 "PCIE_RST_1V8_L", 417 "PCIE_CLKREQ_1V8_ODL", 418 "PCIE_WAKE_1V8_ODL", 419 "CLK_24M_CAM0", 420 "CAM1_SEN_EN", 421 "AP_I2C_PWR_SCL_1V8", 422 "AP_I2C_PWR_SDA_1V8", 423 "AP_I2C_MISC_SCL", 424 "AP_I2C_MISC_SDA", 425 "EN_PP5000_HDMI_X", 426 "AP_HDMITX_HTPLG", 427 "", 428 "AP_HDMITX_SCL_1V8", 429 "AP_HDMITX_SDA_1V8", 430 "AP_RTC_CLK32K", 431 "AP_EC_WATCHDOG_L", 432 "SRCLKENA0", 433 "SRCLKENA1", 434 "PWRAP_SPI0_CS_L", 435 "PWRAP_SPI0_CK", 436 "PWRAP_SPI0_MOSI", 437 "PWRAP_SPI0_MISO", 438 "SPMI_SCL", 439 "SPMI_SDA", 440 "", 441 "", 442 "", 443 "I2S_HP_DATAIN", 444 "I2S_HP_MCLK", 445 "I2S_HP_BCK", 446 "I2S_HP_LRCK", 447 "I2S_HP_DATAOUT", 448 "SD_CD_ODL", 449 "EN_PP3300_DISP_X", 450 "TCHSCR_RST_1V8_L", 451 "TCHSCR_REPORT_DISABLE", 452 "EN_PP3300_WLAN_X", 453 "BT_KILL_1V8_L", 454 "I2S_SPKR_DATAOUT", 455 "WIFI_KILL_1V8_L", 456 "BEEP_ON", 457 "SCP_I2C_SENSOR_SCL_1V8", 458 "SCP_I2C_SENSOR_SDA_1V8", 459 "", 460 "", 461 "", 462 "", 463 "AUD_CLK_MOSI", 464 "AUD_SYNC_MOSI", 465 "AUD_DAT_MOSI0", 466 "AUD_DAT_MOSI1", 467 "AUD_DAT_MISO0", 468 "AUD_DAT_MISO1", 469 "AUD_DAT_MISO2", 470 "SCP_VREQ_VAO", 471 "AP_SPI_GSC_TPM_CLK", 472 "AP_SPI_GSC_TPM_MOSI", 473 "AP_SPI_GSC_TPM_CS_L", 474 "AP_SPI_GSC_TPM_MISO", 475 "EN_PP1000_CAM_X", 476 "AP_EDP_BKLTEN", 477 "", 478 "USB3_HUB_RST_L", 479 "", 480 "WLAN_ALERT_ODL", 481 "EC_IN_RW_ODL", 482 "GSC_AP_INT_ODL", 483 "HP_INT_ODL", 484 "CAM0_RST_L", 485 "CAM1_RST_L", 486 "TCHSCR_INT_1V8_L", 487 "CAM1_DET_L", 488 "RST_ALC1011_L", 489 "", 490 "", 491 "BL_PWM_1V8", 492 "UART_AP_TX_DBG_RX", 493 "UART_DBG_TX_AP_RX", 494 "EN_SPKR", 495 "AP_EC_WARM_RST_REQ", 496 "UART_SCP_TX_DBGCON_RX", 497 "UART_DBGCON_TX_SCP_RX", 498 "", 499 "", 500 "KPCOL0", 501 "", 502 "MT6315_GPU_INT", 503 "MT6315_PROC_BC_INT", 504 "SD_CMD", 505 "SD_CLK", 506 "SD_DAT0", 507 "SD_DAT1", 508 "SD_DAT2", 509 "SD_DAT3", 510 "EMMC_DAT7", 511 "EMMC_DAT6", 512 "EMMC_DAT5", 513 "EMMC_DAT4", 514 "EMMC_RSTB", 515 "EMMC_CMD", 516 "EMMC_CLK", 517 "EMMC_DAT3", 518 "EMMC_DAT2", 519 "EMMC_DAT1", 520 "EMMC_DAT0", 521 "EMMC_DSL", 522 "", 523 "", 524 "MT6360_INT_ODL", 525 "SCP_JTAG0_TRSTN", 526 "AP_SPI_EC_CS_L", 527 "AP_SPI_EC_CLK", 528 "AP_SPI_EC_MOSI", 529 "AP_SPI_EC_MISO", 530 "SCP_JTAG0_TMS", 531 "SCP_JTAG0_TCK", 532 "SCP_JTAG0_TDO", 533 "SCP_JTAG0_TDI", 534 "AP_SPI_FLASH_CS_L", 535 "AP_SPI_FLASH_CLK", 536 "AP_SPI_FLASH_MOSI", 537 "AP_SPI_FLASH_MISO"; 538 539 cr50_int: cr50-irq-default-pins { 540 pins-gsc-ap-int-odl { 541 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 542 input-enable; 543 }; 544 }; 545 546 cros_ec_int: cros-ec-irq-default-pins { 547 pins-ec-ap-int-odl { 548 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 549 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 550 input-enable; 551 }; 552 }; 553 554 edptx_pins_default: edptx-default-pins { 555 pins-cmd-dat { 556 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 557 bias-pull-up; 558 }; 559 }; 560 561 dptx_pin: dptx-default-pins { 562 pins-cmd-dat { 563 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 564 bias-pull-up; 565 }; 566 }; 567 568 i2c0_pins: i2c0-default-pins { 569 pins-bus { 570 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 571 <PINMUX_GPIO9__FUNC_SCL0>; 572 bias-disable; 573 drive-strength-microamp = <1000>; 574 }; 575 }; 576 577 i2c1_pins: i2c1-default-pins { 578 pins-bus { 579 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 580 <PINMUX_GPIO11__FUNC_SCL1>; 581 bias-pull-up = <1000>; 582 drive-strength-microamp = <1000>; 583 }; 584 }; 585 586 i2c2_pins: i2c2-default-pins { 587 pins-bus { 588 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 589 <PINMUX_GPIO13__FUNC_SCL2>; 590 bias-disable; 591 drive-strength-microamp = <1000>; 592 }; 593 }; 594 595 i2c3_pins: i2c3-default-pins { 596 pins-bus { 597 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 598 <PINMUX_GPIO15__FUNC_SCL3>; 599 bias-pull-up = <1000>; 600 drive-strength-microamp = <1000>; 601 }; 602 }; 603 604 i2c4_pins: i2c4-default-pins { 605 pins-bus { 606 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 607 <PINMUX_GPIO17__FUNC_SCL4>; 608 bias-pull-up = <1000>; 609 drive-strength = <4>; 610 }; 611 }; 612 613 i2c5_pins: i2c5-default-pins { 614 pins-bus { 615 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 616 <PINMUX_GPIO30__FUNC_SDA5>; 617 bias-disable; 618 drive-strength-microamp = <1000>; 619 }; 620 }; 621 622 i2c7_pins: i2c7-default-pins { 623 pins-bus { 624 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 625 <PINMUX_GPIO28__FUNC_SDA7>; 626 bias-disable; 627 }; 628 }; 629 630 mmc0_pins_default: mmc0-default-pins { 631 pins-cmd-dat { 632 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 633 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 634 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 635 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 636 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 637 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 638 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 639 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 640 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 641 input-enable; 642 drive-strength = <6>; 643 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 644 }; 645 646 pins-clk { 647 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 648 drive-strength = <6>; 649 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 650 }; 651 652 pins-rst { 653 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 654 drive-strength = <6>; 655 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 656 }; 657 }; 658 659 mmc0_pins_uhs: mmc0-uhs-pins { 660 pins-cmd-dat { 661 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 662 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 663 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 664 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 665 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 666 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 667 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 668 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 669 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 670 input-enable; 671 drive-strength = <8>; 672 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 673 }; 674 675 pins-clk { 676 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 677 drive-strength = <8>; 678 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 679 }; 680 681 pins-ds { 682 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 683 drive-strength = <8>; 684 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 685 }; 686 687 pins-rst { 688 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 689 drive-strength = <8>; 690 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 691 }; 692 }; 693 694 mmc1_pins_detect: mmc1-detect-pins { 695 pins-insert { 696 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 697 bias-pull-up; 698 }; 699 }; 700 701 mmc1_pins_default: mmc1-default-pins { 702 pins-cmd-dat { 703 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 704 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 705 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 706 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 707 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 708 input-enable; 709 drive-strength = <8>; 710 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 711 }; 712 713 pins-clk { 714 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 715 drive-strength = <8>; 716 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 717 }; 718 }; 719 720 nor_pins_default: nor-default-pins { 721 pins-ck-io { 722 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 723 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 724 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 725 drive-strength = <6>; 726 bias-pull-down; 727 }; 728 729 pins-cs { 730 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 731 drive-strength = <6>; 732 bias-pull-up; 733 }; 734 }; 735 736 pio_default: pio-default-pins { 737 pins-wifi-enable { 738 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 739 output-high; 740 drive-strength = <14>; 741 }; 742 743 pins-low-power-pd { 744 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 745 <PINMUX_GPIO26__FUNC_GPIO26>, 746 <PINMUX_GPIO46__FUNC_GPIO46>, 747 <PINMUX_GPIO47__FUNC_GPIO47>, 748 <PINMUX_GPIO48__FUNC_GPIO48>, 749 <PINMUX_GPIO65__FUNC_GPIO65>, 750 <PINMUX_GPIO66__FUNC_GPIO66>, 751 <PINMUX_GPIO67__FUNC_GPIO67>, 752 <PINMUX_GPIO68__FUNC_GPIO68>, 753 <PINMUX_GPIO128__FUNC_GPIO128>, 754 <PINMUX_GPIO129__FUNC_GPIO129>; 755 input-enable; 756 bias-pull-down; 757 }; 758 759 pins-low-power-pupd { 760 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 761 <PINMUX_GPIO78__FUNC_GPIO78>, 762 <PINMUX_GPIO79__FUNC_GPIO79>, 763 <PINMUX_GPIO80__FUNC_GPIO80>, 764 <PINMUX_GPIO83__FUNC_GPIO83>, 765 <PINMUX_GPIO85__FUNC_GPIO85>, 766 <PINMUX_GPIO90__FUNC_GPIO90>, 767 <PINMUX_GPIO91__FUNC_GPIO91>, 768 <PINMUX_GPIO93__FUNC_GPIO93>, 769 <PINMUX_GPIO94__FUNC_GPIO94>, 770 <PINMUX_GPIO95__FUNC_GPIO95>, 771 <PINMUX_GPIO96__FUNC_GPIO96>, 772 <PINMUX_GPIO104__FUNC_GPIO104>, 773 <PINMUX_GPIO105__FUNC_GPIO105>, 774 <PINMUX_GPIO107__FUNC_GPIO107>; 775 input-enable; 776 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 777 }; 778 }; 779 780 scp_pins: scp-default-pins { 781 pins-vreq { 782 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 783 bias-disable; 784 input-enable; 785 }; 786 }; 787 788 spi0_pins: spi0-default-pins { 789 pins-cs-mosi-clk { 790 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 791 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 792 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 793 bias-disable; 794 }; 795 796 pins-miso { 797 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 798 bias-pull-down; 799 }; 800 }; 801 802 subpmic_default: subpmic-default-pins { 803 subpmic_pin_irq: pins-subpmic-int-n { 804 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 805 input-enable; 806 bias-pull-up; 807 }; 808 }; 809 810 trackpad_pins: trackpad-default-pins { 811 pins-int-n { 812 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 813 input-enable; 814 bias-pull-up; 815 }; 816 }; 817 818 touchscreen_pins: touchscreen-default-pins { 819 pins-int-n { 820 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 821 input-enable; 822 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 823 }; 824 pins-rst { 825 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 826 output-high; 827 }; 828 pins-report-sw { 829 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 830 output-low; 831 }; 832 }; 833}; 834 835&pmic { 836 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 837}; 838 839&scp { 840 status = "okay"; 841 842 firmware-name = "mediatek/mt8195/scp.img"; 843 memory-region = <&scp_mem>; 844 pinctrl-names = "default"; 845 pinctrl-0 = <&scp_pins>; 846 847 cros-ec-rpmsg { 848 compatible = "google,cros-ec-rpmsg"; 849 mediatek,rpmsg-name = "cros-ec-rpmsg"; 850 }; 851}; 852 853&spi0 { 854 status = "okay"; 855 856 pinctrl-names = "default"; 857 pinctrl-0 = <&spi0_pins>; 858 mediatek,pad-select = <0>; 859 860 cros_ec: ec@0 { 861 #address-cells = <1>; 862 #size-cells = <0>; 863 864 compatible = "google,cros-ec-spi"; 865 reg = <0>; 866 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&cros_ec_int>; 869 spi-max-frequency = <3000000>; 870 871 keyboard-backlight { 872 compatible = "google,cros-kbd-led-backlight"; 873 }; 874 875 i2c_tunnel: i2c-tunnel { 876 compatible = "google,cros-ec-i2c-tunnel"; 877 google,remote-bus = <0>; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 }; 881 882 mt_pmic_vmc_ldo_reg: regulator@0 { 883 compatible = "google,cros-ec-regulator"; 884 reg = <0>; 885 regulator-name = "mt_pmic_vmc_ldo"; 886 regulator-min-microvolt = <1200000>; 887 regulator-max-microvolt = <3600000>; 888 }; 889 890 mt_pmic_vmch_ldo_reg: regulator@1 { 891 compatible = "google,cros-ec-regulator"; 892 reg = <1>; 893 regulator-name = "mt_pmic_vmch_ldo"; 894 regulator-min-microvolt = <2700000>; 895 regulator-max-microvolt = <3600000>; 896 }; 897 898 typec { 899 compatible = "google,cros-ec-typec"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 903 usb_c0: connector@0 { 904 compatible = "usb-c-connector"; 905 reg = <0>; 906 power-role = "dual"; 907 data-role = "host"; 908 try-power-role = "source"; 909 }; 910 911 usb_c1: connector@1 { 912 compatible = "usb-c-connector"; 913 reg = <1>; 914 power-role = "dual"; 915 data-role = "host"; 916 try-power-role = "source"; 917 }; 918 }; 919 }; 920}; 921 922&spmi { 923 #address-cells = <2>; 924 #size-cells = <0>; 925 926 mt6315@6 { 927 compatible = "mediatek,mt6315-regulator"; 928 reg = <0x6 SPMI_USID>; 929 930 regulators { 931 mt6315_6_vbuck1: vbuck1 { 932 regulator-compatible = "vbuck1"; 933 regulator-name = "Vbcpu"; 934 regulator-min-microvolt = <300000>; 935 regulator-max-microvolt = <1193750>; 936 regulator-enable-ramp-delay = <256>; 937 regulator-ramp-delay = <6250>; 938 regulator-allowed-modes = <0 1 2>; 939 regulator-always-on; 940 }; 941 }; 942 }; 943 944 mt6315@7 { 945 compatible = "mediatek,mt6315-regulator"; 946 reg = <0x7 SPMI_USID>; 947 948 regulators { 949 mt6315_7_vbuck1: vbuck1 { 950 regulator-compatible = "vbuck1"; 951 regulator-name = "Vgpu"; 952 regulator-min-microvolt = <625000>; 953 regulator-max-microvolt = <1193750>; 954 regulator-enable-ramp-delay = <256>; 955 regulator-ramp-delay = <6250>; 956 regulator-allowed-modes = <0 1 2>; 957 regulator-always-on; 958 }; 959 }; 960 }; 961}; 962 963&u3phy0 { 964 status = "okay"; 965}; 966 967&u3phy1 { 968 status = "okay"; 969}; 970 971&u3phy2 { 972 status = "okay"; 973}; 974 975&u3phy3 { 976 status = "okay"; 977}; 978 979&uart0 { 980 status = "okay"; 981}; 982 983&xhci0 { 984 status = "okay"; 985 986 vusb33-supply = <&mt6359_vusb_ldo_reg>; 987 vbus-supply = <&usb_vbus>; 988}; 989 990&xhci1 { 991 status = "okay"; 992 993 vusb33-supply = <&mt6359_vusb_ldo_reg>; 994 vbus-supply = <&usb_vbus>; 995}; 996 997&xhci2 { 998 status = "okay"; 999 1000 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1001 vbus-supply = <&usb_vbus>; 1002}; 1003 1004&xhci3 { 1005 status = "okay"; 1006 1007 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1008 usb2-lpm-disable; 1009 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1010 vbus-supply = <&usb_vbus>; 1011}; 1012 1013#include <arm/cros-ec-keyboard.dtsi> 1014#include <arm/cros-ec-sbs.dtsi> 1015 1016&keyboard_controller { 1017 function-row-physmap = < 1018 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1019 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1020 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1021 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1022 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1023 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1024 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1025 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1026 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1027 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1028 >; 1029 1030 linux,keymap = < 1031 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1032 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1033 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1034 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1035 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 1036 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 1037 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 1038 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1039 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1040 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1041 1042 CROS_STD_MAIN_KEYMAP 1043 >; 1044}; 1045