1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 reg = <0 0x40000000 0 0x80000000>; 32 }; 33 34 /* system wide LDO 3.3V power rail */ 35 pp3300_z5: regulator-pp3300-ldo-z5 { 36 compatible = "regulator-fixed"; 37 regulator-name = "pp3300_ldo_z5"; 38 regulator-always-on; 39 regulator-boot-on; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 vin-supply = <&ppvar_sys>; 43 }; 44 45 /* separately switched 3.3V power rail */ 46 pp3300_s3: regulator-pp3300-s3 { 47 compatible = "regulator-fixed"; 48 regulator-name = "pp3300_s3"; 49 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 50 regulator-always-on; 51 regulator-boot-on; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 vin-supply = <&pp3300_z2>; 55 }; 56 57 /* system wide 3.3V power rail */ 58 pp3300_z2: regulator-pp3300-z2 { 59 compatible = "regulator-fixed"; 60 regulator-name = "pp3300_z2"; 61 /* EN pin tied to pp4200_z2, which is controlled by EC */ 62 regulator-always-on; 63 regulator-boot-on; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 vin-supply = <&ppvar_sys>; 67 }; 68 69 /* system wide 4.2V power rail */ 70 pp4200_z2: regulator-pp4200-z2 { 71 compatible = "regulator-fixed"; 72 regulator-name = "pp4200_z2"; 73 /* controlled by EC */ 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <4200000>; 77 regulator-max-microvolt = <4200000>; 78 vin-supply = <&ppvar_sys>; 79 }; 80 81 /* system wide switching 5.0V power rail */ 82 pp5000_s5: regulator-pp5000-s5 { 83 compatible = "regulator-fixed"; 84 regulator-name = "pp5000_s5"; 85 /* controlled by EC */ 86 regulator-always-on; 87 regulator-boot-on; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 vin-supply = <&ppvar_sys>; 91 }; 92 93 /* system wide semi-regulated power rail from battery or USB */ 94 ppvar_sys: regulator-ppvar-sys { 95 compatible = "regulator-fixed"; 96 regulator-name = "ppvar_sys"; 97 regulator-always-on; 98 regulator-boot-on; 99 }; 100 101 usb_vbus: regulator-5v0-usb-vbus { 102 compatible = "regulator-fixed"; 103 regulator-name = "usb-vbus"; 104 regulator-min-microvolt = <5000000>; 105 regulator-max-microvolt = <5000000>; 106 enable-active-high; 107 regulator-always-on; 108 }; 109 110 reserved_memory: reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 scp_mem: memory@50000000 { 116 compatible = "shared-dma-pool"; 117 reg = <0 0x50000000 0 0x2900000>; 118 no-map; 119 }; 120 121 afe_mem: memory@60d80000 { 122 compatible = "shared-dma-pool"; 123 reg = <0 0x60d80000 0 0x100000>; 124 no-map; 125 }; 126 }; 127}; 128 129&afe { 130 status = "okay"; 131 132 mediatek,etdm-in2-cowork-source = <2>; 133 mediatek,etdm-out2-cowork-source = <0>; 134 memory-region = <&afe_mem>; 135}; 136 137&dp_intf0 { 138 status = "okay"; 139 140 port { 141 dp_intf0_out: endpoint { 142 remote-endpoint = <&edp_in>; 143 }; 144 }; 145}; 146 147&dp_intf1 { 148 status = "okay"; 149 150 port { 151 dp_intf1_out: endpoint { 152 remote-endpoint = <&dptx_in>; 153 }; 154 }; 155}; 156 157&edp_tx { 158 status = "okay"; 159 160 pinctrl-names = "default"; 161 pinctrl-0 = <&edptx_pins_default>; 162 163 ports { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 port@0 { 168 reg = <0>; 169 edp_in: endpoint { 170 remote-endpoint = <&dp_intf0_out>; 171 }; 172 }; 173 174 port@1 { 175 reg = <1>; 176 edp_out: endpoint { 177 data-lanes = <0 1 2 3>; 178 }; 179 }; 180 }; 181}; 182 183&dp_tx { 184 status = "okay"; 185 186 pinctrl-names = "default"; 187 pinctrl-0 = <&dptx_pin>; 188 189 ports { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 port@0 { 194 reg = <0>; 195 dptx_in: endpoint { 196 remote-endpoint = <&dp_intf1_out>; 197 }; 198 }; 199 200 port@1 { 201 reg = <1>; 202 dptx_out: endpoint { 203 data-lanes = <0 1 2 3>; 204 }; 205 }; 206 }; 207}; 208 209&i2c0 { 210 status = "okay"; 211 212 clock-frequency = <400000>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&i2c0_pins>; 215}; 216 217&i2c1 { 218 status = "okay"; 219 220 clock-frequency = <400000>; 221 i2c-scl-internal-delay-ns = <12500>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&i2c1_pins>; 224 225 trackpad@15 { 226 compatible = "elan,ekth3000"; 227 reg = <0x15>; 228 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&trackpad_pins>; 231 vcc-supply = <&pp3300_s3>; 232 wakeup-source; 233 }; 234}; 235 236&i2c2 { 237 status = "okay"; 238 239 clock-frequency = <400000>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&i2c2_pins>; 242}; 243 244&i2c3 { 245 status = "okay"; 246 247 clock-frequency = <400000>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&i2c3_pins>; 250 251 tpm@50 { 252 compatible = "google,cr50"; 253 reg = <0x50>; 254 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&cr50_int>; 257 }; 258}; 259 260&i2c4 { 261 status = "okay"; 262 263 clock-frequency = <400000>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&i2c4_pins>; 266 267 ts_10: touchscreen@10 { 268 compatible = "hid-over-i2c"; 269 reg = <0x10>; 270 hid-descr-addr = <0x0001>; 271 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&touchscreen_pins>; 274 post-power-on-delay-ms = <10>; 275 vdd-supply = <&pp3300_s3>; 276 status = "disabled"; 277 }; 278}; 279 280&i2c5 { 281 status = "okay"; 282 283 clock-frequency = <400000>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&i2c5_pins>; 286}; 287 288&i2c7 { 289 status = "okay"; 290 291 clock-frequency = <400000>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&i2c7_pins>; 294 295 pmic@34 { 296 #interrupt-cells = <1>; 297 compatible = "mediatek,mt6360"; 298 reg = <0x34>; 299 interrupt-controller; 300 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 301 interrupt-names = "IRQB"; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&subpmic_default>; 304 wakeup-source; 305 }; 306}; 307 308&mmc0 { 309 status = "okay"; 310 311 bus-width = <8>; 312 cap-mmc-highspeed; 313 cap-mmc-hw-reset; 314 hs400-ds-delay = <0x14c11>; 315 max-frequency = <200000000>; 316 mmc-hs200-1_8v; 317 mmc-hs400-1_8v; 318 no-sdio; 319 no-sd; 320 non-removable; 321 pinctrl-names = "default", "state_uhs"; 322 pinctrl-0 = <&mmc0_pins_default>; 323 pinctrl-1 = <&mmc0_pins_uhs>; 324 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 325 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 326}; 327 328&mmc1 { 329 status = "okay"; 330 331 bus-width = <4>; 332 cap-sd-highspeed; 333 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 334 max-frequency = <200000000>; 335 no-mmc; 336 no-sdio; 337 pinctrl-names = "default", "state_uhs"; 338 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 339 pinctrl-1 = <&mmc1_pins_default>; 340 sd-uhs-sdr50; 341 sd-uhs-sdr104; 342 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 343 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 344}; 345 346/* for CPU-L */ 347&mt6359_vcore_buck_reg { 348 regulator-always-on; 349}; 350 351/* for CORE */ 352&mt6359_vgpu11_buck_reg { 353 regulator-always-on; 354}; 355 356&mt6359_vgpu11_sshub_buck_reg { 357 regulator-always-on; 358 regulator-min-microvolt = <550000>; 359 regulator-max-microvolt = <550000>; 360}; 361 362/* for CORE SRAM */ 363&mt6359_vpu_buck_reg { 364 regulator-always-on; 365}; 366 367&mt6359_vrf12_ldo_reg { 368 regulator-always-on; 369}; 370 371/* for GPU SRAM */ 372&mt6359_vsram_others_ldo_reg { 373 regulator-always-on; 374 regulator-min-microvolt = <750000>; 375 regulator-max-microvolt = <750000>; 376}; 377 378&mt6359_vufs_ldo_reg { 379 regulator-always-on; 380}; 381 382&nor_flash { 383 status = "okay"; 384 385 pinctrl-names = "default"; 386 pinctrl-0 = <&nor_pins_default>; 387 388 flash@0 { 389 compatible = "jedec,spi-nor"; 390 reg = <0>; 391 spi-max-frequency = <52000000>; 392 spi-rx-bus-width = <2>; 393 spi-tx-bus-width = <2>; 394 }; 395}; 396 397&pio { 398 mediatek,rsel-resistance-in-si-unit; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pio_default>; 401 402 /* 144 lines */ 403 gpio-line-names = 404 "I2S_SPKR_MCLK", 405 "I2S_SPKR_DATAIN", 406 "I2S_SPKR_LRCK", 407 "I2S_SPKR_BCLK", 408 "EC_AP_INT_ODL", 409 /* 410 * AP_FLASH_WP_L is crossystem ABI. Schematics 411 * call it AP_FLASH_WP_ODL. 412 */ 413 "AP_FLASH_WP_L", 414 "TCHPAD_INT_ODL", 415 "EDP_HPD_1V8", 416 "AP_I2C_CAM_SDA", 417 "AP_I2C_CAM_SCL", 418 "AP_I2C_TCHPAD_SDA_1V8", 419 "AP_I2C_TCHPAD_SCL_1V8", 420 "AP_I2C_AUD_SDA", 421 "AP_I2C_AUD_SCL", 422 "AP_I2C_TPM_SDA_1V8", 423 "AP_I2C_TPM_SCL_1V8", 424 "AP_I2C_TCHSCR_SDA_1V8", 425 "AP_I2C_TCHSCR_SCL_1V8", 426 "EC_AP_HPD_OD", 427 "", 428 "PCIE_NVME_RST_L", 429 "PCIE_NVME_CLKREQ_ODL", 430 "PCIE_RST_1V8_L", 431 "PCIE_CLKREQ_1V8_ODL", 432 "PCIE_WAKE_1V8_ODL", 433 "CLK_24M_CAM0", 434 "CAM1_SEN_EN", 435 "AP_I2C_PWR_SCL_1V8", 436 "AP_I2C_PWR_SDA_1V8", 437 "AP_I2C_MISC_SCL", 438 "AP_I2C_MISC_SDA", 439 "EN_PP5000_HDMI_X", 440 "AP_HDMITX_HTPLG", 441 "", 442 "AP_HDMITX_SCL_1V8", 443 "AP_HDMITX_SDA_1V8", 444 "AP_RTC_CLK32K", 445 "AP_EC_WATCHDOG_L", 446 "SRCLKENA0", 447 "SRCLKENA1", 448 "PWRAP_SPI0_CS_L", 449 "PWRAP_SPI0_CK", 450 "PWRAP_SPI0_MOSI", 451 "PWRAP_SPI0_MISO", 452 "SPMI_SCL", 453 "SPMI_SDA", 454 "", 455 "", 456 "", 457 "I2S_HP_DATAIN", 458 "I2S_HP_MCLK", 459 "I2S_HP_BCK", 460 "I2S_HP_LRCK", 461 "I2S_HP_DATAOUT", 462 "SD_CD_ODL", 463 "EN_PP3300_DISP_X", 464 "TCHSCR_RST_1V8_L", 465 "TCHSCR_REPORT_DISABLE", 466 "EN_PP3300_WLAN_X", 467 "BT_KILL_1V8_L", 468 "I2S_SPKR_DATAOUT", 469 "WIFI_KILL_1V8_L", 470 "BEEP_ON", 471 "SCP_I2C_SENSOR_SCL_1V8", 472 "SCP_I2C_SENSOR_SDA_1V8", 473 "", 474 "", 475 "", 476 "", 477 "AUD_CLK_MOSI", 478 "AUD_SYNC_MOSI", 479 "AUD_DAT_MOSI0", 480 "AUD_DAT_MOSI1", 481 "AUD_DAT_MISO0", 482 "AUD_DAT_MISO1", 483 "AUD_DAT_MISO2", 484 "SCP_VREQ_VAO", 485 "AP_SPI_GSC_TPM_CLK", 486 "AP_SPI_GSC_TPM_MOSI", 487 "AP_SPI_GSC_TPM_CS_L", 488 "AP_SPI_GSC_TPM_MISO", 489 "EN_PP1000_CAM_X", 490 "AP_EDP_BKLTEN", 491 "", 492 "USB3_HUB_RST_L", 493 "", 494 "WLAN_ALERT_ODL", 495 "EC_IN_RW_ODL", 496 "GSC_AP_INT_ODL", 497 "HP_INT_ODL", 498 "CAM0_RST_L", 499 "CAM1_RST_L", 500 "TCHSCR_INT_1V8_L", 501 "CAM1_DET_L", 502 "RST_ALC1011_L", 503 "", 504 "", 505 "BL_PWM_1V8", 506 "UART_AP_TX_DBG_RX", 507 "UART_DBG_TX_AP_RX", 508 "EN_SPKR", 509 "AP_EC_WARM_RST_REQ", 510 "UART_SCP_TX_DBGCON_RX", 511 "UART_DBGCON_TX_SCP_RX", 512 "", 513 "", 514 "KPCOL0", 515 "", 516 "MT6315_GPU_INT", 517 "MT6315_PROC_BC_INT", 518 "SD_CMD", 519 "SD_CLK", 520 "SD_DAT0", 521 "SD_DAT1", 522 "SD_DAT2", 523 "SD_DAT3", 524 "EMMC_DAT7", 525 "EMMC_DAT6", 526 "EMMC_DAT5", 527 "EMMC_DAT4", 528 "EMMC_RSTB", 529 "EMMC_CMD", 530 "EMMC_CLK", 531 "EMMC_DAT3", 532 "EMMC_DAT2", 533 "EMMC_DAT1", 534 "EMMC_DAT0", 535 "EMMC_DSL", 536 "", 537 "", 538 "MT6360_INT_ODL", 539 "SCP_JTAG0_TRSTN", 540 "AP_SPI_EC_CS_L", 541 "AP_SPI_EC_CLK", 542 "AP_SPI_EC_MOSI", 543 "AP_SPI_EC_MISO", 544 "SCP_JTAG0_TMS", 545 "SCP_JTAG0_TCK", 546 "SCP_JTAG0_TDO", 547 "SCP_JTAG0_TDI", 548 "AP_SPI_FLASH_CS_L", 549 "AP_SPI_FLASH_CLK", 550 "AP_SPI_FLASH_MOSI", 551 "AP_SPI_FLASH_MISO"; 552 553 cr50_int: cr50-irq-default-pins { 554 pins-gsc-ap-int-odl { 555 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 556 input-enable; 557 }; 558 }; 559 560 cros_ec_int: cros-ec-irq-default-pins { 561 pins-ec-ap-int-odl { 562 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 563 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 564 input-enable; 565 }; 566 }; 567 568 edptx_pins_default: edptx-default-pins { 569 pins-cmd-dat { 570 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 571 bias-pull-up; 572 }; 573 }; 574 575 dptx_pin: dptx-default-pins { 576 pins-cmd-dat { 577 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 578 bias-pull-up; 579 }; 580 }; 581 582 i2c0_pins: i2c0-default-pins { 583 pins-bus { 584 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 585 <PINMUX_GPIO9__FUNC_SCL0>; 586 bias-disable; 587 drive-strength-microamp = <1000>; 588 }; 589 }; 590 591 i2c1_pins: i2c1-default-pins { 592 pins-bus { 593 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 594 <PINMUX_GPIO11__FUNC_SCL1>; 595 bias-pull-up = <1000>; 596 drive-strength-microamp = <1000>; 597 }; 598 }; 599 600 i2c2_pins: i2c2-default-pins { 601 pins-bus { 602 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 603 <PINMUX_GPIO13__FUNC_SCL2>; 604 bias-disable; 605 drive-strength-microamp = <1000>; 606 }; 607 }; 608 609 i2c3_pins: i2c3-default-pins { 610 pins-bus { 611 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 612 <PINMUX_GPIO15__FUNC_SCL3>; 613 bias-pull-up = <1000>; 614 drive-strength-microamp = <1000>; 615 }; 616 }; 617 618 i2c4_pins: i2c4-default-pins { 619 pins-bus { 620 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 621 <PINMUX_GPIO17__FUNC_SCL4>; 622 bias-pull-up = <1000>; 623 drive-strength = <4>; 624 }; 625 }; 626 627 i2c5_pins: i2c5-default-pins { 628 pins-bus { 629 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 630 <PINMUX_GPIO30__FUNC_SDA5>; 631 bias-disable; 632 drive-strength-microamp = <1000>; 633 }; 634 }; 635 636 i2c7_pins: i2c7-default-pins { 637 pins-bus { 638 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 639 <PINMUX_GPIO28__FUNC_SDA7>; 640 bias-disable; 641 }; 642 }; 643 644 mmc0_pins_default: mmc0-default-pins { 645 pins-cmd-dat { 646 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 647 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 648 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 649 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 650 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 651 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 652 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 653 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 654 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 655 input-enable; 656 drive-strength = <6>; 657 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 658 }; 659 660 pins-clk { 661 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 662 drive-strength = <6>; 663 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 664 }; 665 666 pins-rst { 667 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 668 drive-strength = <6>; 669 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 670 }; 671 }; 672 673 mmc0_pins_uhs: mmc0-uhs-pins { 674 pins-cmd-dat { 675 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 676 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 677 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 678 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 679 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 680 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 681 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 682 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 683 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 684 input-enable; 685 drive-strength = <8>; 686 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 687 }; 688 689 pins-clk { 690 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 691 drive-strength = <8>; 692 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 693 }; 694 695 pins-ds { 696 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 697 drive-strength = <8>; 698 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 699 }; 700 701 pins-rst { 702 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 703 drive-strength = <8>; 704 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 705 }; 706 }; 707 708 mmc1_pins_detect: mmc1-detect-pins { 709 pins-insert { 710 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 711 bias-pull-up; 712 }; 713 }; 714 715 mmc1_pins_default: mmc1-default-pins { 716 pins-cmd-dat { 717 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 718 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 719 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 720 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 721 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 722 input-enable; 723 drive-strength = <8>; 724 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 725 }; 726 727 pins-clk { 728 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 729 drive-strength = <8>; 730 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 731 }; 732 }; 733 734 nor_pins_default: nor-default-pins { 735 pins-ck-io { 736 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 737 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 738 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 739 drive-strength = <6>; 740 bias-pull-down; 741 }; 742 743 pins-cs { 744 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 745 drive-strength = <6>; 746 bias-pull-up; 747 }; 748 }; 749 750 pio_default: pio-default-pins { 751 pins-wifi-enable { 752 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 753 output-high; 754 drive-strength = <14>; 755 }; 756 757 pins-low-power-pd { 758 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 759 <PINMUX_GPIO26__FUNC_GPIO26>, 760 <PINMUX_GPIO46__FUNC_GPIO46>, 761 <PINMUX_GPIO47__FUNC_GPIO47>, 762 <PINMUX_GPIO48__FUNC_GPIO48>, 763 <PINMUX_GPIO65__FUNC_GPIO65>, 764 <PINMUX_GPIO66__FUNC_GPIO66>, 765 <PINMUX_GPIO67__FUNC_GPIO67>, 766 <PINMUX_GPIO68__FUNC_GPIO68>, 767 <PINMUX_GPIO128__FUNC_GPIO128>, 768 <PINMUX_GPIO129__FUNC_GPIO129>; 769 input-enable; 770 bias-pull-down; 771 }; 772 773 pins-low-power-pupd { 774 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 775 <PINMUX_GPIO78__FUNC_GPIO78>, 776 <PINMUX_GPIO79__FUNC_GPIO79>, 777 <PINMUX_GPIO80__FUNC_GPIO80>, 778 <PINMUX_GPIO83__FUNC_GPIO83>, 779 <PINMUX_GPIO85__FUNC_GPIO85>, 780 <PINMUX_GPIO90__FUNC_GPIO90>, 781 <PINMUX_GPIO91__FUNC_GPIO91>, 782 <PINMUX_GPIO93__FUNC_GPIO93>, 783 <PINMUX_GPIO94__FUNC_GPIO94>, 784 <PINMUX_GPIO95__FUNC_GPIO95>, 785 <PINMUX_GPIO96__FUNC_GPIO96>, 786 <PINMUX_GPIO104__FUNC_GPIO104>, 787 <PINMUX_GPIO105__FUNC_GPIO105>, 788 <PINMUX_GPIO107__FUNC_GPIO107>; 789 input-enable; 790 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 791 }; 792 }; 793 794 scp_pins: scp-default-pins { 795 pins-vreq { 796 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 797 bias-disable; 798 input-enable; 799 }; 800 }; 801 802 spi0_pins: spi0-default-pins { 803 pins-cs-mosi-clk { 804 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 805 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 806 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 807 bias-disable; 808 }; 809 810 pins-miso { 811 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 812 bias-pull-down; 813 }; 814 }; 815 816 subpmic_default: subpmic-default-pins { 817 subpmic_pin_irq: pins-subpmic-int-n { 818 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 819 input-enable; 820 bias-pull-up; 821 }; 822 }; 823 824 trackpad_pins: trackpad-default-pins { 825 pins-int-n { 826 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 827 input-enable; 828 bias-pull-up; 829 }; 830 }; 831 832 touchscreen_pins: touchscreen-default-pins { 833 pins-int-n { 834 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 835 input-enable; 836 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 837 }; 838 pins-rst { 839 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 840 output-high; 841 }; 842 pins-report-sw { 843 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 844 output-low; 845 }; 846 }; 847}; 848 849&pmic { 850 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 851}; 852 853&scp { 854 status = "okay"; 855 856 firmware-name = "mediatek/mt8195/scp.img"; 857 memory-region = <&scp_mem>; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&scp_pins>; 860 861 cros-ec-rpmsg { 862 compatible = "google,cros-ec-rpmsg"; 863 mediatek,rpmsg-name = "cros-ec-rpmsg"; 864 }; 865}; 866 867&spi0 { 868 status = "okay"; 869 870 pinctrl-names = "default"; 871 pinctrl-0 = <&spi0_pins>; 872 mediatek,pad-select = <0>; 873 874 cros_ec: ec@0 { 875 #address-cells = <1>; 876 #size-cells = <0>; 877 878 compatible = "google,cros-ec-spi"; 879 reg = <0>; 880 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 881 pinctrl-names = "default"; 882 pinctrl-0 = <&cros_ec_int>; 883 spi-max-frequency = <3000000>; 884 885 keyboard-backlight { 886 compatible = "google,cros-kbd-led-backlight"; 887 }; 888 889 i2c_tunnel: i2c-tunnel { 890 compatible = "google,cros-ec-i2c-tunnel"; 891 google,remote-bus = <0>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 }; 895 896 mt_pmic_vmc_ldo_reg: regulator@0 { 897 compatible = "google,cros-ec-regulator"; 898 reg = <0>; 899 regulator-name = "mt_pmic_vmc_ldo"; 900 regulator-min-microvolt = <1200000>; 901 regulator-max-microvolt = <3600000>; 902 }; 903 904 mt_pmic_vmch_ldo_reg: regulator@1 { 905 compatible = "google,cros-ec-regulator"; 906 reg = <1>; 907 regulator-name = "mt_pmic_vmch_ldo"; 908 regulator-min-microvolt = <2700000>; 909 regulator-max-microvolt = <3600000>; 910 }; 911 912 typec { 913 compatible = "google,cros-ec-typec"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 917 usb_c0: connector@0 { 918 compatible = "usb-c-connector"; 919 reg = <0>; 920 power-role = "dual"; 921 data-role = "host"; 922 try-power-role = "source"; 923 }; 924 925 usb_c1: connector@1 { 926 compatible = "usb-c-connector"; 927 reg = <1>; 928 power-role = "dual"; 929 data-role = "host"; 930 try-power-role = "source"; 931 }; 932 }; 933 }; 934}; 935 936&spmi { 937 #address-cells = <2>; 938 #size-cells = <0>; 939 940 mt6315@6 { 941 compatible = "mediatek,mt6315-regulator"; 942 reg = <0x6 SPMI_USID>; 943 944 regulators { 945 mt6315_6_vbuck1: vbuck1 { 946 regulator-compatible = "vbuck1"; 947 regulator-name = "Vbcpu"; 948 regulator-min-microvolt = <300000>; 949 regulator-max-microvolt = <1193750>; 950 regulator-enable-ramp-delay = <256>; 951 regulator-ramp-delay = <6250>; 952 regulator-allowed-modes = <0 1 2>; 953 regulator-always-on; 954 }; 955 }; 956 }; 957 958 mt6315@7 { 959 compatible = "mediatek,mt6315-regulator"; 960 reg = <0x7 SPMI_USID>; 961 962 regulators { 963 mt6315_7_vbuck1: vbuck1 { 964 regulator-compatible = "vbuck1"; 965 regulator-name = "Vgpu"; 966 regulator-min-microvolt = <625000>; 967 regulator-max-microvolt = <1193750>; 968 regulator-enable-ramp-delay = <256>; 969 regulator-ramp-delay = <6250>; 970 regulator-allowed-modes = <0 1 2>; 971 regulator-always-on; 972 }; 973 }; 974 }; 975}; 976 977&u3phy0 { 978 status = "okay"; 979}; 980 981&u3phy1 { 982 status = "okay"; 983}; 984 985&u3phy2 { 986 status = "okay"; 987}; 988 989&u3phy3 { 990 status = "okay"; 991}; 992 993&uart0 { 994 status = "okay"; 995}; 996 997&xhci0 { 998 status = "okay"; 999 1000 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1001 vbus-supply = <&usb_vbus>; 1002}; 1003 1004&xhci1 { 1005 status = "okay"; 1006 1007 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1008 vbus-supply = <&usb_vbus>; 1009}; 1010 1011&xhci2 { 1012 status = "okay"; 1013 1014 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1015 vbus-supply = <&usb_vbus>; 1016}; 1017 1018&xhci3 { 1019 status = "okay"; 1020 1021 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1022 usb2-lpm-disable; 1023 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1024 vbus-supply = <&usb_vbus>; 1025}; 1026 1027#include <arm/cros-ec-keyboard.dtsi> 1028#include <arm/cros-ec-sbs.dtsi> 1029 1030&keyboard_controller { 1031 function-row-physmap = < 1032 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1033 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1034 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1035 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1036 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1037 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1038 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1039 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1040 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1041 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1042 >; 1043 1044 linux,keymap = < 1045 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1046 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1047 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1048 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1049 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 1050 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 1051 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 1052 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1053 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1054 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1055 1056 CROS_STD_MAIN_KEYMAP 1057 >; 1058}; 1059