1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include "mt8195.dtsi" 8#include "mt6359.dtsi" 9 10/ { 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 serial0 = &uart0; 21 }; 22 23 chosen { 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 memory@40000000 { 28 device_type = "memory"; 29 reg = <0 0x40000000 0 0x80000000>; 30 }; 31 32 /* system wide LDO 3.3V power rail */ 33 pp3300_z5: regulator-pp3300-ldo-z5 { 34 compatible = "regulator-fixed"; 35 regulator-name = "pp3300_ldo_z5"; 36 regulator-always-on; 37 regulator-boot-on; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 vin-supply = <&ppvar_sys>; 41 }; 42 43 /* separately switched 3.3V power rail */ 44 pp3300_s3: regulator-pp3300-s3 { 45 compatible = "regulator-fixed"; 46 regulator-name = "pp3300_s3"; 47 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 48 regulator-always-on; 49 regulator-boot-on; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 vin-supply = <&pp3300_z2>; 53 }; 54 55 /* system wide 3.3V power rail */ 56 pp3300_z2: regulator-pp3300-z2 { 57 compatible = "regulator-fixed"; 58 regulator-name = "pp3300_z2"; 59 /* EN pin tied to pp4200_z2, which is controlled by EC */ 60 regulator-always-on; 61 regulator-boot-on; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 vin-supply = <&ppvar_sys>; 65 }; 66 67 /* system wide 4.2V power rail */ 68 pp4200_z2: regulator-pp4200-z2 { 69 compatible = "regulator-fixed"; 70 regulator-name = "pp4200_z2"; 71 /* controlled by EC */ 72 regulator-always-on; 73 regulator-boot-on; 74 regulator-min-microvolt = <4200000>; 75 regulator-max-microvolt = <4200000>; 76 vin-supply = <&ppvar_sys>; 77 }; 78 79 /* system wide switching 5.0V power rail */ 80 pp5000_s5: regulator-pp5000-s5 { 81 compatible = "regulator-fixed"; 82 regulator-name = "pp5000_s5"; 83 /* controlled by EC */ 84 regulator-always-on; 85 regulator-boot-on; 86 regulator-min-microvolt = <5000000>; 87 regulator-max-microvolt = <5000000>; 88 vin-supply = <&ppvar_sys>; 89 }; 90 91 /* system wide semi-regulated power rail from battery or USB */ 92 ppvar_sys: regulator-ppvar-sys { 93 compatible = "regulator-fixed"; 94 regulator-name = "ppvar_sys"; 95 regulator-always-on; 96 regulator-boot-on; 97 }; 98 99 usb_vbus: regulator-5v0-usb-vbus { 100 compatible = "regulator-fixed"; 101 regulator-name = "usb-vbus"; 102 regulator-min-microvolt = <5000000>; 103 regulator-max-microvolt = <5000000>; 104 enable-active-high; 105 regulator-always-on; 106 }; 107 108 reserved_memory: reserved-memory { 109 #address-cells = <2>; 110 #size-cells = <2>; 111 ranges; 112 113 scp_mem: memory@50000000 { 114 compatible = "shared-dma-pool"; 115 reg = <0 0x50000000 0 0x2900000>; 116 no-map; 117 }; 118 }; 119}; 120 121&i2c0 { 122 status = "okay"; 123 124 clock-frequency = <400000>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&i2c0_pins>; 127}; 128 129&i2c1 { 130 status = "okay"; 131 132 clock-frequency = <400000>; 133 i2c-scl-internal-delay-ns = <12500>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&i2c1_pins>; 136}; 137 138&i2c2 { 139 status = "okay"; 140 141 clock-frequency = <400000>; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&i2c2_pins>; 144}; 145 146&i2c3 { 147 status = "okay"; 148 149 clock-frequency = <400000>; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&i2c3_pins>; 152 153 tpm@50 { 154 compatible = "google,cr50"; 155 reg = <0x50>; 156 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&cr50_int>; 159 }; 160}; 161 162&i2c4 { 163 status = "okay"; 164 165 clock-frequency = <400000>; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&i2c4_pins>; 168 169 ts_10: touchscreen@10 { 170 compatible = "hid-over-i2c"; 171 reg = <0x10>; 172 hid-descr-addr = <0x0001>; 173 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&touchscreen_pins>; 176 post-power-on-delay-ms = <10>; 177 vdd-supply = <&pp3300_s3>; 178 status = "disabled"; 179 }; 180}; 181 182&i2c5 { 183 status = "okay"; 184 185 clock-frequency = <400000>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&i2c5_pins>; 188}; 189 190&i2c7 { 191 status = "okay"; 192 193 clock-frequency = <400000>; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&i2c7_pins>; 196 197 pmic@34 { 198 #interrupt-cells = <1>; 199 compatible = "mediatek,mt6360"; 200 reg = <0x34>; 201 interrupt-controller; 202 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 203 interrupt-names = "IRQB"; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&subpmic_default>; 206 wakeup-source; 207 }; 208}; 209 210&mmc0 { 211 status = "okay"; 212 213 bus-width = <8>; 214 cap-mmc-highspeed; 215 cap-mmc-hw-reset; 216 hs400-ds-delay = <0x14c11>; 217 max-frequency = <200000000>; 218 mmc-hs200-1_8v; 219 mmc-hs400-1_8v; 220 no-sdio; 221 no-sd; 222 non-removable; 223 pinctrl-names = "default", "state_uhs"; 224 pinctrl-0 = <&mmc0_pins_default>; 225 pinctrl-1 = <&mmc0_pins_uhs>; 226 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 227 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 228}; 229 230/* for CPU-L */ 231&mt6359_vcore_buck_reg { 232 regulator-always-on; 233}; 234 235/* for CORE */ 236&mt6359_vgpu11_buck_reg { 237 regulator-always-on; 238}; 239 240&mt6359_vgpu11_sshub_buck_reg { 241 regulator-always-on; 242 regulator-min-microvolt = <550000>; 243 regulator-max-microvolt = <550000>; 244}; 245 246/* for CORE SRAM */ 247&mt6359_vpu_buck_reg { 248 regulator-always-on; 249}; 250 251&mt6359_vrf12_ldo_reg { 252 regulator-always-on; 253}; 254 255/* for GPU SRAM */ 256&mt6359_vsram_others_ldo_reg { 257 regulator-always-on; 258 regulator-min-microvolt = <750000>; 259 regulator-max-microvolt = <750000>; 260}; 261 262&mt6359_vufs_ldo_reg { 263 regulator-always-on; 264}; 265 266&nor_flash { 267 status = "okay"; 268 269 pinctrl-names = "default"; 270 pinctrl-0 = <&nor_pins_default>; 271 272 flash@0 { 273 compatible = "jedec,spi-nor"; 274 reg = <0>; 275 spi-max-frequency = <52000000>; 276 spi-rx-bus-width = <2>; 277 spi-tx-bus-width = <2>; 278 }; 279}; 280 281&pio { 282 mediatek,rsel-resistance-in-si-unit; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pio_default>; 285 286 /* 144 lines */ 287 gpio-line-names = 288 "I2S_SPKR_MCLK", 289 "I2S_SPKR_DATAIN", 290 "I2S_SPKR_LRCK", 291 "I2S_SPKR_BCLK", 292 "EC_AP_INT_ODL", 293 /* 294 * AP_FLASH_WP_L is crossystem ABI. Schematics 295 * call it AP_FLASH_WP_ODL. 296 */ 297 "AP_FLASH_WP_L", 298 "TCHPAD_INT_ODL", 299 "EDP_HPD_1V8", 300 "AP_I2C_CAM_SDA", 301 "AP_I2C_CAM_SCL", 302 "AP_I2C_TCHPAD_SDA_1V8", 303 "AP_I2C_TCHPAD_SCL_1V8", 304 "AP_I2C_AUD_SDA", 305 "AP_I2C_AUD_SCL", 306 "AP_I2C_TPM_SDA_1V8", 307 "AP_I2C_TPM_SCL_1V8", 308 "AP_I2C_TCHSCR_SDA_1V8", 309 "AP_I2C_TCHSCR_SCL_1V8", 310 "EC_AP_HPD_OD", 311 "", 312 "PCIE_NVME_RST_L", 313 "PCIE_NVME_CLKREQ_ODL", 314 "PCIE_RST_1V8_L", 315 "PCIE_CLKREQ_1V8_ODL", 316 "PCIE_WAKE_1V8_ODL", 317 "CLK_24M_CAM0", 318 "CAM1_SEN_EN", 319 "AP_I2C_PWR_SCL_1V8", 320 "AP_I2C_PWR_SDA_1V8", 321 "AP_I2C_MISC_SCL", 322 "AP_I2C_MISC_SDA", 323 "EN_PP5000_HDMI_X", 324 "AP_HDMITX_HTPLG", 325 "", 326 "AP_HDMITX_SCL_1V8", 327 "AP_HDMITX_SDA_1V8", 328 "AP_RTC_CLK32K", 329 "AP_EC_WATCHDOG_L", 330 "SRCLKENA0", 331 "SRCLKENA1", 332 "PWRAP_SPI0_CS_L", 333 "PWRAP_SPI0_CK", 334 "PWRAP_SPI0_MOSI", 335 "PWRAP_SPI0_MISO", 336 "SPMI_SCL", 337 "SPMI_SDA", 338 "", 339 "", 340 "", 341 "I2S_HP_DATAIN", 342 "I2S_HP_MCLK", 343 "I2S_HP_BCK", 344 "I2S_HP_LRCK", 345 "I2S_HP_DATAOUT", 346 "SD_CD_ODL", 347 "EN_PP3300_DISP_X", 348 "TCHSCR_RST_1V8_L", 349 "TCHSCR_REPORT_DISABLE", 350 "EN_PP3300_WLAN_X", 351 "BT_KILL_1V8_L", 352 "I2S_SPKR_DATAOUT", 353 "WIFI_KILL_1V8_L", 354 "BEEP_ON", 355 "SCP_I2C_SENSOR_SCL_1V8", 356 "SCP_I2C_SENSOR_SDA_1V8", 357 "", 358 "", 359 "", 360 "", 361 "AUD_CLK_MOSI", 362 "AUD_SYNC_MOSI", 363 "AUD_DAT_MOSI0", 364 "AUD_DAT_MOSI1", 365 "AUD_DAT_MISO0", 366 "AUD_DAT_MISO1", 367 "AUD_DAT_MISO2", 368 "SCP_VREQ_VAO", 369 "AP_SPI_GSC_TPM_CLK", 370 "AP_SPI_GSC_TPM_MOSI", 371 "AP_SPI_GSC_TPM_CS_L", 372 "AP_SPI_GSC_TPM_MISO", 373 "EN_PP1000_CAM_X", 374 "AP_EDP_BKLTEN", 375 "", 376 "USB3_HUB_RST_L", 377 "", 378 "WLAN_ALERT_ODL", 379 "EC_IN_RW_ODL", 380 "GSC_AP_INT_ODL", 381 "HP_INT_ODL", 382 "CAM0_RST_L", 383 "CAM1_RST_L", 384 "TCHSCR_INT_1V8_L", 385 "CAM1_DET_L", 386 "RST_ALC1011_L", 387 "", 388 "", 389 "BL_PWM_1V8", 390 "UART_AP_TX_DBG_RX", 391 "UART_DBG_TX_AP_RX", 392 "EN_SPKR", 393 "AP_EC_WARM_RST_REQ", 394 "UART_SCP_TX_DBGCON_RX", 395 "UART_DBGCON_TX_SCP_RX", 396 "", 397 "", 398 "KPCOL0", 399 "", 400 "MT6315_GPU_INT", 401 "MT6315_PROC_BC_INT", 402 "SD_CMD", 403 "SD_CLK", 404 "SD_DAT0", 405 "SD_DAT1", 406 "SD_DAT2", 407 "SD_DAT3", 408 "EMMC_DAT7", 409 "EMMC_DAT6", 410 "EMMC_DAT5", 411 "EMMC_DAT4", 412 "EMMC_RSTB", 413 "EMMC_CMD", 414 "EMMC_CLK", 415 "EMMC_DAT3", 416 "EMMC_DAT2", 417 "EMMC_DAT1", 418 "EMMC_DAT0", 419 "EMMC_DSL", 420 "", 421 "", 422 "MT6360_INT_ODL", 423 "SCP_JTAG0_TRSTN", 424 "AP_SPI_EC_CS_L", 425 "AP_SPI_EC_CLK", 426 "AP_SPI_EC_MOSI", 427 "AP_SPI_EC_MISO", 428 "SCP_JTAG0_TMS", 429 "SCP_JTAG0_TCK", 430 "SCP_JTAG0_TDO", 431 "SCP_JTAG0_TDI", 432 "AP_SPI_FLASH_CS_L", 433 "AP_SPI_FLASH_CLK", 434 "AP_SPI_FLASH_MOSI", 435 "AP_SPI_FLASH_MISO"; 436 437 cr50_int: cr50-irq-default-pins { 438 pins-gsc-ap-int-odl { 439 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 440 input-enable; 441 }; 442 }; 443 444 cros_ec_int: cros-ec-irq-default-pins { 445 pins-ec-ap-int-odl { 446 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 447 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 448 input-enable; 449 }; 450 }; 451 452 i2c0_pins: i2c0-default-pins { 453 pins-bus { 454 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 455 <PINMUX_GPIO9__FUNC_SCL0>; 456 bias-disable; 457 drive-strength-microamp = <1000>; 458 }; 459 }; 460 461 i2c1_pins: i2c1-default-pins { 462 pins-bus { 463 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 464 <PINMUX_GPIO11__FUNC_SCL1>; 465 bias-pull-up = <1000>; 466 drive-strength-microamp = <1000>; 467 }; 468 }; 469 470 i2c2_pins: i2c2-default-pins { 471 pins-bus { 472 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 473 <PINMUX_GPIO13__FUNC_SCL2>; 474 bias-disable; 475 drive-strength-microamp = <1000>; 476 }; 477 }; 478 479 i2c3_pins: i2c3-default-pins { 480 pins-bus { 481 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 482 <PINMUX_GPIO15__FUNC_SCL3>; 483 bias-pull-up = <1000>; 484 drive-strength-microamp = <1000>; 485 }; 486 }; 487 488 i2c4_pins: i2c4-default-pins { 489 pins-bus { 490 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 491 <PINMUX_GPIO17__FUNC_SCL4>; 492 bias-pull-up = <1000>; 493 drive-strength = <4>; 494 }; 495 }; 496 497 i2c5_pins: i2c5-default-pins { 498 pins-bus { 499 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 500 <PINMUX_GPIO30__FUNC_SDA5>; 501 bias-disable; 502 drive-strength-microamp = <1000>; 503 }; 504 }; 505 506 i2c7_pins: i2c7-default-pins { 507 pins-bus { 508 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 509 <PINMUX_GPIO28__FUNC_SDA7>; 510 bias-disable; 511 }; 512 }; 513 514 mmc0_pins_default: mmc0-default-pins { 515 pins-cmd-dat { 516 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 517 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 518 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 519 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 520 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 521 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 522 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 523 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 524 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 525 input-enable; 526 drive-strength = <6>; 527 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 528 }; 529 530 pins-clk { 531 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 532 drive-strength = <6>; 533 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 534 }; 535 536 pins-rst { 537 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 538 drive-strength = <6>; 539 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 540 }; 541 }; 542 543 mmc0_pins_uhs: mmc0-uhs-pins { 544 pins-cmd-dat { 545 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 546 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 547 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 548 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 549 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 550 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 551 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 552 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 553 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 554 input-enable; 555 drive-strength = <8>; 556 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 557 }; 558 559 pins-clk { 560 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 561 drive-strength = <8>; 562 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 563 }; 564 565 pins-ds { 566 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 567 drive-strength = <8>; 568 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 569 }; 570 571 pins-rst { 572 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 573 drive-strength = <8>; 574 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 575 }; 576 }; 577 578 nor_pins_default: nor-default-pins { 579 pins-ck-io { 580 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 581 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 582 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 583 drive-strength = <6>; 584 bias-pull-down; 585 }; 586 587 pins-cs { 588 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 589 drive-strength = <6>; 590 bias-pull-up; 591 }; 592 }; 593 594 pio_default: pio-default-pins { 595 pins-wifi-enable { 596 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 597 output-high; 598 drive-strength = <14>; 599 }; 600 601 pins-low-power-pd { 602 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 603 <PINMUX_GPIO26__FUNC_GPIO26>, 604 <PINMUX_GPIO46__FUNC_GPIO46>, 605 <PINMUX_GPIO47__FUNC_GPIO47>, 606 <PINMUX_GPIO48__FUNC_GPIO48>, 607 <PINMUX_GPIO65__FUNC_GPIO65>, 608 <PINMUX_GPIO66__FUNC_GPIO66>, 609 <PINMUX_GPIO67__FUNC_GPIO67>, 610 <PINMUX_GPIO68__FUNC_GPIO68>, 611 <PINMUX_GPIO128__FUNC_GPIO128>, 612 <PINMUX_GPIO129__FUNC_GPIO129>; 613 input-enable; 614 bias-pull-down; 615 }; 616 617 pins-low-power-pupd { 618 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 619 <PINMUX_GPIO78__FUNC_GPIO78>, 620 <PINMUX_GPIO79__FUNC_GPIO79>, 621 <PINMUX_GPIO80__FUNC_GPIO80>, 622 <PINMUX_GPIO83__FUNC_GPIO83>, 623 <PINMUX_GPIO85__FUNC_GPIO85>, 624 <PINMUX_GPIO90__FUNC_GPIO90>, 625 <PINMUX_GPIO91__FUNC_GPIO91>, 626 <PINMUX_GPIO93__FUNC_GPIO93>, 627 <PINMUX_GPIO94__FUNC_GPIO94>, 628 <PINMUX_GPIO95__FUNC_GPIO95>, 629 <PINMUX_GPIO96__FUNC_GPIO96>, 630 <PINMUX_GPIO104__FUNC_GPIO104>, 631 <PINMUX_GPIO105__FUNC_GPIO105>, 632 <PINMUX_GPIO107__FUNC_GPIO107>; 633 input-enable; 634 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 635 }; 636 }; 637 638 scp_pins: scp-default-pins { 639 pins-vreq { 640 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 641 bias-disable; 642 input-enable; 643 }; 644 }; 645 646 spi0_pins: spi0-default-pins { 647 pins-cs-mosi-clk { 648 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 649 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 650 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 651 bias-disable; 652 }; 653 654 pins-miso { 655 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 656 bias-pull-down; 657 }; 658 }; 659 660 subpmic_default: subpmic-default-pins { 661 subpmic_pin_irq: pins-subpmic-int-n { 662 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 663 input-enable; 664 bias-pull-up; 665 }; 666 }; 667 668 touchscreen_pins: touchscreen-default-pins { 669 pins-int-n { 670 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 671 input-enable; 672 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 673 }; 674 pins-rst { 675 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 676 output-high; 677 }; 678 pins-report-sw { 679 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 680 output-low; 681 }; 682 }; 683}; 684 685&pmic { 686 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 687}; 688 689&scp { 690 status = "okay"; 691 692 firmware-name = "mediatek/mt8195/scp.img"; 693 memory-region = <&scp_mem>; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&scp_pins>; 696 697 cros-ec-rpmsg { 698 compatible = "google,cros-ec-rpmsg"; 699 mediatek,rpmsg-name = "cros-ec-rpmsg"; 700 }; 701}; 702 703&spi0 { 704 status = "okay"; 705 706 pinctrl-names = "default"; 707 pinctrl-0 = <&spi0_pins>; 708 mediatek,pad-select = <0>; 709 710 cros_ec: ec@0 { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 714 compatible = "google,cros-ec-spi"; 715 reg = <0>; 716 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&cros_ec_int>; 719 spi-max-frequency = <3000000>; 720 721 keyboard-backlight { 722 compatible = "google,cros-kbd-led-backlight"; 723 }; 724 725 i2c_tunnel: i2c-tunnel { 726 compatible = "google,cros-ec-i2c-tunnel"; 727 google,remote-bus = <0>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 }; 731 732 mt_pmic_vmc_ldo_reg: regulator@0 { 733 compatible = "google,cros-ec-regulator"; 734 reg = <0>; 735 regulator-name = "mt_pmic_vmc_ldo"; 736 regulator-min-microvolt = <1200000>; 737 regulator-max-microvolt = <3600000>; 738 }; 739 740 mt_pmic_vmch_ldo_reg: regulator@1 { 741 compatible = "google,cros-ec-regulator"; 742 reg = <1>; 743 regulator-name = "mt_pmic_vmch_ldo"; 744 regulator-min-microvolt = <2700000>; 745 regulator-max-microvolt = <3600000>; 746 }; 747 748 typec { 749 compatible = "google,cros-ec-typec"; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 753 usb_c0: connector@0 { 754 compatible = "usb-c-connector"; 755 reg = <0>; 756 power-role = "dual"; 757 data-role = "host"; 758 try-power-role = "source"; 759 }; 760 761 usb_c1: connector@1 { 762 compatible = "usb-c-connector"; 763 reg = <1>; 764 power-role = "dual"; 765 data-role = "host"; 766 try-power-role = "source"; 767 }; 768 }; 769 }; 770}; 771 772&u3phy0 { 773 status = "okay"; 774}; 775 776&u3phy1 { 777 status = "okay"; 778}; 779 780&u3phy2 { 781 status = "okay"; 782}; 783 784&u3phy3 { 785 status = "okay"; 786}; 787 788&uart0 { 789 status = "okay"; 790}; 791 792&xhci0 { 793 status = "okay"; 794 795 vusb33-supply = <&mt6359_vusb_ldo_reg>; 796 vbus-supply = <&usb_vbus>; 797}; 798 799&xhci1 { 800 status = "okay"; 801 802 vusb33-supply = <&mt6359_vusb_ldo_reg>; 803 vbus-supply = <&usb_vbus>; 804}; 805 806&xhci2 { 807 status = "okay"; 808 809 vusb33-supply = <&mt6359_vusb_ldo_reg>; 810 vbus-supply = <&usb_vbus>; 811}; 812 813&xhci3 { 814 status = "okay"; 815 816 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 817 usb2-lpm-disable; 818 vusb33-supply = <&mt6359_vusb_ldo_reg>; 819 vbus-supply = <&usb_vbus>; 820}; 821 822#include <arm/cros-ec-keyboard.dtsi> 823#include <arm/cros-ec-sbs.dtsi> 824 825&keyboard_controller { 826 function-row-physmap = < 827 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 828 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 829 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 830 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 831 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 832 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 833 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 834 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 835 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 836 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 837 >; 838 839 linux,keymap = < 840 MATRIX_KEY(0x00, 0x02, KEY_BACK) 841 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 842 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 843 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 844 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 845 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 846 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 847 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 848 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 849 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 850 851 CROS_STD_MAIN_KEYMAP 852 >; 853}; 854