1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 dmic-codec { 30 compatible = "dmic-codec"; 31 num-channels = <2>; 32 wakeup-delay-ms = <50>; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 /* system wide LDO 3.3V power rail */ 41 pp3300_z5: regulator-pp3300-ldo-z5 { 42 compatible = "regulator-fixed"; 43 regulator-name = "pp3300_ldo_z5"; 44 regulator-always-on; 45 regulator-boot-on; 46 regulator-min-microvolt = <3300000>; 47 regulator-max-microvolt = <3300000>; 48 vin-supply = <&ppvar_sys>; 49 }; 50 51 /* separately switched 3.3V power rail */ 52 pp3300_s3: regulator-pp3300-s3 { 53 compatible = "regulator-fixed"; 54 regulator-name = "pp3300_s3"; 55 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 56 regulator-always-on; 57 regulator-boot-on; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 vin-supply = <&pp3300_z2>; 61 }; 62 63 /* system wide 3.3V power rail */ 64 pp3300_z2: regulator-pp3300-z2 { 65 compatible = "regulator-fixed"; 66 regulator-name = "pp3300_z2"; 67 /* EN pin tied to pp4200_z2, which is controlled by EC */ 68 regulator-always-on; 69 regulator-boot-on; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 vin-supply = <&ppvar_sys>; 73 }; 74 75 /* system wide 4.2V power rail */ 76 pp4200_z2: regulator-pp4200-z2 { 77 compatible = "regulator-fixed"; 78 regulator-name = "pp4200_z2"; 79 /* controlled by EC */ 80 regulator-always-on; 81 regulator-boot-on; 82 regulator-min-microvolt = <4200000>; 83 regulator-max-microvolt = <4200000>; 84 vin-supply = <&ppvar_sys>; 85 }; 86 87 /* system wide switching 5.0V power rail */ 88 pp5000_s5: regulator-pp5000-s5 { 89 compatible = "regulator-fixed"; 90 regulator-name = "pp5000_s5"; 91 /* controlled by EC */ 92 regulator-always-on; 93 regulator-boot-on; 94 regulator-min-microvolt = <5000000>; 95 regulator-max-microvolt = <5000000>; 96 vin-supply = <&ppvar_sys>; 97 }; 98 99 /* system wide semi-regulated power rail from battery or USB */ 100 ppvar_sys: regulator-ppvar-sys { 101 compatible = "regulator-fixed"; 102 regulator-name = "ppvar_sys"; 103 regulator-always-on; 104 regulator-boot-on; 105 }; 106 107 usb_vbus: regulator-5v0-usb-vbus { 108 compatible = "regulator-fixed"; 109 regulator-name = "usb-vbus"; 110 regulator-min-microvolt = <5000000>; 111 regulator-max-microvolt = <5000000>; 112 enable-active-high; 113 regulator-always-on; 114 }; 115 116 reserved_memory: reserved-memory { 117 #address-cells = <2>; 118 #size-cells = <2>; 119 ranges; 120 121 scp_mem: memory@50000000 { 122 compatible = "shared-dma-pool"; 123 reg = <0 0x50000000 0 0x2900000>; 124 no-map; 125 }; 126 127 adsp_mem: memory@60000000 { 128 compatible = "shared-dma-pool"; 129 reg = <0 0x60000000 0 0xd80000>; 130 no-map; 131 }; 132 133 afe_mem: memory@60d80000 { 134 compatible = "shared-dma-pool"; 135 reg = <0 0x60d80000 0 0x100000>; 136 no-map; 137 }; 138 139 adsp_device_mem: memory@60e80000 { 140 compatible = "shared-dma-pool"; 141 reg = <0 0x60e80000 0 0x280000>; 142 no-map; 143 }; 144 }; 145 146 spk_amplifier: rt1019p { 147 compatible = "realtek,rt1019p"; 148 label = "rt1019p"; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&rt1019p_pins_default>; 151 sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; 152 }; 153}; 154 155&adsp { 156 status = "okay"; 157 158 memory-region = <&adsp_device_mem>, <&adsp_mem>; 159}; 160 161&afe { 162 status = "okay"; 163 164 mediatek,etdm-in2-cowork-source = <2>; 165 mediatek,etdm-out2-cowork-source = <0>; 166 memory-region = <&afe_mem>; 167}; 168 169&dp_intf0 { 170 status = "okay"; 171 172 port { 173 dp_intf0_out: endpoint { 174 remote-endpoint = <&edp_in>; 175 }; 176 }; 177}; 178 179&dp_intf1 { 180 status = "okay"; 181 182 port { 183 dp_intf1_out: endpoint { 184 remote-endpoint = <&dptx_in>; 185 }; 186 }; 187}; 188 189&edp_tx { 190 status = "okay"; 191 192 pinctrl-names = "default"; 193 pinctrl-0 = <&edptx_pins_default>; 194 195 ports { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 port@0 { 200 reg = <0>; 201 edp_in: endpoint { 202 remote-endpoint = <&dp_intf0_out>; 203 }; 204 }; 205 206 port@1 { 207 reg = <1>; 208 edp_out: endpoint { 209 data-lanes = <0 1 2 3>; 210 }; 211 }; 212 }; 213}; 214 215&dp_tx { 216 status = "okay"; 217 218 pinctrl-names = "default"; 219 pinctrl-0 = <&dptx_pin>; 220 221 ports { 222 #address-cells = <1>; 223 #size-cells = <0>; 224 225 port@0 { 226 reg = <0>; 227 dptx_in: endpoint { 228 remote-endpoint = <&dp_intf1_out>; 229 }; 230 }; 231 232 port@1 { 233 reg = <1>; 234 dptx_out: endpoint { 235 data-lanes = <0 1 2 3>; 236 }; 237 }; 238 }; 239}; 240 241&gpu { 242 status = "okay"; 243 mali-supply = <&mt6315_7_vbuck1>; 244}; 245 246&i2c0 { 247 status = "okay"; 248 249 clock-frequency = <400000>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&i2c0_pins>; 252}; 253 254&i2c1 { 255 status = "okay"; 256 257 clock-frequency = <400000>; 258 i2c-scl-internal-delay-ns = <12500>; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&i2c1_pins>; 261 262 trackpad@15 { 263 compatible = "elan,ekth3000"; 264 reg = <0x15>; 265 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&trackpad_pins>; 268 vcc-supply = <&pp3300_s3>; 269 wakeup-source; 270 }; 271}; 272 273&i2c2 { 274 status = "okay"; 275 276 clock-frequency = <400000>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&i2c2_pins>; 279 280 audio_codec: codec@1a { 281 /* Realtek RT5682i or RT5682s, sharing the same configuration */ 282 reg = <0x1a>; 283 interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; 284 realtek,jd-src = <1>; 285 286 AVDD-supply = <&mt6359_vio18_ldo_reg>; 287 MICVDD-supply = <&pp3300_z2>; 288 VBAT-supply = <&pp3300_z5>; 289 }; 290}; 291 292&i2c3 { 293 status = "okay"; 294 295 clock-frequency = <400000>; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&i2c3_pins>; 298 299 tpm@50 { 300 compatible = "google,cr50"; 301 reg = <0x50>; 302 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&cr50_int>; 305 }; 306}; 307 308&i2c4 { 309 status = "okay"; 310 311 clock-frequency = <400000>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&i2c4_pins>; 314 315 ts_10: touchscreen@10 { 316 compatible = "hid-over-i2c"; 317 reg = <0x10>; 318 hid-descr-addr = <0x0001>; 319 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&touchscreen_pins>; 322 post-power-on-delay-ms = <10>; 323 vdd-supply = <&pp3300_s3>; 324 status = "disabled"; 325 }; 326}; 327 328&i2c5 { 329 status = "okay"; 330 331 clock-frequency = <400000>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&i2c5_pins>; 334}; 335 336&i2c7 { 337 status = "okay"; 338 339 clock-frequency = <400000>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&i2c7_pins>; 342 343 pmic@34 { 344 #interrupt-cells = <1>; 345 compatible = "mediatek,mt6360"; 346 reg = <0x34>; 347 interrupt-controller; 348 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 349 interrupt-names = "IRQB"; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&subpmic_default>; 352 wakeup-source; 353 }; 354}; 355 356&mmc0 { 357 status = "okay"; 358 359 bus-width = <8>; 360 cap-mmc-highspeed; 361 cap-mmc-hw-reset; 362 hs400-ds-delay = <0x14c11>; 363 max-frequency = <200000000>; 364 mmc-hs200-1_8v; 365 mmc-hs400-1_8v; 366 no-sdio; 367 no-sd; 368 non-removable; 369 pinctrl-names = "default", "state_uhs"; 370 pinctrl-0 = <&mmc0_pins_default>; 371 pinctrl-1 = <&mmc0_pins_uhs>; 372 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 373 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 374}; 375 376&mmc1 { 377 status = "okay"; 378 379 bus-width = <4>; 380 cap-sd-highspeed; 381 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 382 max-frequency = <200000000>; 383 no-mmc; 384 no-sdio; 385 pinctrl-names = "default", "state_uhs"; 386 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 387 pinctrl-1 = <&mmc1_pins_default>; 388 sd-uhs-sdr50; 389 sd-uhs-sdr104; 390 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 391 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 392}; 393 394&mt6359codec { 395 mediatek,dmic-mode = <1>; /* one-wire */ 396 mediatek,mic-type-0 = <2>; /* DMIC */ 397}; 398 399/* for CPU-L */ 400&mt6359_vcore_buck_reg { 401 regulator-always-on; 402}; 403 404/* for CORE */ 405&mt6359_vgpu11_buck_reg { 406 regulator-always-on; 407}; 408 409&mt6359_vgpu11_sshub_buck_reg { 410 regulator-always-on; 411 regulator-min-microvolt = <550000>; 412 regulator-max-microvolt = <550000>; 413}; 414 415/* for CORE SRAM */ 416&mt6359_vpu_buck_reg { 417 regulator-always-on; 418}; 419 420&mt6359_vrf12_ldo_reg { 421 regulator-always-on; 422}; 423 424/* for GPU SRAM */ 425&mt6359_vsram_others_ldo_reg { 426 regulator-always-on; 427 regulator-min-microvolt = <750000>; 428 regulator-max-microvolt = <750000>; 429}; 430 431&mt6359_vufs_ldo_reg { 432 regulator-always-on; 433}; 434 435&nor_flash { 436 status = "okay"; 437 438 pinctrl-names = "default"; 439 pinctrl-0 = <&nor_pins_default>; 440 441 flash@0 { 442 compatible = "jedec,spi-nor"; 443 reg = <0>; 444 spi-max-frequency = <52000000>; 445 spi-rx-bus-width = <2>; 446 spi-tx-bus-width = <2>; 447 }; 448}; 449 450&pio { 451 mediatek,rsel-resistance-in-si-unit; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pio_default>; 454 455 /* 144 lines */ 456 gpio-line-names = 457 "I2S_SPKR_MCLK", 458 "I2S_SPKR_DATAIN", 459 "I2S_SPKR_LRCK", 460 "I2S_SPKR_BCLK", 461 "EC_AP_INT_ODL", 462 /* 463 * AP_FLASH_WP_L is crossystem ABI. Schematics 464 * call it AP_FLASH_WP_ODL. 465 */ 466 "AP_FLASH_WP_L", 467 "TCHPAD_INT_ODL", 468 "EDP_HPD_1V8", 469 "AP_I2C_CAM_SDA", 470 "AP_I2C_CAM_SCL", 471 "AP_I2C_TCHPAD_SDA_1V8", 472 "AP_I2C_TCHPAD_SCL_1V8", 473 "AP_I2C_AUD_SDA", 474 "AP_I2C_AUD_SCL", 475 "AP_I2C_TPM_SDA_1V8", 476 "AP_I2C_TPM_SCL_1V8", 477 "AP_I2C_TCHSCR_SDA_1V8", 478 "AP_I2C_TCHSCR_SCL_1V8", 479 "EC_AP_HPD_OD", 480 "", 481 "PCIE_NVME_RST_L", 482 "PCIE_NVME_CLKREQ_ODL", 483 "PCIE_RST_1V8_L", 484 "PCIE_CLKREQ_1V8_ODL", 485 "PCIE_WAKE_1V8_ODL", 486 "CLK_24M_CAM0", 487 "CAM1_SEN_EN", 488 "AP_I2C_PWR_SCL_1V8", 489 "AP_I2C_PWR_SDA_1V8", 490 "AP_I2C_MISC_SCL", 491 "AP_I2C_MISC_SDA", 492 "EN_PP5000_HDMI_X", 493 "AP_HDMITX_HTPLG", 494 "", 495 "AP_HDMITX_SCL_1V8", 496 "AP_HDMITX_SDA_1V8", 497 "AP_RTC_CLK32K", 498 "AP_EC_WATCHDOG_L", 499 "SRCLKENA0", 500 "SRCLKENA1", 501 "PWRAP_SPI0_CS_L", 502 "PWRAP_SPI0_CK", 503 "PWRAP_SPI0_MOSI", 504 "PWRAP_SPI0_MISO", 505 "SPMI_SCL", 506 "SPMI_SDA", 507 "", 508 "", 509 "", 510 "I2S_HP_DATAIN", 511 "I2S_HP_MCLK", 512 "I2S_HP_BCK", 513 "I2S_HP_LRCK", 514 "I2S_HP_DATAOUT", 515 "SD_CD_ODL", 516 "EN_PP3300_DISP_X", 517 "TCHSCR_RST_1V8_L", 518 "TCHSCR_REPORT_DISABLE", 519 "EN_PP3300_WLAN_X", 520 "BT_KILL_1V8_L", 521 "I2S_SPKR_DATAOUT", 522 "WIFI_KILL_1V8_L", 523 "BEEP_ON", 524 "SCP_I2C_SENSOR_SCL_1V8", 525 "SCP_I2C_SENSOR_SDA_1V8", 526 "", 527 "", 528 "", 529 "", 530 "AUD_CLK_MOSI", 531 "AUD_SYNC_MOSI", 532 "AUD_DAT_MOSI0", 533 "AUD_DAT_MOSI1", 534 "AUD_DAT_MISO0", 535 "AUD_DAT_MISO1", 536 "AUD_DAT_MISO2", 537 "SCP_VREQ_VAO", 538 "AP_SPI_GSC_TPM_CLK", 539 "AP_SPI_GSC_TPM_MOSI", 540 "AP_SPI_GSC_TPM_CS_L", 541 "AP_SPI_GSC_TPM_MISO", 542 "EN_PP1000_CAM_X", 543 "AP_EDP_BKLTEN", 544 "", 545 "USB3_HUB_RST_L", 546 "", 547 "WLAN_ALERT_ODL", 548 "EC_IN_RW_ODL", 549 "GSC_AP_INT_ODL", 550 "HP_INT_ODL", 551 "CAM0_RST_L", 552 "CAM1_RST_L", 553 "TCHSCR_INT_1V8_L", 554 "CAM1_DET_L", 555 "RST_ALC1011_L", 556 "", 557 "", 558 "BL_PWM_1V8", 559 "UART_AP_TX_DBG_RX", 560 "UART_DBG_TX_AP_RX", 561 "EN_SPKR", 562 "AP_EC_WARM_RST_REQ", 563 "UART_SCP_TX_DBGCON_RX", 564 "UART_DBGCON_TX_SCP_RX", 565 "", 566 "", 567 "KPCOL0", 568 "", 569 "MT6315_GPU_INT", 570 "MT6315_PROC_BC_INT", 571 "SD_CMD", 572 "SD_CLK", 573 "SD_DAT0", 574 "SD_DAT1", 575 "SD_DAT2", 576 "SD_DAT3", 577 "EMMC_DAT7", 578 "EMMC_DAT6", 579 "EMMC_DAT5", 580 "EMMC_DAT4", 581 "EMMC_RSTB", 582 "EMMC_CMD", 583 "EMMC_CLK", 584 "EMMC_DAT3", 585 "EMMC_DAT2", 586 "EMMC_DAT1", 587 "EMMC_DAT0", 588 "EMMC_DSL", 589 "", 590 "", 591 "MT6360_INT_ODL", 592 "SCP_JTAG0_TRSTN", 593 "AP_SPI_EC_CS_L", 594 "AP_SPI_EC_CLK", 595 "AP_SPI_EC_MOSI", 596 "AP_SPI_EC_MISO", 597 "SCP_JTAG0_TMS", 598 "SCP_JTAG0_TCK", 599 "SCP_JTAG0_TDO", 600 "SCP_JTAG0_TDI", 601 "AP_SPI_FLASH_CS_L", 602 "AP_SPI_FLASH_CLK", 603 "AP_SPI_FLASH_MOSI", 604 "AP_SPI_FLASH_MISO"; 605 606 aud_pins_default: audio-default-pins { 607 pins-cmd-dat { 608 pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, 609 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, 610 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, 611 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, 612 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, 613 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, 614 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>, 615 <PINMUX_GPIO0__FUNC_TDMIN_MCK>, 616 <PINMUX_GPIO1__FUNC_TDMIN_DI>, 617 <PINMUX_GPIO2__FUNC_TDMIN_LRCK>, 618 <PINMUX_GPIO3__FUNC_TDMIN_BCK>, 619 <PINMUX_GPIO60__FUNC_I2SO2_D0>, 620 <PINMUX_GPIO49__FUNC_I2SIN_D0>, 621 <PINMUX_GPIO50__FUNC_I2SO1_MCK>, 622 <PINMUX_GPIO51__FUNC_I2SO1_BCK>, 623 <PINMUX_GPIO52__FUNC_I2SO1_WS>, 624 <PINMUX_GPIO53__FUNC_I2SO1_D0>; 625 }; 626 627 pins-hp-jack-int-odl { 628 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>; 629 input-enable; 630 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 631 }; 632 }; 633 634 cr50_int: cr50-irq-default-pins { 635 pins-gsc-ap-int-odl { 636 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 637 input-enable; 638 }; 639 }; 640 641 cros_ec_int: cros-ec-irq-default-pins { 642 pins-ec-ap-int-odl { 643 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 644 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 645 input-enable; 646 }; 647 }; 648 649 edptx_pins_default: edptx-default-pins { 650 pins-cmd-dat { 651 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 652 bias-pull-up; 653 }; 654 }; 655 656 dptx_pin: dptx-default-pins { 657 pins-cmd-dat { 658 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 659 bias-pull-up; 660 }; 661 }; 662 663 i2c0_pins: i2c0-default-pins { 664 pins-bus { 665 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 666 <PINMUX_GPIO9__FUNC_SCL0>; 667 bias-disable; 668 drive-strength-microamp = <1000>; 669 }; 670 }; 671 672 i2c1_pins: i2c1-default-pins { 673 pins-bus { 674 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 675 <PINMUX_GPIO11__FUNC_SCL1>; 676 bias-pull-up = <1000>; 677 drive-strength-microamp = <1000>; 678 }; 679 }; 680 681 i2c2_pins: i2c2-default-pins { 682 pins-bus { 683 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 684 <PINMUX_GPIO13__FUNC_SCL2>; 685 bias-disable; 686 drive-strength-microamp = <1000>; 687 }; 688 }; 689 690 i2c3_pins: i2c3-default-pins { 691 pins-bus { 692 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 693 <PINMUX_GPIO15__FUNC_SCL3>; 694 bias-pull-up = <1000>; 695 drive-strength-microamp = <1000>; 696 }; 697 }; 698 699 i2c4_pins: i2c4-default-pins { 700 pins-bus { 701 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 702 <PINMUX_GPIO17__FUNC_SCL4>; 703 bias-pull-up = <1000>; 704 drive-strength = <4>; 705 }; 706 }; 707 708 i2c5_pins: i2c5-default-pins { 709 pins-bus { 710 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 711 <PINMUX_GPIO30__FUNC_SDA5>; 712 bias-disable; 713 drive-strength-microamp = <1000>; 714 }; 715 }; 716 717 i2c7_pins: i2c7-default-pins { 718 pins-bus { 719 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 720 <PINMUX_GPIO28__FUNC_SDA7>; 721 bias-disable; 722 }; 723 }; 724 725 mmc0_pins_default: mmc0-default-pins { 726 pins-cmd-dat { 727 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 728 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 729 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 730 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 731 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 732 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 733 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 734 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 735 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 736 input-enable; 737 drive-strength = <6>; 738 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 739 }; 740 741 pins-clk { 742 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 743 drive-strength = <6>; 744 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 745 }; 746 747 pins-rst { 748 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 749 drive-strength = <6>; 750 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 751 }; 752 }; 753 754 mmc0_pins_uhs: mmc0-uhs-pins { 755 pins-cmd-dat { 756 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 757 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 758 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 759 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 760 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 761 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 762 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 763 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 764 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 765 input-enable; 766 drive-strength = <8>; 767 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 768 }; 769 770 pins-clk { 771 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 772 drive-strength = <8>; 773 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 774 }; 775 776 pins-ds { 777 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 778 drive-strength = <8>; 779 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 780 }; 781 782 pins-rst { 783 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 784 drive-strength = <8>; 785 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 786 }; 787 }; 788 789 mmc1_pins_detect: mmc1-detect-pins { 790 pins-insert { 791 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 792 bias-pull-up; 793 }; 794 }; 795 796 mmc1_pins_default: mmc1-default-pins { 797 pins-cmd-dat { 798 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 799 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 800 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 801 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 802 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 803 input-enable; 804 drive-strength = <8>; 805 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 806 }; 807 808 pins-clk { 809 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 810 drive-strength = <8>; 811 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 812 }; 813 }; 814 815 nor_pins_default: nor-default-pins { 816 pins-ck-io { 817 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 818 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 819 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 820 drive-strength = <6>; 821 bias-pull-down; 822 }; 823 824 pins-cs { 825 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 826 drive-strength = <6>; 827 bias-pull-up; 828 }; 829 }; 830 831 pio_default: pio-default-pins { 832 pins-wifi-enable { 833 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 834 output-high; 835 drive-strength = <14>; 836 }; 837 838 pins-low-power-pd { 839 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 840 <PINMUX_GPIO26__FUNC_GPIO26>, 841 <PINMUX_GPIO46__FUNC_GPIO46>, 842 <PINMUX_GPIO47__FUNC_GPIO47>, 843 <PINMUX_GPIO48__FUNC_GPIO48>, 844 <PINMUX_GPIO65__FUNC_GPIO65>, 845 <PINMUX_GPIO66__FUNC_GPIO66>, 846 <PINMUX_GPIO67__FUNC_GPIO67>, 847 <PINMUX_GPIO68__FUNC_GPIO68>, 848 <PINMUX_GPIO128__FUNC_GPIO128>, 849 <PINMUX_GPIO129__FUNC_GPIO129>; 850 input-enable; 851 bias-pull-down; 852 }; 853 854 pins-low-power-pupd { 855 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 856 <PINMUX_GPIO78__FUNC_GPIO78>, 857 <PINMUX_GPIO79__FUNC_GPIO79>, 858 <PINMUX_GPIO80__FUNC_GPIO80>, 859 <PINMUX_GPIO83__FUNC_GPIO83>, 860 <PINMUX_GPIO85__FUNC_GPIO85>, 861 <PINMUX_GPIO90__FUNC_GPIO90>, 862 <PINMUX_GPIO91__FUNC_GPIO91>, 863 <PINMUX_GPIO93__FUNC_GPIO93>, 864 <PINMUX_GPIO94__FUNC_GPIO94>, 865 <PINMUX_GPIO95__FUNC_GPIO95>, 866 <PINMUX_GPIO96__FUNC_GPIO96>, 867 <PINMUX_GPIO104__FUNC_GPIO104>, 868 <PINMUX_GPIO105__FUNC_GPIO105>, 869 <PINMUX_GPIO107__FUNC_GPIO107>; 870 input-enable; 871 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 872 }; 873 }; 874 875 rt1019p_pins_default: rt1019p-default-pins { 876 pins-amp-sdb { 877 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>; 878 output-low; 879 }; 880 }; 881 882 scp_pins: scp-default-pins { 883 pins-vreq { 884 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 885 bias-disable; 886 input-enable; 887 }; 888 }; 889 890 spi0_pins: spi0-default-pins { 891 pins-cs-mosi-clk { 892 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 893 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 894 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 895 bias-disable; 896 }; 897 898 pins-miso { 899 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 900 bias-pull-down; 901 }; 902 }; 903 904 subpmic_default: subpmic-default-pins { 905 subpmic_pin_irq: pins-subpmic-int-n { 906 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 907 input-enable; 908 bias-pull-up; 909 }; 910 }; 911 912 trackpad_pins: trackpad-default-pins { 913 pins-int-n { 914 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 915 input-enable; 916 bias-pull-up; 917 }; 918 }; 919 920 touchscreen_pins: touchscreen-default-pins { 921 pins-int-n { 922 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 923 input-enable; 924 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 925 }; 926 pins-rst { 927 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 928 output-high; 929 }; 930 pins-report-sw { 931 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 932 output-low; 933 }; 934 }; 935}; 936 937&pmic { 938 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 939}; 940 941&scp { 942 status = "okay"; 943 944 firmware-name = "mediatek/mt8195/scp.img"; 945 memory-region = <&scp_mem>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&scp_pins>; 948 949 cros-ec-rpmsg { 950 compatible = "google,cros-ec-rpmsg"; 951 mediatek,rpmsg-name = "cros-ec-rpmsg"; 952 }; 953}; 954 955&sound { 956 status = "okay"; 957 958 mediatek,adsp = <&adsp>; 959 mediatek,dai-link = 960 "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE", 961 "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE", 962 "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5"; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&aud_pins_default>; 965}; 966 967&spi0 { 968 status = "okay"; 969 970 pinctrl-names = "default"; 971 pinctrl-0 = <&spi0_pins>; 972 mediatek,pad-select = <0>; 973 974 cros_ec: ec@0 { 975 #address-cells = <1>; 976 #size-cells = <0>; 977 978 compatible = "google,cros-ec-spi"; 979 reg = <0>; 980 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&cros_ec_int>; 983 spi-max-frequency = <3000000>; 984 985 keyboard-backlight { 986 compatible = "google,cros-kbd-led-backlight"; 987 }; 988 989 i2c_tunnel: i2c-tunnel { 990 compatible = "google,cros-ec-i2c-tunnel"; 991 google,remote-bus = <0>; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 }; 995 996 mt_pmic_vmc_ldo_reg: regulator@0 { 997 compatible = "google,cros-ec-regulator"; 998 reg = <0>; 999 regulator-name = "mt_pmic_vmc_ldo"; 1000 regulator-min-microvolt = <1200000>; 1001 regulator-max-microvolt = <3600000>; 1002 }; 1003 1004 mt_pmic_vmch_ldo_reg: regulator@1 { 1005 compatible = "google,cros-ec-regulator"; 1006 reg = <1>; 1007 regulator-name = "mt_pmic_vmch_ldo"; 1008 regulator-min-microvolt = <2700000>; 1009 regulator-max-microvolt = <3600000>; 1010 }; 1011 1012 typec { 1013 compatible = "google,cros-ec-typec"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 1017 usb_c0: connector@0 { 1018 compatible = "usb-c-connector"; 1019 reg = <0>; 1020 power-role = "dual"; 1021 data-role = "host"; 1022 try-power-role = "source"; 1023 }; 1024 1025 usb_c1: connector@1 { 1026 compatible = "usb-c-connector"; 1027 reg = <1>; 1028 power-role = "dual"; 1029 data-role = "host"; 1030 try-power-role = "source"; 1031 }; 1032 }; 1033 }; 1034}; 1035 1036&spmi { 1037 #address-cells = <2>; 1038 #size-cells = <0>; 1039 1040 mt6315@6 { 1041 compatible = "mediatek,mt6315-regulator"; 1042 reg = <0x6 SPMI_USID>; 1043 1044 regulators { 1045 mt6315_6_vbuck1: vbuck1 { 1046 regulator-compatible = "vbuck1"; 1047 regulator-name = "Vbcpu"; 1048 regulator-min-microvolt = <300000>; 1049 regulator-max-microvolt = <1193750>; 1050 regulator-enable-ramp-delay = <256>; 1051 regulator-ramp-delay = <6250>; 1052 regulator-allowed-modes = <0 1 2>; 1053 regulator-always-on; 1054 }; 1055 }; 1056 }; 1057 1058 mt6315@7 { 1059 compatible = "mediatek,mt6315-regulator"; 1060 reg = <0x7 SPMI_USID>; 1061 1062 regulators { 1063 mt6315_7_vbuck1: vbuck1 { 1064 regulator-compatible = "vbuck1"; 1065 regulator-name = "Vgpu"; 1066 regulator-min-microvolt = <625000>; 1067 regulator-max-microvolt = <1193750>; 1068 regulator-enable-ramp-delay = <256>; 1069 regulator-ramp-delay = <6250>; 1070 regulator-allowed-modes = <0 1 2>; 1071 regulator-always-on; 1072 }; 1073 }; 1074 }; 1075}; 1076 1077&u3phy0 { 1078 status = "okay"; 1079}; 1080 1081&u3phy1 { 1082 status = "okay"; 1083}; 1084 1085&u3phy2 { 1086 status = "okay"; 1087}; 1088 1089&u3phy3 { 1090 status = "okay"; 1091}; 1092 1093&uart0 { 1094 status = "okay"; 1095}; 1096 1097&xhci0 { 1098 status = "okay"; 1099 1100 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1101 vbus-supply = <&usb_vbus>; 1102}; 1103 1104&xhci1 { 1105 status = "okay"; 1106 1107 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1108 vbus-supply = <&usb_vbus>; 1109}; 1110 1111&xhci2 { 1112 status = "okay"; 1113 1114 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1115 vbus-supply = <&usb_vbus>; 1116}; 1117 1118&xhci3 { 1119 status = "okay"; 1120 1121 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1122 usb2-lpm-disable; 1123 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1124 vbus-supply = <&usb_vbus>; 1125}; 1126 1127#include <arm/cros-ec-keyboard.dtsi> 1128#include <arm/cros-ec-sbs.dtsi> 1129 1130&keyboard_controller { 1131 function-row-physmap = < 1132 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1133 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1134 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1135 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1136 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1137 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1138 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1139 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1140 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1141 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1142 >; 1143 1144 linux,keymap = < 1145 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1146 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1147 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1148 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1149 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 1150 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 1151 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 1152 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1153 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1154 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1155 1156 CROS_STD_MAIN_KEYMAP 1157 >; 1158}; 1159