1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include "mt8195.dtsi"
8#include "mt6359.dtsi"
9
10/ {
11	aliases {
12		mmc0 = &mmc0;
13		serial0 = &uart0;
14	};
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	memory@40000000 {
21		device_type = "memory";
22		reg = <0 0x40000000 0 0x80000000>;
23	};
24
25	/* system wide LDO 3.3V power rail */
26	pp3300_z5: regulator-pp3300-ldo-z5 {
27		compatible = "regulator-fixed";
28		regulator-name = "pp3300_ldo_z5";
29		regulator-always-on;
30		regulator-boot-on;
31		regulator-min-microvolt = <3300000>;
32		regulator-max-microvolt = <3300000>;
33		vin-supply = <&ppvar_sys>;
34	};
35
36	/* separately switched 3.3V power rail */
37	pp3300_s3: regulator-pp3300-s3 {
38		compatible = "regulator-fixed";
39		regulator-name = "pp3300_s3";
40		/* automatically sequenced by PMIC EXT_PMIC_EN2 */
41		regulator-always-on;
42		regulator-boot-on;
43		regulator-min-microvolt = <3300000>;
44		regulator-max-microvolt = <3300000>;
45		vin-supply = <&pp3300_z2>;
46	};
47
48	/* system wide 3.3V power rail */
49	pp3300_z2: regulator-pp3300-z2 {
50		compatible = "regulator-fixed";
51		regulator-name = "pp3300_z2";
52		/* EN pin tied to pp4200_z2, which is controlled by EC */
53		regulator-always-on;
54		regulator-boot-on;
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57		vin-supply = <&ppvar_sys>;
58	};
59
60	/* system wide 4.2V power rail */
61	pp4200_z2: regulator-pp4200-z2 {
62		compatible = "regulator-fixed";
63		regulator-name = "pp4200_z2";
64		/* controlled by EC */
65		regulator-always-on;
66		regulator-boot-on;
67		regulator-min-microvolt = <4200000>;
68		regulator-max-microvolt = <4200000>;
69		vin-supply = <&ppvar_sys>;
70	};
71
72	/* system wide switching 5.0V power rail */
73	pp5000_s5: regulator-pp5000-s5 {
74		compatible = "regulator-fixed";
75		regulator-name = "pp5000_s5";
76		/* controlled by EC */
77		regulator-always-on;
78		regulator-boot-on;
79		regulator-min-microvolt = <5000000>;
80		regulator-max-microvolt = <5000000>;
81		vin-supply = <&ppvar_sys>;
82	};
83
84	/* system wide semi-regulated power rail from battery or USB */
85	ppvar_sys: regulator-ppvar-sys {
86		compatible = "regulator-fixed";
87		regulator-name = "ppvar_sys";
88		regulator-always-on;
89		regulator-boot-on;
90	};
91};
92
93&mmc0 {
94	status = "okay";
95
96	bus-width = <8>;
97	cap-mmc-highspeed;
98	cap-mmc-hw-reset;
99	hs400-ds-delay = <0x14c11>;
100	max-frequency = <200000000>;
101	mmc-hs200-1_8v;
102	mmc-hs400-1_8v;
103	no-sdio;
104	no-sd;
105	non-removable;
106	pinctrl-names = "default", "state_uhs";
107	pinctrl-0 = <&mmc0_pins_default>;
108	pinctrl-1 = <&mmc0_pins_uhs>;
109	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
110	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
111};
112
113/* for CPU-L */
114&mt6359_vcore_buck_reg {
115	regulator-always-on;
116};
117
118/* for CORE */
119&mt6359_vgpu11_buck_reg {
120	regulator-always-on;
121};
122
123&mt6359_vgpu11_sshub_buck_reg {
124	regulator-always-on;
125	regulator-min-microvolt = <550000>;
126	regulator-max-microvolt = <550000>;
127};
128
129/* for CORE SRAM */
130&mt6359_vpu_buck_reg {
131	regulator-always-on;
132};
133
134&mt6359_vrf12_ldo_reg {
135	regulator-always-on;
136};
137
138/* for GPU SRAM */
139&mt6359_vsram_others_ldo_reg {
140	regulator-always-on;
141	regulator-min-microvolt = <750000>;
142	regulator-max-microvolt = <750000>;
143};
144
145&mt6359_vufs_ldo_reg {
146	regulator-always-on;
147};
148
149&pio {
150	mediatek,rsel-resistance-in-si-unit;
151	pinctrl-names = "default";
152	pinctrl-0 = <&pio_default>;
153
154	/* 144 lines */
155	gpio-line-names =
156		"I2S_SPKR_MCLK",
157		"I2S_SPKR_DATAIN",
158		"I2S_SPKR_LRCK",
159		"I2S_SPKR_BCLK",
160		"EC_AP_INT_ODL",
161		/*
162		 * AP_FLASH_WP_L is crossystem ABI. Schematics
163		 * call it AP_FLASH_WP_ODL.
164		 */
165		"AP_FLASH_WP_L",
166		"TCHPAD_INT_ODL",
167		"EDP_HPD_1V8",
168		"AP_I2C_CAM_SDA",
169		"AP_I2C_CAM_SCL",
170		"AP_I2C_TCHPAD_SDA_1V8",
171		"AP_I2C_TCHPAD_SCL_1V8",
172		"AP_I2C_AUD_SDA",
173		"AP_I2C_AUD_SCL",
174		"AP_I2C_TPM_SDA_1V8",
175		"AP_I2C_TPM_SCL_1V8",
176		"AP_I2C_TCHSCR_SDA_1V8",
177		"AP_I2C_TCHSCR_SCL_1V8",
178		"EC_AP_HPD_OD",
179		"",
180		"PCIE_NVME_RST_L",
181		"PCIE_NVME_CLKREQ_ODL",
182		"PCIE_RST_1V8_L",
183		"PCIE_CLKREQ_1V8_ODL",
184		"PCIE_WAKE_1V8_ODL",
185		"CLK_24M_CAM0",
186		"CAM1_SEN_EN",
187		"AP_I2C_PWR_SCL_1V8",
188		"AP_I2C_PWR_SDA_1V8",
189		"AP_I2C_MISC_SCL",
190		"AP_I2C_MISC_SDA",
191		"EN_PP5000_HDMI_X",
192		"AP_HDMITX_HTPLG",
193		"",
194		"AP_HDMITX_SCL_1V8",
195		"AP_HDMITX_SDA_1V8",
196		"AP_RTC_CLK32K",
197		"AP_EC_WATCHDOG_L",
198		"SRCLKENA0",
199		"SRCLKENA1",
200		"PWRAP_SPI0_CS_L",
201		"PWRAP_SPI0_CK",
202		"PWRAP_SPI0_MOSI",
203		"PWRAP_SPI0_MISO",
204		"SPMI_SCL",
205		"SPMI_SDA",
206		"",
207		"",
208		"",
209		"I2S_HP_DATAIN",
210		"I2S_HP_MCLK",
211		"I2S_HP_BCK",
212		"I2S_HP_LRCK",
213		"I2S_HP_DATAOUT",
214		"SD_CD_ODL",
215		"EN_PP3300_DISP_X",
216		"TCHSCR_RST_1V8_L",
217		"TCHSCR_REPORT_DISABLE",
218		"EN_PP3300_WLAN_X",
219		"BT_KILL_1V8_L",
220		"I2S_SPKR_DATAOUT",
221		"WIFI_KILL_1V8_L",
222		"BEEP_ON",
223		"SCP_I2C_SENSOR_SCL_1V8",
224		"SCP_I2C_SENSOR_SDA_1V8",
225		"",
226		"",
227		"",
228		"",
229		"AUD_CLK_MOSI",
230		"AUD_SYNC_MOSI",
231		"AUD_DAT_MOSI0",
232		"AUD_DAT_MOSI1",
233		"AUD_DAT_MISO0",
234		"AUD_DAT_MISO1",
235		"AUD_DAT_MISO2",
236		"SCP_VREQ_VAO",
237		"AP_SPI_GSC_TPM_CLK",
238		"AP_SPI_GSC_TPM_MOSI",
239		"AP_SPI_GSC_TPM_CS_L",
240		"AP_SPI_GSC_TPM_MISO",
241		"EN_PP1000_CAM_X",
242		"AP_EDP_BKLTEN",
243		"",
244		"USB3_HUB_RST_L",
245		"",
246		"WLAN_ALERT_ODL",
247		"EC_IN_RW_ODL",
248		"GSC_AP_INT_ODL",
249		"HP_INT_ODL",
250		"CAM0_RST_L",
251		"CAM1_RST_L",
252		"TCHSCR_INT_1V8_L",
253		"CAM1_DET_L",
254		"RST_ALC1011_L",
255		"",
256		"",
257		"BL_PWM_1V8",
258		"UART_AP_TX_DBG_RX",
259		"UART_DBG_TX_AP_RX",
260		"EN_SPKR",
261		"AP_EC_WARM_RST_REQ",
262		"UART_SCP_TX_DBGCON_RX",
263		"UART_DBGCON_TX_SCP_RX",
264		"",
265		"",
266		"KPCOL0",
267		"",
268		"MT6315_GPU_INT",
269		"MT6315_PROC_BC_INT",
270		"SD_CMD",
271		"SD_CLK",
272		"SD_DAT0",
273		"SD_DAT1",
274		"SD_DAT2",
275		"SD_DAT3",
276		"EMMC_DAT7",
277		"EMMC_DAT6",
278		"EMMC_DAT5",
279		"EMMC_DAT4",
280		"EMMC_RSTB",
281		"EMMC_CMD",
282		"EMMC_CLK",
283		"EMMC_DAT3",
284		"EMMC_DAT2",
285		"EMMC_DAT1",
286		"EMMC_DAT0",
287		"EMMC_DSL",
288		"",
289		"",
290		"MT6360_INT_ODL",
291		"SCP_JTAG0_TRSTN",
292		"AP_SPI_EC_CS_L",
293		"AP_SPI_EC_CLK",
294		"AP_SPI_EC_MOSI",
295		"AP_SPI_EC_MISO",
296		"SCP_JTAG0_TMS",
297		"SCP_JTAG0_TCK",
298		"SCP_JTAG0_TDO",
299		"SCP_JTAG0_TDI",
300		"AP_SPI_FLASH_CS_L",
301		"AP_SPI_FLASH_CLK",
302		"AP_SPI_FLASH_MOSI",
303		"AP_SPI_FLASH_MISO";
304
305	mmc0_pins_default: mmc0-default-pins {
306		pins-cmd-dat {
307			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
308				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
309				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
310				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
311				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
312				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
313				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
314				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
315				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
316			input-enable;
317			drive-strength = <6>;
318			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
319		};
320
321		pins-clk {
322			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
323			drive-strength = <6>;
324			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
325		};
326
327		pins-rst {
328			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
329			drive-strength = <6>;
330			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
331		};
332	};
333
334	mmc0_pins_uhs: mmc0-uhs-pins {
335		pins-cmd-dat {
336			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
337				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
338				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
339				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
340				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
341				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
342				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
343				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
344				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
345			input-enable;
346			drive-strength = <8>;
347			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
348		};
349
350		pins-clk {
351			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
352			drive-strength = <8>;
353			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
354		};
355
356		pins-ds {
357			pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
358			drive-strength = <8>;
359			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
360		};
361
362		pins-rst {
363			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
364			drive-strength = <8>;
365			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
366		};
367	};
368
369	pio_default: pio-default-pins {
370		pins-wifi-enable {
371			pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
372			output-high;
373			drive-strength = <14>;
374		};
375
376		pins-low-power-pd {
377			pinmux = <PINMUX_GPIO25__FUNC_GPIO25>,
378				 <PINMUX_GPIO26__FUNC_GPIO26>,
379				 <PINMUX_GPIO46__FUNC_GPIO46>,
380				 <PINMUX_GPIO47__FUNC_GPIO47>,
381				 <PINMUX_GPIO48__FUNC_GPIO48>,
382				 <PINMUX_GPIO65__FUNC_GPIO65>,
383				 <PINMUX_GPIO66__FUNC_GPIO66>,
384				 <PINMUX_GPIO67__FUNC_GPIO67>,
385				 <PINMUX_GPIO68__FUNC_GPIO68>,
386				 <PINMUX_GPIO128__FUNC_GPIO128>,
387				 <PINMUX_GPIO129__FUNC_GPIO129>;
388			input-enable;
389			bias-pull-down;
390		};
391
392		pins-low-power-pupd {
393			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
394				 <PINMUX_GPIO78__FUNC_GPIO78>,
395				 <PINMUX_GPIO79__FUNC_GPIO79>,
396				 <PINMUX_GPIO80__FUNC_GPIO80>,
397				 <PINMUX_GPIO83__FUNC_GPIO83>,
398				 <PINMUX_GPIO85__FUNC_GPIO85>,
399				 <PINMUX_GPIO90__FUNC_GPIO90>,
400				 <PINMUX_GPIO91__FUNC_GPIO91>,
401				 <PINMUX_GPIO93__FUNC_GPIO93>,
402				 <PINMUX_GPIO94__FUNC_GPIO94>,
403				 <PINMUX_GPIO95__FUNC_GPIO95>,
404				 <PINMUX_GPIO96__FUNC_GPIO96>,
405				 <PINMUX_GPIO104__FUNC_GPIO104>,
406				 <PINMUX_GPIO105__FUNC_GPIO105>,
407				 <PINMUX_GPIO107__FUNC_GPIO107>;
408			input-enable;
409			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
410		};
411	};
412};
413
414&pmic {
415	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
416};
417
418&uart0 {
419	status = "okay";
420};
421