1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 backlight_lcd0: backlight-lcd0 { 26 compatible = "pwm-backlight"; 27 brightness-levels = <0 1023>; 28 default-brightness-level = <576>; 29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>; 30 num-interpolated-steps = <1023>; 31 pwms = <&disp_pwm0 0 500000>; 32 power-supply = <&ppvar_sys>; 33 }; 34 35 chosen { 36 stdout-path = "serial0:115200n8"; 37 }; 38 39 dmic-codec { 40 compatible = "dmic-codec"; 41 num-channels = <2>; 42 wakeup-delay-ms = <50>; 43 }; 44 45 memory@40000000 { 46 device_type = "memory"; 47 reg = <0 0x40000000 0 0x80000000>; 48 }; 49 50 /* system wide LDO 3.3V power rail */ 51 pp3300_z5: regulator-pp3300-ldo-z5 { 52 compatible = "regulator-fixed"; 53 regulator-name = "pp3300_ldo_z5"; 54 regulator-always-on; 55 regulator-boot-on; 56 regulator-min-microvolt = <3300000>; 57 regulator-max-microvolt = <3300000>; 58 vin-supply = <&ppvar_sys>; 59 }; 60 61 /* separately switched 3.3V power rail */ 62 pp3300_s3: regulator-pp3300-s3 { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp3300_s3"; 65 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 66 regulator-always-on; 67 regulator-boot-on; 68 regulator-min-microvolt = <3300000>; 69 regulator-max-microvolt = <3300000>; 70 vin-supply = <&pp3300_z2>; 71 }; 72 73 /* system wide 3.3V power rail */ 74 pp3300_z2: regulator-pp3300-z2 { 75 compatible = "regulator-fixed"; 76 regulator-name = "pp3300_z2"; 77 /* EN pin tied to pp4200_z2, which is controlled by EC */ 78 regulator-always-on; 79 regulator-boot-on; 80 regulator-min-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>; 82 vin-supply = <&ppvar_sys>; 83 }; 84 85 /* system wide 4.2V power rail */ 86 pp4200_z2: regulator-pp4200-z2 { 87 compatible = "regulator-fixed"; 88 regulator-name = "pp4200_z2"; 89 /* controlled by EC */ 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <4200000>; 93 regulator-max-microvolt = <4200000>; 94 vin-supply = <&ppvar_sys>; 95 }; 96 97 /* system wide switching 5.0V power rail */ 98 pp5000_s5: regulator-pp5000-s5 { 99 compatible = "regulator-fixed"; 100 regulator-name = "pp5000_s5"; 101 /* controlled by EC */ 102 regulator-always-on; 103 regulator-boot-on; 104 regulator-min-microvolt = <5000000>; 105 regulator-max-microvolt = <5000000>; 106 vin-supply = <&ppvar_sys>; 107 }; 108 109 /* system wide semi-regulated power rail from battery or USB */ 110 ppvar_sys: regulator-ppvar-sys { 111 compatible = "regulator-fixed"; 112 regulator-name = "ppvar_sys"; 113 regulator-always-on; 114 regulator-boot-on; 115 }; 116 117 usb_vbus: regulator-5v0-usb-vbus { 118 compatible = "regulator-fixed"; 119 regulator-name = "usb-vbus"; 120 regulator-min-microvolt = <5000000>; 121 regulator-max-microvolt = <5000000>; 122 enable-active-high; 123 regulator-always-on; 124 }; 125 126 reserved_memory: reserved-memory { 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges; 130 131 scp_mem: memory@50000000 { 132 compatible = "shared-dma-pool"; 133 reg = <0 0x50000000 0 0x2900000>; 134 no-map; 135 }; 136 137 adsp_mem: memory@60000000 { 138 compatible = "shared-dma-pool"; 139 reg = <0 0x60000000 0 0xd80000>; 140 no-map; 141 }; 142 143 afe_mem: memory@60d80000 { 144 compatible = "shared-dma-pool"; 145 reg = <0 0x60d80000 0 0x100000>; 146 no-map; 147 }; 148 149 adsp_device_mem: memory@60e80000 { 150 compatible = "shared-dma-pool"; 151 reg = <0 0x60e80000 0 0x280000>; 152 no-map; 153 }; 154 }; 155 156 spk_amplifier: rt1019p { 157 compatible = "realtek,rt1019p"; 158 label = "rt1019p"; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&rt1019p_pins_default>; 161 sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; 162 }; 163}; 164 165&adsp { 166 status = "okay"; 167 168 memory-region = <&adsp_device_mem>, <&adsp_mem>; 169}; 170 171&afe { 172 status = "okay"; 173 174 mediatek,etdm-in2-cowork-source = <2>; 175 mediatek,etdm-out2-cowork-source = <0>; 176 memory-region = <&afe_mem>; 177}; 178 179&dp_intf0 { 180 status = "okay"; 181 182 port { 183 dp_intf0_out: endpoint { 184 remote-endpoint = <&edp_in>; 185 }; 186 }; 187}; 188 189&dp_intf1 { 190 status = "okay"; 191 192 port { 193 dp_intf1_out: endpoint { 194 remote-endpoint = <&dptx_in>; 195 }; 196 }; 197}; 198 199&edp_tx { 200 status = "okay"; 201 202 pinctrl-names = "default"; 203 pinctrl-0 = <&edptx_pins_default>; 204 205 ports { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 209 port@0 { 210 reg = <0>; 211 edp_in: endpoint { 212 remote-endpoint = <&dp_intf0_out>; 213 }; 214 }; 215 216 port@1 { 217 reg = <1>; 218 edp_out: endpoint { 219 data-lanes = <0 1 2 3>; 220 }; 221 }; 222 }; 223}; 224 225&disp_pwm0 { 226 status = "okay"; 227 228 pinctrl-names = "default"; 229 pinctrl-0 = <&disp_pwm0_pin_default>; 230}; 231 232&dp_tx { 233 status = "okay"; 234 235 pinctrl-names = "default"; 236 pinctrl-0 = <&dptx_pin>; 237 238 ports { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 242 port@0 { 243 reg = <0>; 244 dptx_in: endpoint { 245 remote-endpoint = <&dp_intf1_out>; 246 }; 247 }; 248 249 port@1 { 250 reg = <1>; 251 dptx_out: endpoint { 252 data-lanes = <0 1 2 3>; 253 }; 254 }; 255 }; 256}; 257 258&gpu { 259 status = "okay"; 260 mali-supply = <&mt6315_7_vbuck1>; 261}; 262 263&i2c0 { 264 status = "okay"; 265 266 clock-frequency = <400000>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&i2c0_pins>; 269}; 270 271&i2c1 { 272 status = "okay"; 273 274 clock-frequency = <400000>; 275 i2c-scl-internal-delay-ns = <12500>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&i2c1_pins>; 278 279 trackpad@15 { 280 compatible = "elan,ekth3000"; 281 reg = <0x15>; 282 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&trackpad_pins>; 285 vcc-supply = <&pp3300_s3>; 286 wakeup-source; 287 }; 288}; 289 290&i2c2 { 291 status = "okay"; 292 293 clock-frequency = <400000>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&i2c2_pins>; 296 297 audio_codec: codec@1a { 298 /* Realtek RT5682i or RT5682s, sharing the same configuration */ 299 reg = <0x1a>; 300 interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; 301 realtek,jd-src = <1>; 302 303 AVDD-supply = <&mt6359_vio18_ldo_reg>; 304 MICVDD-supply = <&pp3300_z2>; 305 VBAT-supply = <&pp3300_z5>; 306 }; 307}; 308 309&i2c3 { 310 status = "okay"; 311 312 clock-frequency = <400000>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&i2c3_pins>; 315 316 tpm@50 { 317 compatible = "google,cr50"; 318 reg = <0x50>; 319 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&cr50_int>; 322 }; 323}; 324 325&i2c4 { 326 status = "okay"; 327 328 clock-frequency = <400000>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&i2c4_pins>; 331 332 ts_10: touchscreen@10 { 333 compatible = "hid-over-i2c"; 334 reg = <0x10>; 335 hid-descr-addr = <0x0001>; 336 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&touchscreen_pins>; 339 post-power-on-delay-ms = <10>; 340 vdd-supply = <&pp3300_s3>; 341 status = "disabled"; 342 }; 343}; 344 345&i2c5 { 346 status = "okay"; 347 348 clock-frequency = <400000>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&i2c5_pins>; 351}; 352 353&i2c7 { 354 status = "okay"; 355 356 clock-frequency = <400000>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&i2c7_pins>; 359 360 pmic@34 { 361 #interrupt-cells = <1>; 362 compatible = "mediatek,mt6360"; 363 reg = <0x34>; 364 interrupt-controller; 365 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 366 interrupt-names = "IRQB"; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&subpmic_default>; 369 wakeup-source; 370 }; 371}; 372 373&mmc0 { 374 status = "okay"; 375 376 bus-width = <8>; 377 cap-mmc-highspeed; 378 cap-mmc-hw-reset; 379 hs400-ds-delay = <0x14c11>; 380 max-frequency = <200000000>; 381 mmc-hs200-1_8v; 382 mmc-hs400-1_8v; 383 no-sdio; 384 no-sd; 385 non-removable; 386 pinctrl-names = "default", "state_uhs"; 387 pinctrl-0 = <&mmc0_pins_default>; 388 pinctrl-1 = <&mmc0_pins_uhs>; 389 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 390 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 391}; 392 393&mmc1 { 394 status = "okay"; 395 396 bus-width = <4>; 397 cap-sd-highspeed; 398 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 399 max-frequency = <200000000>; 400 no-mmc; 401 no-sdio; 402 pinctrl-names = "default", "state_uhs"; 403 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 404 pinctrl-1 = <&mmc1_pins_default>; 405 sd-uhs-sdr50; 406 sd-uhs-sdr104; 407 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 408 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 409}; 410 411&mt6359codec { 412 mediatek,dmic-mode = <1>; /* one-wire */ 413 mediatek,mic-type-0 = <2>; /* DMIC */ 414}; 415 416/* for CPU-L */ 417&mt6359_vcore_buck_reg { 418 regulator-always-on; 419}; 420 421/* for CORE */ 422&mt6359_vgpu11_buck_reg { 423 regulator-always-on; 424}; 425 426&mt6359_vgpu11_sshub_buck_reg { 427 regulator-always-on; 428 regulator-min-microvolt = <550000>; 429 regulator-max-microvolt = <550000>; 430}; 431 432/* for CORE SRAM */ 433&mt6359_vpu_buck_reg { 434 regulator-always-on; 435}; 436 437&mt6359_vrf12_ldo_reg { 438 regulator-always-on; 439}; 440 441/* for GPU SRAM */ 442&mt6359_vsram_others_ldo_reg { 443 regulator-always-on; 444 regulator-min-microvolt = <750000>; 445 regulator-max-microvolt = <750000>; 446}; 447 448&mt6359_vufs_ldo_reg { 449 regulator-always-on; 450}; 451 452&nor_flash { 453 status = "okay"; 454 455 pinctrl-names = "default"; 456 pinctrl-0 = <&nor_pins_default>; 457 458 flash@0 { 459 compatible = "jedec,spi-nor"; 460 reg = <0>; 461 spi-max-frequency = <52000000>; 462 spi-rx-bus-width = <2>; 463 spi-tx-bus-width = <2>; 464 }; 465}; 466 467&pcie1 { 468 status = "okay"; 469 470 pinctrl-names = "default"; 471 pinctrl-0 = <&pcie1_pins_default>; 472}; 473 474&pio { 475 mediatek,rsel-resistance-in-si-unit; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pio_default>; 478 479 /* 144 lines */ 480 gpio-line-names = 481 "I2S_SPKR_MCLK", 482 "I2S_SPKR_DATAIN", 483 "I2S_SPKR_LRCK", 484 "I2S_SPKR_BCLK", 485 "EC_AP_INT_ODL", 486 /* 487 * AP_FLASH_WP_L is crossystem ABI. Schematics 488 * call it AP_FLASH_WP_ODL. 489 */ 490 "AP_FLASH_WP_L", 491 "TCHPAD_INT_ODL", 492 "EDP_HPD_1V8", 493 "AP_I2C_CAM_SDA", 494 "AP_I2C_CAM_SCL", 495 "AP_I2C_TCHPAD_SDA_1V8", 496 "AP_I2C_TCHPAD_SCL_1V8", 497 "AP_I2C_AUD_SDA", 498 "AP_I2C_AUD_SCL", 499 "AP_I2C_TPM_SDA_1V8", 500 "AP_I2C_TPM_SCL_1V8", 501 "AP_I2C_TCHSCR_SDA_1V8", 502 "AP_I2C_TCHSCR_SCL_1V8", 503 "EC_AP_HPD_OD", 504 "", 505 "PCIE_NVME_RST_L", 506 "PCIE_NVME_CLKREQ_ODL", 507 "PCIE_RST_1V8_L", 508 "PCIE_CLKREQ_1V8_ODL", 509 "PCIE_WAKE_1V8_ODL", 510 "CLK_24M_CAM0", 511 "CAM1_SEN_EN", 512 "AP_I2C_PWR_SCL_1V8", 513 "AP_I2C_PWR_SDA_1V8", 514 "AP_I2C_MISC_SCL", 515 "AP_I2C_MISC_SDA", 516 "EN_PP5000_HDMI_X", 517 "AP_HDMITX_HTPLG", 518 "", 519 "AP_HDMITX_SCL_1V8", 520 "AP_HDMITX_SDA_1V8", 521 "AP_RTC_CLK32K", 522 "AP_EC_WATCHDOG_L", 523 "SRCLKENA0", 524 "SRCLKENA1", 525 "PWRAP_SPI0_CS_L", 526 "PWRAP_SPI0_CK", 527 "PWRAP_SPI0_MOSI", 528 "PWRAP_SPI0_MISO", 529 "SPMI_SCL", 530 "SPMI_SDA", 531 "", 532 "", 533 "", 534 "I2S_HP_DATAIN", 535 "I2S_HP_MCLK", 536 "I2S_HP_BCK", 537 "I2S_HP_LRCK", 538 "I2S_HP_DATAOUT", 539 "SD_CD_ODL", 540 "EN_PP3300_DISP_X", 541 "TCHSCR_RST_1V8_L", 542 "TCHSCR_REPORT_DISABLE", 543 "EN_PP3300_WLAN_X", 544 "BT_KILL_1V8_L", 545 "I2S_SPKR_DATAOUT", 546 "WIFI_KILL_1V8_L", 547 "BEEP_ON", 548 "SCP_I2C_SENSOR_SCL_1V8", 549 "SCP_I2C_SENSOR_SDA_1V8", 550 "", 551 "", 552 "", 553 "", 554 "AUD_CLK_MOSI", 555 "AUD_SYNC_MOSI", 556 "AUD_DAT_MOSI0", 557 "AUD_DAT_MOSI1", 558 "AUD_DAT_MISO0", 559 "AUD_DAT_MISO1", 560 "AUD_DAT_MISO2", 561 "SCP_VREQ_VAO", 562 "AP_SPI_GSC_TPM_CLK", 563 "AP_SPI_GSC_TPM_MOSI", 564 "AP_SPI_GSC_TPM_CS_L", 565 "AP_SPI_GSC_TPM_MISO", 566 "EN_PP1000_CAM_X", 567 "AP_EDP_BKLTEN", 568 "", 569 "USB3_HUB_RST_L", 570 "", 571 "WLAN_ALERT_ODL", 572 "EC_IN_RW_ODL", 573 "GSC_AP_INT_ODL", 574 "HP_INT_ODL", 575 "CAM0_RST_L", 576 "CAM1_RST_L", 577 "TCHSCR_INT_1V8_L", 578 "CAM1_DET_L", 579 "RST_ALC1011_L", 580 "", 581 "", 582 "BL_PWM_1V8", 583 "UART_AP_TX_DBG_RX", 584 "UART_DBG_TX_AP_RX", 585 "EN_SPKR", 586 "AP_EC_WARM_RST_REQ", 587 "UART_SCP_TX_DBGCON_RX", 588 "UART_DBGCON_TX_SCP_RX", 589 "", 590 "", 591 "KPCOL0", 592 "", 593 "MT6315_GPU_INT", 594 "MT6315_PROC_BC_INT", 595 "SD_CMD", 596 "SD_CLK", 597 "SD_DAT0", 598 "SD_DAT1", 599 "SD_DAT2", 600 "SD_DAT3", 601 "EMMC_DAT7", 602 "EMMC_DAT6", 603 "EMMC_DAT5", 604 "EMMC_DAT4", 605 "EMMC_RSTB", 606 "EMMC_CMD", 607 "EMMC_CLK", 608 "EMMC_DAT3", 609 "EMMC_DAT2", 610 "EMMC_DAT1", 611 "EMMC_DAT0", 612 "EMMC_DSL", 613 "", 614 "", 615 "MT6360_INT_ODL", 616 "SCP_JTAG0_TRSTN", 617 "AP_SPI_EC_CS_L", 618 "AP_SPI_EC_CLK", 619 "AP_SPI_EC_MOSI", 620 "AP_SPI_EC_MISO", 621 "SCP_JTAG0_TMS", 622 "SCP_JTAG0_TCK", 623 "SCP_JTAG0_TDO", 624 "SCP_JTAG0_TDI", 625 "AP_SPI_FLASH_CS_L", 626 "AP_SPI_FLASH_CLK", 627 "AP_SPI_FLASH_MOSI", 628 "AP_SPI_FLASH_MISO"; 629 630 aud_pins_default: audio-default-pins { 631 pins-cmd-dat { 632 pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, 633 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, 634 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, 635 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, 636 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, 637 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, 638 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>, 639 <PINMUX_GPIO0__FUNC_TDMIN_MCK>, 640 <PINMUX_GPIO1__FUNC_TDMIN_DI>, 641 <PINMUX_GPIO2__FUNC_TDMIN_LRCK>, 642 <PINMUX_GPIO3__FUNC_TDMIN_BCK>, 643 <PINMUX_GPIO60__FUNC_I2SO2_D0>, 644 <PINMUX_GPIO49__FUNC_I2SIN_D0>, 645 <PINMUX_GPIO50__FUNC_I2SO1_MCK>, 646 <PINMUX_GPIO51__FUNC_I2SO1_BCK>, 647 <PINMUX_GPIO52__FUNC_I2SO1_WS>, 648 <PINMUX_GPIO53__FUNC_I2SO1_D0>; 649 }; 650 651 pins-hp-jack-int-odl { 652 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>; 653 input-enable; 654 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 655 }; 656 }; 657 658 cr50_int: cr50-irq-default-pins { 659 pins-gsc-ap-int-odl { 660 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 661 input-enable; 662 }; 663 }; 664 665 cros_ec_int: cros-ec-irq-default-pins { 666 pins-ec-ap-int-odl { 667 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 668 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 669 input-enable; 670 }; 671 }; 672 673 edptx_pins_default: edptx-default-pins { 674 pins-cmd-dat { 675 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 676 bias-pull-up; 677 }; 678 }; 679 680 disp_pwm0_pin_default: disp-pwm0-default-pins { 681 pins-disp-pwm { 682 pinmux = <PINMUX_GPIO82__FUNC_GPIO82>, 683 <PINMUX_GPIO97__FUNC_DISP_PWM0>; 684 }; 685 }; 686 687 dptx_pin: dptx-default-pins { 688 pins-cmd-dat { 689 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 690 bias-pull-up; 691 }; 692 }; 693 694 i2c0_pins: i2c0-default-pins { 695 pins-bus { 696 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 697 <PINMUX_GPIO9__FUNC_SCL0>; 698 bias-disable; 699 drive-strength-microamp = <1000>; 700 }; 701 }; 702 703 i2c1_pins: i2c1-default-pins { 704 pins-bus { 705 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 706 <PINMUX_GPIO11__FUNC_SCL1>; 707 bias-pull-up = <1000>; 708 drive-strength-microamp = <1000>; 709 }; 710 }; 711 712 i2c2_pins: i2c2-default-pins { 713 pins-bus { 714 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 715 <PINMUX_GPIO13__FUNC_SCL2>; 716 bias-disable; 717 drive-strength-microamp = <1000>; 718 }; 719 }; 720 721 i2c3_pins: i2c3-default-pins { 722 pins-bus { 723 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 724 <PINMUX_GPIO15__FUNC_SCL3>; 725 bias-pull-up = <1000>; 726 drive-strength-microamp = <1000>; 727 }; 728 }; 729 730 i2c4_pins: i2c4-default-pins { 731 pins-bus { 732 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 733 <PINMUX_GPIO17__FUNC_SCL4>; 734 bias-pull-up = <1000>; 735 drive-strength = <4>; 736 }; 737 }; 738 739 i2c5_pins: i2c5-default-pins { 740 pins-bus { 741 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 742 <PINMUX_GPIO30__FUNC_SDA5>; 743 bias-disable; 744 drive-strength-microamp = <1000>; 745 }; 746 }; 747 748 i2c7_pins: i2c7-default-pins { 749 pins-bus { 750 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 751 <PINMUX_GPIO28__FUNC_SDA7>; 752 bias-disable; 753 }; 754 }; 755 756 mmc0_pins_default: mmc0-default-pins { 757 pins-cmd-dat { 758 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 759 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 760 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 761 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 762 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 763 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 764 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 765 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 766 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 767 input-enable; 768 drive-strength = <6>; 769 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 770 }; 771 772 pins-clk { 773 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 774 drive-strength = <6>; 775 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 776 }; 777 778 pins-rst { 779 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 780 drive-strength = <6>; 781 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 782 }; 783 }; 784 785 mmc0_pins_uhs: mmc0-uhs-pins { 786 pins-cmd-dat { 787 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 788 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 789 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 790 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 791 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 792 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 793 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 794 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 795 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 796 input-enable; 797 drive-strength = <8>; 798 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 799 }; 800 801 pins-clk { 802 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 803 drive-strength = <8>; 804 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 805 }; 806 807 pins-ds { 808 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 809 drive-strength = <8>; 810 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 811 }; 812 813 pins-rst { 814 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 815 drive-strength = <8>; 816 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 817 }; 818 }; 819 820 mmc1_pins_detect: mmc1-detect-pins { 821 pins-insert { 822 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 823 bias-pull-up; 824 }; 825 }; 826 827 mmc1_pins_default: mmc1-default-pins { 828 pins-cmd-dat { 829 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 830 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 831 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 832 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 833 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 834 input-enable; 835 drive-strength = <8>; 836 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 837 }; 838 839 pins-clk { 840 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 841 drive-strength = <8>; 842 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 843 }; 844 }; 845 846 nor_pins_default: nor-default-pins { 847 pins-ck-io { 848 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 849 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 850 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 851 drive-strength = <6>; 852 bias-pull-down; 853 }; 854 855 pins-cs { 856 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 857 drive-strength = <6>; 858 bias-pull-up; 859 }; 860 }; 861 862 pcie0_pins_default: pcie0-default-pins { 863 pins-bus { 864 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 865 <PINMUX_GPIO20__FUNC_PERSTN>, 866 <PINMUX_GPIO21__FUNC_CLKREQN>; 867 bias-pull-up; 868 }; 869 }; 870 871 pcie1_pins_default: pcie1-default-pins { 872 pins-bus { 873 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>, 874 <PINMUX_GPIO23__FUNC_CLKREQN_1>, 875 <PINMUX_GPIO24__FUNC_WAKEN_1>; 876 bias-pull-up; 877 }; 878 }; 879 880 pio_default: pio-default-pins { 881 pins-wifi-enable { 882 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 883 output-high; 884 drive-strength = <14>; 885 }; 886 887 pins-low-power-pd { 888 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 889 <PINMUX_GPIO26__FUNC_GPIO26>, 890 <PINMUX_GPIO46__FUNC_GPIO46>, 891 <PINMUX_GPIO47__FUNC_GPIO47>, 892 <PINMUX_GPIO48__FUNC_GPIO48>, 893 <PINMUX_GPIO65__FUNC_GPIO65>, 894 <PINMUX_GPIO66__FUNC_GPIO66>, 895 <PINMUX_GPIO67__FUNC_GPIO67>, 896 <PINMUX_GPIO68__FUNC_GPIO68>, 897 <PINMUX_GPIO128__FUNC_GPIO128>, 898 <PINMUX_GPIO129__FUNC_GPIO129>; 899 input-enable; 900 bias-pull-down; 901 }; 902 903 pins-low-power-pupd { 904 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 905 <PINMUX_GPIO78__FUNC_GPIO78>, 906 <PINMUX_GPIO79__FUNC_GPIO79>, 907 <PINMUX_GPIO80__FUNC_GPIO80>, 908 <PINMUX_GPIO83__FUNC_GPIO83>, 909 <PINMUX_GPIO85__FUNC_GPIO85>, 910 <PINMUX_GPIO90__FUNC_GPIO90>, 911 <PINMUX_GPIO91__FUNC_GPIO91>, 912 <PINMUX_GPIO93__FUNC_GPIO93>, 913 <PINMUX_GPIO94__FUNC_GPIO94>, 914 <PINMUX_GPIO95__FUNC_GPIO95>, 915 <PINMUX_GPIO96__FUNC_GPIO96>, 916 <PINMUX_GPIO104__FUNC_GPIO104>, 917 <PINMUX_GPIO105__FUNC_GPIO105>, 918 <PINMUX_GPIO107__FUNC_GPIO107>; 919 input-enable; 920 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 921 }; 922 }; 923 924 rt1019p_pins_default: rt1019p-default-pins { 925 pins-amp-sdb { 926 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>; 927 output-low; 928 }; 929 }; 930 931 scp_pins: scp-default-pins { 932 pins-vreq { 933 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 934 bias-disable; 935 input-enable; 936 }; 937 }; 938 939 spi0_pins: spi0-default-pins { 940 pins-cs-mosi-clk { 941 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 942 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 943 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 944 bias-disable; 945 }; 946 947 pins-miso { 948 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 949 bias-pull-down; 950 }; 951 }; 952 953 subpmic_default: subpmic-default-pins { 954 subpmic_pin_irq: pins-subpmic-int-n { 955 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 956 input-enable; 957 bias-pull-up; 958 }; 959 }; 960 961 trackpad_pins: trackpad-default-pins { 962 pins-int-n { 963 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 964 input-enable; 965 bias-pull-up; 966 }; 967 }; 968 969 touchscreen_pins: touchscreen-default-pins { 970 pins-int-n { 971 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 972 input-enable; 973 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 974 }; 975 pins-rst { 976 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 977 output-high; 978 }; 979 pins-report-sw { 980 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 981 output-low; 982 }; 983 }; 984}; 985 986&pmic { 987 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 988}; 989 990&scp { 991 status = "okay"; 992 993 firmware-name = "mediatek/mt8195/scp.img"; 994 memory-region = <&scp_mem>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&scp_pins>; 997 998 cros-ec-rpmsg { 999 compatible = "google,cros-ec-rpmsg"; 1000 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1001 }; 1002}; 1003 1004&sound { 1005 status = "okay"; 1006 1007 mediatek,adsp = <&adsp>; 1008 mediatek,dai-link = 1009 "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE", 1010 "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE", 1011 "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5"; 1012 pinctrl-names = "default"; 1013 pinctrl-0 = <&aud_pins_default>; 1014}; 1015 1016&spi0 { 1017 status = "okay"; 1018 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&spi0_pins>; 1021 mediatek,pad-select = <0>; 1022 1023 cros_ec: ec@0 { 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 1027 compatible = "google,cros-ec-spi"; 1028 reg = <0>; 1029 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&cros_ec_int>; 1032 spi-max-frequency = <3000000>; 1033 1034 keyboard-backlight { 1035 compatible = "google,cros-kbd-led-backlight"; 1036 }; 1037 1038 i2c_tunnel: i2c-tunnel { 1039 compatible = "google,cros-ec-i2c-tunnel"; 1040 google,remote-bus = <0>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 }; 1044 1045 mt_pmic_vmc_ldo_reg: regulator@0 { 1046 compatible = "google,cros-ec-regulator"; 1047 reg = <0>; 1048 regulator-name = "mt_pmic_vmc_ldo"; 1049 regulator-min-microvolt = <1200000>; 1050 regulator-max-microvolt = <3600000>; 1051 }; 1052 1053 mt_pmic_vmch_ldo_reg: regulator@1 { 1054 compatible = "google,cros-ec-regulator"; 1055 reg = <1>; 1056 regulator-name = "mt_pmic_vmch_ldo"; 1057 regulator-min-microvolt = <2700000>; 1058 regulator-max-microvolt = <3600000>; 1059 }; 1060 1061 typec { 1062 compatible = "google,cros-ec-typec"; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 1066 usb_c0: connector@0 { 1067 compatible = "usb-c-connector"; 1068 reg = <0>; 1069 power-role = "dual"; 1070 data-role = "host"; 1071 try-power-role = "source"; 1072 }; 1073 1074 usb_c1: connector@1 { 1075 compatible = "usb-c-connector"; 1076 reg = <1>; 1077 power-role = "dual"; 1078 data-role = "host"; 1079 try-power-role = "source"; 1080 }; 1081 }; 1082 }; 1083}; 1084 1085&spmi { 1086 #address-cells = <2>; 1087 #size-cells = <0>; 1088 1089 mt6315@6 { 1090 compatible = "mediatek,mt6315-regulator"; 1091 reg = <0x6 SPMI_USID>; 1092 1093 regulators { 1094 mt6315_6_vbuck1: vbuck1 { 1095 regulator-compatible = "vbuck1"; 1096 regulator-name = "Vbcpu"; 1097 regulator-min-microvolt = <300000>; 1098 regulator-max-microvolt = <1193750>; 1099 regulator-enable-ramp-delay = <256>; 1100 regulator-ramp-delay = <6250>; 1101 regulator-allowed-modes = <0 1 2>; 1102 regulator-always-on; 1103 }; 1104 }; 1105 }; 1106 1107 mt6315@7 { 1108 compatible = "mediatek,mt6315-regulator"; 1109 reg = <0x7 SPMI_USID>; 1110 1111 regulators { 1112 mt6315_7_vbuck1: vbuck1 { 1113 regulator-compatible = "vbuck1"; 1114 regulator-name = "Vgpu"; 1115 regulator-min-microvolt = <625000>; 1116 regulator-max-microvolt = <1193750>; 1117 regulator-enable-ramp-delay = <256>; 1118 regulator-ramp-delay = <6250>; 1119 regulator-allowed-modes = <0 1 2>; 1120 regulator-always-on; 1121 }; 1122 }; 1123 }; 1124}; 1125 1126&u3phy0 { 1127 status = "okay"; 1128}; 1129 1130&u3phy1 { 1131 status = "okay"; 1132}; 1133 1134&u3phy2 { 1135 status = "okay"; 1136}; 1137 1138&u3phy3 { 1139 status = "okay"; 1140}; 1141 1142&uart0 { 1143 status = "okay"; 1144}; 1145 1146&xhci0 { 1147 status = "okay"; 1148 1149 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1150 vbus-supply = <&usb_vbus>; 1151}; 1152 1153&xhci1 { 1154 status = "okay"; 1155 1156 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1157 vbus-supply = <&usb_vbus>; 1158}; 1159 1160&xhci2 { 1161 status = "okay"; 1162 1163 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1164 vbus-supply = <&usb_vbus>; 1165}; 1166 1167&xhci3 { 1168 status = "okay"; 1169 1170 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1171 usb2-lpm-disable; 1172 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1173 vbus-supply = <&usb_vbus>; 1174}; 1175 1176#include <arm/cros-ec-keyboard.dtsi> 1177#include <arm/cros-ec-sbs.dtsi> 1178 1179&keyboard_controller { 1180 function-row-physmap = < 1181 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1182 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1183 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1184 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1185 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1186 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1187 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1188 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1189 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1190 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1191 >; 1192 1193 linux,keymap = < 1194 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1195 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1196 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1197 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1198 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 1199 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 1200 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 1201 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1202 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1203 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1204 1205 CROS_STD_MAIN_KEYMAP 1206 >; 1207}; 1208