1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include "mt8195.dtsi" 8#include "mt6359.dtsi" 9 10/ { 11 aliases { 12 mmc0 = &mmc0; 13 serial0 = &uart0; 14 }; 15 16 chosen { 17 stdout-path = "serial0:115200n8"; 18 }; 19 20 memory@40000000 { 21 device_type = "memory"; 22 reg = <0 0x40000000 0 0x80000000>; 23 }; 24 25 /* system wide LDO 3.3V power rail */ 26 pp3300_z5: regulator-pp3300-ldo-z5 { 27 compatible = "regulator-fixed"; 28 regulator-name = "pp3300_ldo_z5"; 29 regulator-always-on; 30 regulator-boot-on; 31 regulator-min-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>; 33 vin-supply = <&ppvar_sys>; 34 }; 35 36 /* separately switched 3.3V power rail */ 37 pp3300_s3: regulator-pp3300-s3 { 38 compatible = "regulator-fixed"; 39 regulator-name = "pp3300_s3"; 40 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 41 regulator-always-on; 42 regulator-boot-on; 43 regulator-min-microvolt = <3300000>; 44 regulator-max-microvolt = <3300000>; 45 vin-supply = <&pp3300_z2>; 46 }; 47 48 /* system wide 3.3V power rail */ 49 pp3300_z2: regulator-pp3300-z2 { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp3300_z2"; 52 /* EN pin tied to pp4200_z2, which is controlled by EC */ 53 regulator-always-on; 54 regulator-boot-on; 55 regulator-min-microvolt = <3300000>; 56 regulator-max-microvolt = <3300000>; 57 vin-supply = <&ppvar_sys>; 58 }; 59 60 /* system wide 4.2V power rail */ 61 pp4200_z2: regulator-pp4200-z2 { 62 compatible = "regulator-fixed"; 63 regulator-name = "pp4200_z2"; 64 /* controlled by EC */ 65 regulator-always-on; 66 regulator-boot-on; 67 regulator-min-microvolt = <4200000>; 68 regulator-max-microvolt = <4200000>; 69 vin-supply = <&ppvar_sys>; 70 }; 71 72 /* system wide switching 5.0V power rail */ 73 pp5000_s5: regulator-pp5000-s5 { 74 compatible = "regulator-fixed"; 75 regulator-name = "pp5000_s5"; 76 /* controlled by EC */ 77 regulator-always-on; 78 regulator-boot-on; 79 regulator-min-microvolt = <5000000>; 80 regulator-max-microvolt = <5000000>; 81 vin-supply = <&ppvar_sys>; 82 }; 83 84 /* system wide semi-regulated power rail from battery or USB */ 85 ppvar_sys: regulator-ppvar-sys { 86 compatible = "regulator-fixed"; 87 regulator-name = "ppvar_sys"; 88 regulator-always-on; 89 regulator-boot-on; 90 }; 91}; 92 93&mmc0 { 94 status = "okay"; 95 96 bus-width = <8>; 97 cap-mmc-highspeed; 98 cap-mmc-hw-reset; 99 hs400-ds-delay = <0x14c11>; 100 max-frequency = <200000000>; 101 mmc-hs200-1_8v; 102 mmc-hs400-1_8v; 103 no-sdio; 104 no-sd; 105 non-removable; 106 pinctrl-names = "default", "state_uhs"; 107 pinctrl-0 = <&mmc0_pins_default>; 108 pinctrl-1 = <&mmc0_pins_uhs>; 109 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 110 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 111}; 112 113/* for CPU-L */ 114&mt6359_vcore_buck_reg { 115 regulator-always-on; 116}; 117 118/* for CORE */ 119&mt6359_vgpu11_buck_reg { 120 regulator-always-on; 121}; 122 123&mt6359_vgpu11_sshub_buck_reg { 124 regulator-always-on; 125 regulator-min-microvolt = <550000>; 126 regulator-max-microvolt = <550000>; 127}; 128 129/* for CORE SRAM */ 130&mt6359_vpu_buck_reg { 131 regulator-always-on; 132}; 133 134&mt6359_vrf12_ldo_reg { 135 regulator-always-on; 136}; 137 138/* for GPU SRAM */ 139&mt6359_vsram_others_ldo_reg { 140 regulator-always-on; 141 regulator-min-microvolt = <750000>; 142 regulator-max-microvolt = <750000>; 143}; 144 145&mt6359_vufs_ldo_reg { 146 regulator-always-on; 147}; 148 149&pio { 150 mmc0_pins_default: mmc0-default-pins { 151 pins-cmd-dat { 152 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 153 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 154 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 155 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 156 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 157 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 158 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 159 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 160 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 161 input-enable; 162 drive-strength = <6>; 163 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 164 }; 165 166 pins-clk { 167 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 168 drive-strength = <6>; 169 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 170 }; 171 172 pins-rst { 173 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 174 drive-strength = <6>; 175 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 176 }; 177 }; 178 179 mmc0_pins_uhs: mmc0-uhs-pins { 180 pins-cmd-dat { 181 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 182 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 183 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 184 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 185 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 186 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 187 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 188 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 189 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 190 input-enable; 191 drive-strength = <8>; 192 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 193 }; 194 195 pins-clk { 196 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 197 drive-strength = <8>; 198 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 199 }; 200 201 pins-ds { 202 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 203 drive-strength = <8>; 204 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 205 }; 206 207 pins-rst { 208 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 209 drive-strength = <8>; 210 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 211 }; 212 }; 213}; 214 215&pmic { 216 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 217}; 218 219&uart0 { 220 status = "okay"; 221}; 222