1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 dmic-codec { 30 compatible = "dmic-codec"; 31 num-channels = <2>; 32 wakeup-delay-ms = <50>; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 /* system wide LDO 3.3V power rail */ 41 pp3300_z5: regulator-pp3300-ldo-z5 { 42 compatible = "regulator-fixed"; 43 regulator-name = "pp3300_ldo_z5"; 44 regulator-always-on; 45 regulator-boot-on; 46 regulator-min-microvolt = <3300000>; 47 regulator-max-microvolt = <3300000>; 48 vin-supply = <&ppvar_sys>; 49 }; 50 51 /* separately switched 3.3V power rail */ 52 pp3300_s3: regulator-pp3300-s3 { 53 compatible = "regulator-fixed"; 54 regulator-name = "pp3300_s3"; 55 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 56 regulator-always-on; 57 regulator-boot-on; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 vin-supply = <&pp3300_z2>; 61 }; 62 63 /* system wide 3.3V power rail */ 64 pp3300_z2: regulator-pp3300-z2 { 65 compatible = "regulator-fixed"; 66 regulator-name = "pp3300_z2"; 67 /* EN pin tied to pp4200_z2, which is controlled by EC */ 68 regulator-always-on; 69 regulator-boot-on; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 vin-supply = <&ppvar_sys>; 73 }; 74 75 /* system wide 4.2V power rail */ 76 pp4200_z2: regulator-pp4200-z2 { 77 compatible = "regulator-fixed"; 78 regulator-name = "pp4200_z2"; 79 /* controlled by EC */ 80 regulator-always-on; 81 regulator-boot-on; 82 regulator-min-microvolt = <4200000>; 83 regulator-max-microvolt = <4200000>; 84 vin-supply = <&ppvar_sys>; 85 }; 86 87 /* system wide switching 5.0V power rail */ 88 pp5000_s5: regulator-pp5000-s5 { 89 compatible = "regulator-fixed"; 90 regulator-name = "pp5000_s5"; 91 /* controlled by EC */ 92 regulator-always-on; 93 regulator-boot-on; 94 regulator-min-microvolt = <5000000>; 95 regulator-max-microvolt = <5000000>; 96 vin-supply = <&ppvar_sys>; 97 }; 98 99 /* system wide semi-regulated power rail from battery or USB */ 100 ppvar_sys: regulator-ppvar-sys { 101 compatible = "regulator-fixed"; 102 regulator-name = "ppvar_sys"; 103 regulator-always-on; 104 regulator-boot-on; 105 }; 106 107 usb_vbus: regulator-5v0-usb-vbus { 108 compatible = "regulator-fixed"; 109 regulator-name = "usb-vbus"; 110 regulator-min-microvolt = <5000000>; 111 regulator-max-microvolt = <5000000>; 112 enable-active-high; 113 regulator-always-on; 114 }; 115 116 reserved_memory: reserved-memory { 117 #address-cells = <2>; 118 #size-cells = <2>; 119 ranges; 120 121 scp_mem: memory@50000000 { 122 compatible = "shared-dma-pool"; 123 reg = <0 0x50000000 0 0x2900000>; 124 no-map; 125 }; 126 127 adsp_mem: memory@60000000 { 128 compatible = "shared-dma-pool"; 129 reg = <0 0x60000000 0 0xd80000>; 130 no-map; 131 }; 132 133 afe_mem: memory@60d80000 { 134 compatible = "shared-dma-pool"; 135 reg = <0 0x60d80000 0 0x100000>; 136 no-map; 137 }; 138 139 adsp_device_mem: memory@60e80000 { 140 compatible = "shared-dma-pool"; 141 reg = <0 0x60e80000 0 0x280000>; 142 no-map; 143 }; 144 }; 145 146 spk_amplifier: rt1019p { 147 compatible = "realtek,rt1019p"; 148 label = "rt1019p"; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&rt1019p_pins_default>; 151 sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; 152 }; 153}; 154 155&adsp { 156 status = "okay"; 157 158 memory-region = <&adsp_device_mem>, <&adsp_mem>; 159}; 160 161&afe { 162 status = "okay"; 163 164 mediatek,etdm-in2-cowork-source = <2>; 165 mediatek,etdm-out2-cowork-source = <0>; 166 memory-region = <&afe_mem>; 167}; 168 169&dp_intf0 { 170 status = "okay"; 171 172 port { 173 dp_intf0_out: endpoint { 174 remote-endpoint = <&edp_in>; 175 }; 176 }; 177}; 178 179&dp_intf1 { 180 status = "okay"; 181 182 port { 183 dp_intf1_out: endpoint { 184 remote-endpoint = <&dptx_in>; 185 }; 186 }; 187}; 188 189&edp_tx { 190 status = "okay"; 191 192 pinctrl-names = "default"; 193 pinctrl-0 = <&edptx_pins_default>; 194 195 ports { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 port@0 { 200 reg = <0>; 201 edp_in: endpoint { 202 remote-endpoint = <&dp_intf0_out>; 203 }; 204 }; 205 206 port@1 { 207 reg = <1>; 208 edp_out: endpoint { 209 data-lanes = <0 1 2 3>; 210 }; 211 }; 212 }; 213}; 214 215&dp_tx { 216 status = "okay"; 217 218 pinctrl-names = "default"; 219 pinctrl-0 = <&dptx_pin>; 220 221 ports { 222 #address-cells = <1>; 223 #size-cells = <0>; 224 225 port@0 { 226 reg = <0>; 227 dptx_in: endpoint { 228 remote-endpoint = <&dp_intf1_out>; 229 }; 230 }; 231 232 port@1 { 233 reg = <1>; 234 dptx_out: endpoint { 235 data-lanes = <0 1 2 3>; 236 }; 237 }; 238 }; 239}; 240 241&i2c0 { 242 status = "okay"; 243 244 clock-frequency = <400000>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&i2c0_pins>; 247}; 248 249&i2c1 { 250 status = "okay"; 251 252 clock-frequency = <400000>; 253 i2c-scl-internal-delay-ns = <12500>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&i2c1_pins>; 256 257 trackpad@15 { 258 compatible = "elan,ekth3000"; 259 reg = <0x15>; 260 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&trackpad_pins>; 263 vcc-supply = <&pp3300_s3>; 264 wakeup-source; 265 }; 266}; 267 268&i2c2 { 269 status = "okay"; 270 271 clock-frequency = <400000>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&i2c2_pins>; 274 275 audio_codec: codec@1a { 276 /* Realtek RT5682i or RT5682s, sharing the same configuration */ 277 reg = <0x1a>; 278 interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; 279 realtek,jd-src = <1>; 280 281 AVDD-supply = <&mt6359_vio18_ldo_reg>; 282 MICVDD-supply = <&pp3300_z2>; 283 VBAT-supply = <&pp3300_z5>; 284 }; 285}; 286 287&i2c3 { 288 status = "okay"; 289 290 clock-frequency = <400000>; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&i2c3_pins>; 293 294 tpm@50 { 295 compatible = "google,cr50"; 296 reg = <0x50>; 297 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&cr50_int>; 300 }; 301}; 302 303&i2c4 { 304 status = "okay"; 305 306 clock-frequency = <400000>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c4_pins>; 309 310 ts_10: touchscreen@10 { 311 compatible = "hid-over-i2c"; 312 reg = <0x10>; 313 hid-descr-addr = <0x0001>; 314 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&touchscreen_pins>; 317 post-power-on-delay-ms = <10>; 318 vdd-supply = <&pp3300_s3>; 319 status = "disabled"; 320 }; 321}; 322 323&i2c5 { 324 status = "okay"; 325 326 clock-frequency = <400000>; 327 pinctrl-names = "default"; 328 pinctrl-0 = <&i2c5_pins>; 329}; 330 331&i2c7 { 332 status = "okay"; 333 334 clock-frequency = <400000>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&i2c7_pins>; 337 338 pmic@34 { 339 #interrupt-cells = <1>; 340 compatible = "mediatek,mt6360"; 341 reg = <0x34>; 342 interrupt-controller; 343 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 344 interrupt-names = "IRQB"; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&subpmic_default>; 347 wakeup-source; 348 }; 349}; 350 351&mmc0 { 352 status = "okay"; 353 354 bus-width = <8>; 355 cap-mmc-highspeed; 356 cap-mmc-hw-reset; 357 hs400-ds-delay = <0x14c11>; 358 max-frequency = <200000000>; 359 mmc-hs200-1_8v; 360 mmc-hs400-1_8v; 361 no-sdio; 362 no-sd; 363 non-removable; 364 pinctrl-names = "default", "state_uhs"; 365 pinctrl-0 = <&mmc0_pins_default>; 366 pinctrl-1 = <&mmc0_pins_uhs>; 367 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 368 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 369}; 370 371&mmc1 { 372 status = "okay"; 373 374 bus-width = <4>; 375 cap-sd-highspeed; 376 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 377 max-frequency = <200000000>; 378 no-mmc; 379 no-sdio; 380 pinctrl-names = "default", "state_uhs"; 381 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 382 pinctrl-1 = <&mmc1_pins_default>; 383 sd-uhs-sdr50; 384 sd-uhs-sdr104; 385 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 386 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 387}; 388 389&mt6359codec { 390 mediatek,dmic-mode = <1>; /* one-wire */ 391 mediatek,mic-type-0 = <2>; /* DMIC */ 392}; 393 394/* for CPU-L */ 395&mt6359_vcore_buck_reg { 396 regulator-always-on; 397}; 398 399/* for CORE */ 400&mt6359_vgpu11_buck_reg { 401 regulator-always-on; 402}; 403 404&mt6359_vgpu11_sshub_buck_reg { 405 regulator-always-on; 406 regulator-min-microvolt = <550000>; 407 regulator-max-microvolt = <550000>; 408}; 409 410/* for CORE SRAM */ 411&mt6359_vpu_buck_reg { 412 regulator-always-on; 413}; 414 415&mt6359_vrf12_ldo_reg { 416 regulator-always-on; 417}; 418 419/* for GPU SRAM */ 420&mt6359_vsram_others_ldo_reg { 421 regulator-always-on; 422 regulator-min-microvolt = <750000>; 423 regulator-max-microvolt = <750000>; 424}; 425 426&mt6359_vufs_ldo_reg { 427 regulator-always-on; 428}; 429 430&nor_flash { 431 status = "okay"; 432 433 pinctrl-names = "default"; 434 pinctrl-0 = <&nor_pins_default>; 435 436 flash@0 { 437 compatible = "jedec,spi-nor"; 438 reg = <0>; 439 spi-max-frequency = <52000000>; 440 spi-rx-bus-width = <2>; 441 spi-tx-bus-width = <2>; 442 }; 443}; 444 445&pio { 446 mediatek,rsel-resistance-in-si-unit; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&pio_default>; 449 450 /* 144 lines */ 451 gpio-line-names = 452 "I2S_SPKR_MCLK", 453 "I2S_SPKR_DATAIN", 454 "I2S_SPKR_LRCK", 455 "I2S_SPKR_BCLK", 456 "EC_AP_INT_ODL", 457 /* 458 * AP_FLASH_WP_L is crossystem ABI. Schematics 459 * call it AP_FLASH_WP_ODL. 460 */ 461 "AP_FLASH_WP_L", 462 "TCHPAD_INT_ODL", 463 "EDP_HPD_1V8", 464 "AP_I2C_CAM_SDA", 465 "AP_I2C_CAM_SCL", 466 "AP_I2C_TCHPAD_SDA_1V8", 467 "AP_I2C_TCHPAD_SCL_1V8", 468 "AP_I2C_AUD_SDA", 469 "AP_I2C_AUD_SCL", 470 "AP_I2C_TPM_SDA_1V8", 471 "AP_I2C_TPM_SCL_1V8", 472 "AP_I2C_TCHSCR_SDA_1V8", 473 "AP_I2C_TCHSCR_SCL_1V8", 474 "EC_AP_HPD_OD", 475 "", 476 "PCIE_NVME_RST_L", 477 "PCIE_NVME_CLKREQ_ODL", 478 "PCIE_RST_1V8_L", 479 "PCIE_CLKREQ_1V8_ODL", 480 "PCIE_WAKE_1V8_ODL", 481 "CLK_24M_CAM0", 482 "CAM1_SEN_EN", 483 "AP_I2C_PWR_SCL_1V8", 484 "AP_I2C_PWR_SDA_1V8", 485 "AP_I2C_MISC_SCL", 486 "AP_I2C_MISC_SDA", 487 "EN_PP5000_HDMI_X", 488 "AP_HDMITX_HTPLG", 489 "", 490 "AP_HDMITX_SCL_1V8", 491 "AP_HDMITX_SDA_1V8", 492 "AP_RTC_CLK32K", 493 "AP_EC_WATCHDOG_L", 494 "SRCLKENA0", 495 "SRCLKENA1", 496 "PWRAP_SPI0_CS_L", 497 "PWRAP_SPI0_CK", 498 "PWRAP_SPI0_MOSI", 499 "PWRAP_SPI0_MISO", 500 "SPMI_SCL", 501 "SPMI_SDA", 502 "", 503 "", 504 "", 505 "I2S_HP_DATAIN", 506 "I2S_HP_MCLK", 507 "I2S_HP_BCK", 508 "I2S_HP_LRCK", 509 "I2S_HP_DATAOUT", 510 "SD_CD_ODL", 511 "EN_PP3300_DISP_X", 512 "TCHSCR_RST_1V8_L", 513 "TCHSCR_REPORT_DISABLE", 514 "EN_PP3300_WLAN_X", 515 "BT_KILL_1V8_L", 516 "I2S_SPKR_DATAOUT", 517 "WIFI_KILL_1V8_L", 518 "BEEP_ON", 519 "SCP_I2C_SENSOR_SCL_1V8", 520 "SCP_I2C_SENSOR_SDA_1V8", 521 "", 522 "", 523 "", 524 "", 525 "AUD_CLK_MOSI", 526 "AUD_SYNC_MOSI", 527 "AUD_DAT_MOSI0", 528 "AUD_DAT_MOSI1", 529 "AUD_DAT_MISO0", 530 "AUD_DAT_MISO1", 531 "AUD_DAT_MISO2", 532 "SCP_VREQ_VAO", 533 "AP_SPI_GSC_TPM_CLK", 534 "AP_SPI_GSC_TPM_MOSI", 535 "AP_SPI_GSC_TPM_CS_L", 536 "AP_SPI_GSC_TPM_MISO", 537 "EN_PP1000_CAM_X", 538 "AP_EDP_BKLTEN", 539 "", 540 "USB3_HUB_RST_L", 541 "", 542 "WLAN_ALERT_ODL", 543 "EC_IN_RW_ODL", 544 "GSC_AP_INT_ODL", 545 "HP_INT_ODL", 546 "CAM0_RST_L", 547 "CAM1_RST_L", 548 "TCHSCR_INT_1V8_L", 549 "CAM1_DET_L", 550 "RST_ALC1011_L", 551 "", 552 "", 553 "BL_PWM_1V8", 554 "UART_AP_TX_DBG_RX", 555 "UART_DBG_TX_AP_RX", 556 "EN_SPKR", 557 "AP_EC_WARM_RST_REQ", 558 "UART_SCP_TX_DBGCON_RX", 559 "UART_DBGCON_TX_SCP_RX", 560 "", 561 "", 562 "KPCOL0", 563 "", 564 "MT6315_GPU_INT", 565 "MT6315_PROC_BC_INT", 566 "SD_CMD", 567 "SD_CLK", 568 "SD_DAT0", 569 "SD_DAT1", 570 "SD_DAT2", 571 "SD_DAT3", 572 "EMMC_DAT7", 573 "EMMC_DAT6", 574 "EMMC_DAT5", 575 "EMMC_DAT4", 576 "EMMC_RSTB", 577 "EMMC_CMD", 578 "EMMC_CLK", 579 "EMMC_DAT3", 580 "EMMC_DAT2", 581 "EMMC_DAT1", 582 "EMMC_DAT0", 583 "EMMC_DSL", 584 "", 585 "", 586 "MT6360_INT_ODL", 587 "SCP_JTAG0_TRSTN", 588 "AP_SPI_EC_CS_L", 589 "AP_SPI_EC_CLK", 590 "AP_SPI_EC_MOSI", 591 "AP_SPI_EC_MISO", 592 "SCP_JTAG0_TMS", 593 "SCP_JTAG0_TCK", 594 "SCP_JTAG0_TDO", 595 "SCP_JTAG0_TDI", 596 "AP_SPI_FLASH_CS_L", 597 "AP_SPI_FLASH_CLK", 598 "AP_SPI_FLASH_MOSI", 599 "AP_SPI_FLASH_MISO"; 600 601 cr50_int: cr50-irq-default-pins { 602 pins-gsc-ap-int-odl { 603 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 604 input-enable; 605 }; 606 }; 607 608 cros_ec_int: cros-ec-irq-default-pins { 609 pins-ec-ap-int-odl { 610 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 611 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 612 input-enable; 613 }; 614 }; 615 616 edptx_pins_default: edptx-default-pins { 617 pins-cmd-dat { 618 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 619 bias-pull-up; 620 }; 621 }; 622 623 dptx_pin: dptx-default-pins { 624 pins-cmd-dat { 625 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 626 bias-pull-up; 627 }; 628 }; 629 630 i2c0_pins: i2c0-default-pins { 631 pins-bus { 632 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 633 <PINMUX_GPIO9__FUNC_SCL0>; 634 bias-disable; 635 drive-strength-microamp = <1000>; 636 }; 637 }; 638 639 i2c1_pins: i2c1-default-pins { 640 pins-bus { 641 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 642 <PINMUX_GPIO11__FUNC_SCL1>; 643 bias-pull-up = <1000>; 644 drive-strength-microamp = <1000>; 645 }; 646 }; 647 648 i2c2_pins: i2c2-default-pins { 649 pins-bus { 650 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 651 <PINMUX_GPIO13__FUNC_SCL2>; 652 bias-disable; 653 drive-strength-microamp = <1000>; 654 }; 655 }; 656 657 i2c3_pins: i2c3-default-pins { 658 pins-bus { 659 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 660 <PINMUX_GPIO15__FUNC_SCL3>; 661 bias-pull-up = <1000>; 662 drive-strength-microamp = <1000>; 663 }; 664 }; 665 666 i2c4_pins: i2c4-default-pins { 667 pins-bus { 668 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 669 <PINMUX_GPIO17__FUNC_SCL4>; 670 bias-pull-up = <1000>; 671 drive-strength = <4>; 672 }; 673 }; 674 675 i2c5_pins: i2c5-default-pins { 676 pins-bus { 677 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 678 <PINMUX_GPIO30__FUNC_SDA5>; 679 bias-disable; 680 drive-strength-microamp = <1000>; 681 }; 682 }; 683 684 i2c7_pins: i2c7-default-pins { 685 pins-bus { 686 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 687 <PINMUX_GPIO28__FUNC_SDA7>; 688 bias-disable; 689 }; 690 }; 691 692 mmc0_pins_default: mmc0-default-pins { 693 pins-cmd-dat { 694 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 695 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 696 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 697 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 698 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 699 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 700 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 701 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 702 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 703 input-enable; 704 drive-strength = <6>; 705 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 706 }; 707 708 pins-clk { 709 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 710 drive-strength = <6>; 711 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 712 }; 713 714 pins-rst { 715 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 716 drive-strength = <6>; 717 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 718 }; 719 }; 720 721 mmc0_pins_uhs: mmc0-uhs-pins { 722 pins-cmd-dat { 723 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 724 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 725 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 726 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 727 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 728 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 729 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 730 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 731 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 732 input-enable; 733 drive-strength = <8>; 734 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 735 }; 736 737 pins-clk { 738 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 739 drive-strength = <8>; 740 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 741 }; 742 743 pins-ds { 744 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 745 drive-strength = <8>; 746 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 747 }; 748 749 pins-rst { 750 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 751 drive-strength = <8>; 752 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 753 }; 754 }; 755 756 mmc1_pins_detect: mmc1-detect-pins { 757 pins-insert { 758 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 759 bias-pull-up; 760 }; 761 }; 762 763 mmc1_pins_default: mmc1-default-pins { 764 pins-cmd-dat { 765 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 766 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 767 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 768 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 769 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 770 input-enable; 771 drive-strength = <8>; 772 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 773 }; 774 775 pins-clk { 776 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 777 drive-strength = <8>; 778 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 779 }; 780 }; 781 782 nor_pins_default: nor-default-pins { 783 pins-ck-io { 784 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 785 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 786 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 787 drive-strength = <6>; 788 bias-pull-down; 789 }; 790 791 pins-cs { 792 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 793 drive-strength = <6>; 794 bias-pull-up; 795 }; 796 }; 797 798 pio_default: pio-default-pins { 799 pins-wifi-enable { 800 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 801 output-high; 802 drive-strength = <14>; 803 }; 804 805 pins-low-power-pd { 806 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 807 <PINMUX_GPIO26__FUNC_GPIO26>, 808 <PINMUX_GPIO46__FUNC_GPIO46>, 809 <PINMUX_GPIO47__FUNC_GPIO47>, 810 <PINMUX_GPIO48__FUNC_GPIO48>, 811 <PINMUX_GPIO65__FUNC_GPIO65>, 812 <PINMUX_GPIO66__FUNC_GPIO66>, 813 <PINMUX_GPIO67__FUNC_GPIO67>, 814 <PINMUX_GPIO68__FUNC_GPIO68>, 815 <PINMUX_GPIO128__FUNC_GPIO128>, 816 <PINMUX_GPIO129__FUNC_GPIO129>; 817 input-enable; 818 bias-pull-down; 819 }; 820 821 pins-low-power-pupd { 822 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 823 <PINMUX_GPIO78__FUNC_GPIO78>, 824 <PINMUX_GPIO79__FUNC_GPIO79>, 825 <PINMUX_GPIO80__FUNC_GPIO80>, 826 <PINMUX_GPIO83__FUNC_GPIO83>, 827 <PINMUX_GPIO85__FUNC_GPIO85>, 828 <PINMUX_GPIO90__FUNC_GPIO90>, 829 <PINMUX_GPIO91__FUNC_GPIO91>, 830 <PINMUX_GPIO93__FUNC_GPIO93>, 831 <PINMUX_GPIO94__FUNC_GPIO94>, 832 <PINMUX_GPIO95__FUNC_GPIO95>, 833 <PINMUX_GPIO96__FUNC_GPIO96>, 834 <PINMUX_GPIO104__FUNC_GPIO104>, 835 <PINMUX_GPIO105__FUNC_GPIO105>, 836 <PINMUX_GPIO107__FUNC_GPIO107>; 837 input-enable; 838 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 839 }; 840 }; 841 842 rt1019p_pins_default: rt1019p-default-pins { 843 pins-amp-sdb { 844 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>; 845 output-low; 846 }; 847 }; 848 849 scp_pins: scp-default-pins { 850 pins-vreq { 851 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 852 bias-disable; 853 input-enable; 854 }; 855 }; 856 857 spi0_pins: spi0-default-pins { 858 pins-cs-mosi-clk { 859 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 860 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 861 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 862 bias-disable; 863 }; 864 865 pins-miso { 866 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 867 bias-pull-down; 868 }; 869 }; 870 871 subpmic_default: subpmic-default-pins { 872 subpmic_pin_irq: pins-subpmic-int-n { 873 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 874 input-enable; 875 bias-pull-up; 876 }; 877 }; 878 879 trackpad_pins: trackpad-default-pins { 880 pins-int-n { 881 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 882 input-enable; 883 bias-pull-up; 884 }; 885 }; 886 887 touchscreen_pins: touchscreen-default-pins { 888 pins-int-n { 889 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 890 input-enable; 891 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 892 }; 893 pins-rst { 894 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 895 output-high; 896 }; 897 pins-report-sw { 898 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 899 output-low; 900 }; 901 }; 902}; 903 904&pmic { 905 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 906}; 907 908&scp { 909 status = "okay"; 910 911 firmware-name = "mediatek/mt8195/scp.img"; 912 memory-region = <&scp_mem>; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&scp_pins>; 915 916 cros-ec-rpmsg { 917 compatible = "google,cros-ec-rpmsg"; 918 mediatek,rpmsg-name = "cros-ec-rpmsg"; 919 }; 920}; 921 922&spi0 { 923 status = "okay"; 924 925 pinctrl-names = "default"; 926 pinctrl-0 = <&spi0_pins>; 927 mediatek,pad-select = <0>; 928 929 cros_ec: ec@0 { 930 #address-cells = <1>; 931 #size-cells = <0>; 932 933 compatible = "google,cros-ec-spi"; 934 reg = <0>; 935 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&cros_ec_int>; 938 spi-max-frequency = <3000000>; 939 940 keyboard-backlight { 941 compatible = "google,cros-kbd-led-backlight"; 942 }; 943 944 i2c_tunnel: i2c-tunnel { 945 compatible = "google,cros-ec-i2c-tunnel"; 946 google,remote-bus = <0>; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 }; 950 951 mt_pmic_vmc_ldo_reg: regulator@0 { 952 compatible = "google,cros-ec-regulator"; 953 reg = <0>; 954 regulator-name = "mt_pmic_vmc_ldo"; 955 regulator-min-microvolt = <1200000>; 956 regulator-max-microvolt = <3600000>; 957 }; 958 959 mt_pmic_vmch_ldo_reg: regulator@1 { 960 compatible = "google,cros-ec-regulator"; 961 reg = <1>; 962 regulator-name = "mt_pmic_vmch_ldo"; 963 regulator-min-microvolt = <2700000>; 964 regulator-max-microvolt = <3600000>; 965 }; 966 967 typec { 968 compatible = "google,cros-ec-typec"; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 972 usb_c0: connector@0 { 973 compatible = "usb-c-connector"; 974 reg = <0>; 975 power-role = "dual"; 976 data-role = "host"; 977 try-power-role = "source"; 978 }; 979 980 usb_c1: connector@1 { 981 compatible = "usb-c-connector"; 982 reg = <1>; 983 power-role = "dual"; 984 data-role = "host"; 985 try-power-role = "source"; 986 }; 987 }; 988 }; 989}; 990 991&spmi { 992 #address-cells = <2>; 993 #size-cells = <0>; 994 995 mt6315@6 { 996 compatible = "mediatek,mt6315-regulator"; 997 reg = <0x6 SPMI_USID>; 998 999 regulators { 1000 mt6315_6_vbuck1: vbuck1 { 1001 regulator-compatible = "vbuck1"; 1002 regulator-name = "Vbcpu"; 1003 regulator-min-microvolt = <300000>; 1004 regulator-max-microvolt = <1193750>; 1005 regulator-enable-ramp-delay = <256>; 1006 regulator-ramp-delay = <6250>; 1007 regulator-allowed-modes = <0 1 2>; 1008 regulator-always-on; 1009 }; 1010 }; 1011 }; 1012 1013 mt6315@7 { 1014 compatible = "mediatek,mt6315-regulator"; 1015 reg = <0x7 SPMI_USID>; 1016 1017 regulators { 1018 mt6315_7_vbuck1: vbuck1 { 1019 regulator-compatible = "vbuck1"; 1020 regulator-name = "Vgpu"; 1021 regulator-min-microvolt = <625000>; 1022 regulator-max-microvolt = <1193750>; 1023 regulator-enable-ramp-delay = <256>; 1024 regulator-ramp-delay = <6250>; 1025 regulator-allowed-modes = <0 1 2>; 1026 regulator-always-on; 1027 }; 1028 }; 1029 }; 1030}; 1031 1032&u3phy0 { 1033 status = "okay"; 1034}; 1035 1036&u3phy1 { 1037 status = "okay"; 1038}; 1039 1040&u3phy2 { 1041 status = "okay"; 1042}; 1043 1044&u3phy3 { 1045 status = "okay"; 1046}; 1047 1048&uart0 { 1049 status = "okay"; 1050}; 1051 1052&xhci0 { 1053 status = "okay"; 1054 1055 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1056 vbus-supply = <&usb_vbus>; 1057}; 1058 1059&xhci1 { 1060 status = "okay"; 1061 1062 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1063 vbus-supply = <&usb_vbus>; 1064}; 1065 1066&xhci2 { 1067 status = "okay"; 1068 1069 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1070 vbus-supply = <&usb_vbus>; 1071}; 1072 1073&xhci3 { 1074 status = "okay"; 1075 1076 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1077 usb2-lpm-disable; 1078 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1079 vbus-supply = <&usb_vbus>; 1080}; 1081 1082#include <arm/cros-ec-keyboard.dtsi> 1083#include <arm/cros-ec-sbs.dtsi> 1084 1085&keyboard_controller { 1086 function-row-physmap = < 1087 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1088 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1089 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1090 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1091 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1092 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1093 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1094 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1095 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1096 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1097 >; 1098 1099 linux,keymap = < 1100 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1101 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1102 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1103 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1104 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 1105 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 1106 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 1107 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1108 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1109 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1110 1111 CROS_STD_MAIN_KEYMAP 1112 >; 1113}; 1114