1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include "mt8195.dtsi"
8#include "mt6359.dtsi"
9
10/ {
11	aliases {
12		i2c0 = &i2c0;
13		i2c1 = &i2c1;
14		i2c2 = &i2c2;
15		i2c3 = &i2c3;
16		i2c4 = &i2c4;
17		i2c5 = &i2c5;
18		i2c7 = &i2c7;
19		mmc0 = &mmc0;
20		serial0 = &uart0;
21	};
22
23	chosen {
24		stdout-path = "serial0:115200n8";
25	};
26
27	memory@40000000 {
28		device_type = "memory";
29		reg = <0 0x40000000 0 0x80000000>;
30	};
31
32	/* system wide LDO 3.3V power rail */
33	pp3300_z5: regulator-pp3300-ldo-z5 {
34		compatible = "regulator-fixed";
35		regulator-name = "pp3300_ldo_z5";
36		regulator-always-on;
37		regulator-boot-on;
38		regulator-min-microvolt = <3300000>;
39		regulator-max-microvolt = <3300000>;
40		vin-supply = <&ppvar_sys>;
41	};
42
43	/* separately switched 3.3V power rail */
44	pp3300_s3: regulator-pp3300-s3 {
45		compatible = "regulator-fixed";
46		regulator-name = "pp3300_s3";
47		/* automatically sequenced by PMIC EXT_PMIC_EN2 */
48		regulator-always-on;
49		regulator-boot-on;
50		regulator-min-microvolt = <3300000>;
51		regulator-max-microvolt = <3300000>;
52		vin-supply = <&pp3300_z2>;
53	};
54
55	/* system wide 3.3V power rail */
56	pp3300_z2: regulator-pp3300-z2 {
57		compatible = "regulator-fixed";
58		regulator-name = "pp3300_z2";
59		/* EN pin tied to pp4200_z2, which is controlled by EC */
60		regulator-always-on;
61		regulator-boot-on;
62		regulator-min-microvolt = <3300000>;
63		regulator-max-microvolt = <3300000>;
64		vin-supply = <&ppvar_sys>;
65	};
66
67	/* system wide 4.2V power rail */
68	pp4200_z2: regulator-pp4200-z2 {
69		compatible = "regulator-fixed";
70		regulator-name = "pp4200_z2";
71		/* controlled by EC */
72		regulator-always-on;
73		regulator-boot-on;
74		regulator-min-microvolt = <4200000>;
75		regulator-max-microvolt = <4200000>;
76		vin-supply = <&ppvar_sys>;
77	};
78
79	/* system wide switching 5.0V power rail */
80	pp5000_s5: regulator-pp5000-s5 {
81		compatible = "regulator-fixed";
82		regulator-name = "pp5000_s5";
83		/* controlled by EC */
84		regulator-always-on;
85		regulator-boot-on;
86		regulator-min-microvolt = <5000000>;
87		regulator-max-microvolt = <5000000>;
88		vin-supply = <&ppvar_sys>;
89	};
90
91	/* system wide semi-regulated power rail from battery or USB */
92	ppvar_sys: regulator-ppvar-sys {
93		compatible = "regulator-fixed";
94		regulator-name = "ppvar_sys";
95		regulator-always-on;
96		regulator-boot-on;
97	};
98
99	usb_vbus: regulator-5v0-usb-vbus {
100		compatible = "regulator-fixed";
101		regulator-name = "usb-vbus";
102		regulator-min-microvolt = <5000000>;
103		regulator-max-microvolt = <5000000>;
104		enable-active-high;
105		regulator-always-on;
106	};
107};
108
109&i2c0 {
110	status = "okay";
111
112	clock-frequency = <400000>;
113	pinctrl-names = "default";
114	pinctrl-0 = <&i2c0_pins>;
115};
116
117&i2c1 {
118	status = "okay";
119
120	clock-frequency = <400000>;
121	i2c-scl-internal-delay-ns = <12500>;
122	pinctrl-names = "default";
123	pinctrl-0 = <&i2c1_pins>;
124};
125
126&i2c2 {
127	status = "okay";
128
129	clock-frequency = <400000>;
130	pinctrl-names = "default";
131	pinctrl-0 = <&i2c2_pins>;
132};
133
134&i2c3 {
135	status = "okay";
136
137	clock-frequency = <400000>;
138	pinctrl-names = "default";
139	pinctrl-0 = <&i2c3_pins>;
140};
141
142&i2c4 {
143	status = "okay";
144
145	clock-frequency = <400000>;
146	pinctrl-names = "default";
147	pinctrl-0 = <&i2c4_pins>;
148};
149
150&i2c5 {
151	status = "okay";
152
153	clock-frequency = <400000>;
154	pinctrl-names = "default";
155	pinctrl-0 = <&i2c5_pins>;
156};
157
158&i2c7 {
159	status = "okay";
160
161	clock-frequency = <400000>;
162	pinctrl-names = "default";
163	pinctrl-0 = <&i2c7_pins>;
164
165	pmic@34 {
166		#interrupt-cells = <1>;
167		compatible = "mediatek,mt6360";
168		reg = <0x34>;
169		interrupt-controller;
170		interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>;
171		interrupt-names = "IRQB";
172		pinctrl-names = "default";
173		pinctrl-0 = <&subpmic_default>;
174		wakeup-source;
175	};
176};
177
178&mmc0 {
179	status = "okay";
180
181	bus-width = <8>;
182	cap-mmc-highspeed;
183	cap-mmc-hw-reset;
184	hs400-ds-delay = <0x14c11>;
185	max-frequency = <200000000>;
186	mmc-hs200-1_8v;
187	mmc-hs400-1_8v;
188	no-sdio;
189	no-sd;
190	non-removable;
191	pinctrl-names = "default", "state_uhs";
192	pinctrl-0 = <&mmc0_pins_default>;
193	pinctrl-1 = <&mmc0_pins_uhs>;
194	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
195	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
196};
197
198/* for CPU-L */
199&mt6359_vcore_buck_reg {
200	regulator-always-on;
201};
202
203/* for CORE */
204&mt6359_vgpu11_buck_reg {
205	regulator-always-on;
206};
207
208&mt6359_vgpu11_sshub_buck_reg {
209	regulator-always-on;
210	regulator-min-microvolt = <550000>;
211	regulator-max-microvolt = <550000>;
212};
213
214/* for CORE SRAM */
215&mt6359_vpu_buck_reg {
216	regulator-always-on;
217};
218
219&mt6359_vrf12_ldo_reg {
220	regulator-always-on;
221};
222
223/* for GPU SRAM */
224&mt6359_vsram_others_ldo_reg {
225	regulator-always-on;
226	regulator-min-microvolt = <750000>;
227	regulator-max-microvolt = <750000>;
228};
229
230&mt6359_vufs_ldo_reg {
231	regulator-always-on;
232};
233
234&pio {
235	mediatek,rsel-resistance-in-si-unit;
236	pinctrl-names = "default";
237	pinctrl-0 = <&pio_default>;
238
239	/* 144 lines */
240	gpio-line-names =
241		"I2S_SPKR_MCLK",
242		"I2S_SPKR_DATAIN",
243		"I2S_SPKR_LRCK",
244		"I2S_SPKR_BCLK",
245		"EC_AP_INT_ODL",
246		/*
247		 * AP_FLASH_WP_L is crossystem ABI. Schematics
248		 * call it AP_FLASH_WP_ODL.
249		 */
250		"AP_FLASH_WP_L",
251		"TCHPAD_INT_ODL",
252		"EDP_HPD_1V8",
253		"AP_I2C_CAM_SDA",
254		"AP_I2C_CAM_SCL",
255		"AP_I2C_TCHPAD_SDA_1V8",
256		"AP_I2C_TCHPAD_SCL_1V8",
257		"AP_I2C_AUD_SDA",
258		"AP_I2C_AUD_SCL",
259		"AP_I2C_TPM_SDA_1V8",
260		"AP_I2C_TPM_SCL_1V8",
261		"AP_I2C_TCHSCR_SDA_1V8",
262		"AP_I2C_TCHSCR_SCL_1V8",
263		"EC_AP_HPD_OD",
264		"",
265		"PCIE_NVME_RST_L",
266		"PCIE_NVME_CLKREQ_ODL",
267		"PCIE_RST_1V8_L",
268		"PCIE_CLKREQ_1V8_ODL",
269		"PCIE_WAKE_1V8_ODL",
270		"CLK_24M_CAM0",
271		"CAM1_SEN_EN",
272		"AP_I2C_PWR_SCL_1V8",
273		"AP_I2C_PWR_SDA_1V8",
274		"AP_I2C_MISC_SCL",
275		"AP_I2C_MISC_SDA",
276		"EN_PP5000_HDMI_X",
277		"AP_HDMITX_HTPLG",
278		"",
279		"AP_HDMITX_SCL_1V8",
280		"AP_HDMITX_SDA_1V8",
281		"AP_RTC_CLK32K",
282		"AP_EC_WATCHDOG_L",
283		"SRCLKENA0",
284		"SRCLKENA1",
285		"PWRAP_SPI0_CS_L",
286		"PWRAP_SPI0_CK",
287		"PWRAP_SPI0_MOSI",
288		"PWRAP_SPI0_MISO",
289		"SPMI_SCL",
290		"SPMI_SDA",
291		"",
292		"",
293		"",
294		"I2S_HP_DATAIN",
295		"I2S_HP_MCLK",
296		"I2S_HP_BCK",
297		"I2S_HP_LRCK",
298		"I2S_HP_DATAOUT",
299		"SD_CD_ODL",
300		"EN_PP3300_DISP_X",
301		"TCHSCR_RST_1V8_L",
302		"TCHSCR_REPORT_DISABLE",
303		"EN_PP3300_WLAN_X",
304		"BT_KILL_1V8_L",
305		"I2S_SPKR_DATAOUT",
306		"WIFI_KILL_1V8_L",
307		"BEEP_ON",
308		"SCP_I2C_SENSOR_SCL_1V8",
309		"SCP_I2C_SENSOR_SDA_1V8",
310		"",
311		"",
312		"",
313		"",
314		"AUD_CLK_MOSI",
315		"AUD_SYNC_MOSI",
316		"AUD_DAT_MOSI0",
317		"AUD_DAT_MOSI1",
318		"AUD_DAT_MISO0",
319		"AUD_DAT_MISO1",
320		"AUD_DAT_MISO2",
321		"SCP_VREQ_VAO",
322		"AP_SPI_GSC_TPM_CLK",
323		"AP_SPI_GSC_TPM_MOSI",
324		"AP_SPI_GSC_TPM_CS_L",
325		"AP_SPI_GSC_TPM_MISO",
326		"EN_PP1000_CAM_X",
327		"AP_EDP_BKLTEN",
328		"",
329		"USB3_HUB_RST_L",
330		"",
331		"WLAN_ALERT_ODL",
332		"EC_IN_RW_ODL",
333		"GSC_AP_INT_ODL",
334		"HP_INT_ODL",
335		"CAM0_RST_L",
336		"CAM1_RST_L",
337		"TCHSCR_INT_1V8_L",
338		"CAM1_DET_L",
339		"RST_ALC1011_L",
340		"",
341		"",
342		"BL_PWM_1V8",
343		"UART_AP_TX_DBG_RX",
344		"UART_DBG_TX_AP_RX",
345		"EN_SPKR",
346		"AP_EC_WARM_RST_REQ",
347		"UART_SCP_TX_DBGCON_RX",
348		"UART_DBGCON_TX_SCP_RX",
349		"",
350		"",
351		"KPCOL0",
352		"",
353		"MT6315_GPU_INT",
354		"MT6315_PROC_BC_INT",
355		"SD_CMD",
356		"SD_CLK",
357		"SD_DAT0",
358		"SD_DAT1",
359		"SD_DAT2",
360		"SD_DAT3",
361		"EMMC_DAT7",
362		"EMMC_DAT6",
363		"EMMC_DAT5",
364		"EMMC_DAT4",
365		"EMMC_RSTB",
366		"EMMC_CMD",
367		"EMMC_CLK",
368		"EMMC_DAT3",
369		"EMMC_DAT2",
370		"EMMC_DAT1",
371		"EMMC_DAT0",
372		"EMMC_DSL",
373		"",
374		"",
375		"MT6360_INT_ODL",
376		"SCP_JTAG0_TRSTN",
377		"AP_SPI_EC_CS_L",
378		"AP_SPI_EC_CLK",
379		"AP_SPI_EC_MOSI",
380		"AP_SPI_EC_MISO",
381		"SCP_JTAG0_TMS",
382		"SCP_JTAG0_TCK",
383		"SCP_JTAG0_TDO",
384		"SCP_JTAG0_TDI",
385		"AP_SPI_FLASH_CS_L",
386		"AP_SPI_FLASH_CLK",
387		"AP_SPI_FLASH_MOSI",
388		"AP_SPI_FLASH_MISO";
389
390	i2c0_pins: i2c0-default-pins {
391		pins-bus {
392			pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
393				 <PINMUX_GPIO9__FUNC_SCL0>;
394			bias-disable;
395			drive-strength-microamp = <1000>;
396		};
397	};
398
399	i2c1_pins: i2c1-default-pins {
400		pins-bus {
401			pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
402				 <PINMUX_GPIO11__FUNC_SCL1>;
403			bias-pull-up = <1000>;
404			drive-strength-microamp = <1000>;
405		};
406	};
407
408	i2c2_pins: i2c2-default-pins {
409		pins-bus {
410			pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
411				 <PINMUX_GPIO13__FUNC_SCL2>;
412			bias-disable;
413			drive-strength-microamp = <1000>;
414		};
415	};
416
417	i2c3_pins: i2c3-default-pins {
418		pins-bus {
419			pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
420				 <PINMUX_GPIO15__FUNC_SCL3>;
421			bias-pull-up = <1000>;
422			drive-strength-microamp = <1000>;
423		};
424	};
425
426	i2c4_pins: i2c4-default-pins {
427		pins-bus {
428			pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
429				 <PINMUX_GPIO17__FUNC_SCL4>;
430			bias-pull-up = <1000>;
431			drive-strength = <4>;
432		};
433	};
434
435	i2c5_pins: i2c5-default-pins {
436		pins-bus {
437			pinmux = <PINMUX_GPIO29__FUNC_SCL5>,
438				 <PINMUX_GPIO30__FUNC_SDA5>;
439			bias-disable;
440			drive-strength-microamp = <1000>;
441		};
442	};
443
444	i2c7_pins: i2c7-default-pins {
445		pins-bus {
446			pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
447				 <PINMUX_GPIO28__FUNC_SDA7>;
448			bias-disable;
449		};
450	};
451
452	mmc0_pins_default: mmc0-default-pins {
453		pins-cmd-dat {
454			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
455				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
456				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
457				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
458				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
459				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
460				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
461				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
462				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
463			input-enable;
464			drive-strength = <6>;
465			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
466		};
467
468		pins-clk {
469			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
470			drive-strength = <6>;
471			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
472		};
473
474		pins-rst {
475			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
476			drive-strength = <6>;
477			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
478		};
479	};
480
481	mmc0_pins_uhs: mmc0-uhs-pins {
482		pins-cmd-dat {
483			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
484				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
485				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
486				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
487				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
488				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
489				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
490				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
491				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
492			input-enable;
493			drive-strength = <8>;
494			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
495		};
496
497		pins-clk {
498			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
499			drive-strength = <8>;
500			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
501		};
502
503		pins-ds {
504			pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
505			drive-strength = <8>;
506			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
507		};
508
509		pins-rst {
510			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
511			drive-strength = <8>;
512			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
513		};
514	};
515
516	pio_default: pio-default-pins {
517		pins-wifi-enable {
518			pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
519			output-high;
520			drive-strength = <14>;
521		};
522
523		pins-low-power-pd {
524			pinmux = <PINMUX_GPIO25__FUNC_GPIO25>,
525				 <PINMUX_GPIO26__FUNC_GPIO26>,
526				 <PINMUX_GPIO46__FUNC_GPIO46>,
527				 <PINMUX_GPIO47__FUNC_GPIO47>,
528				 <PINMUX_GPIO48__FUNC_GPIO48>,
529				 <PINMUX_GPIO65__FUNC_GPIO65>,
530				 <PINMUX_GPIO66__FUNC_GPIO66>,
531				 <PINMUX_GPIO67__FUNC_GPIO67>,
532				 <PINMUX_GPIO68__FUNC_GPIO68>,
533				 <PINMUX_GPIO128__FUNC_GPIO128>,
534				 <PINMUX_GPIO129__FUNC_GPIO129>;
535			input-enable;
536			bias-pull-down;
537		};
538
539		pins-low-power-pupd {
540			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
541				 <PINMUX_GPIO78__FUNC_GPIO78>,
542				 <PINMUX_GPIO79__FUNC_GPIO79>,
543				 <PINMUX_GPIO80__FUNC_GPIO80>,
544				 <PINMUX_GPIO83__FUNC_GPIO83>,
545				 <PINMUX_GPIO85__FUNC_GPIO85>,
546				 <PINMUX_GPIO90__FUNC_GPIO90>,
547				 <PINMUX_GPIO91__FUNC_GPIO91>,
548				 <PINMUX_GPIO93__FUNC_GPIO93>,
549				 <PINMUX_GPIO94__FUNC_GPIO94>,
550				 <PINMUX_GPIO95__FUNC_GPIO95>,
551				 <PINMUX_GPIO96__FUNC_GPIO96>,
552				 <PINMUX_GPIO104__FUNC_GPIO104>,
553				 <PINMUX_GPIO105__FUNC_GPIO105>,
554				 <PINMUX_GPIO107__FUNC_GPIO107>;
555			input-enable;
556			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
557		};
558	};
559
560	spi0_pins: spi0-default-pins {
561		pins-cs-mosi-clk {
562			pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
563				 <PINMUX_GPIO134__FUNC_SPIM0_MO>,
564				 <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
565			bias-disable;
566		};
567
568		pins-miso {
569			pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
570			bias-pull-down;
571		};
572	};
573
574	subpmic_default: subpmic-default-pins {
575		subpmic_pin_irq: pins-subpmic-int-n {
576			pinmux = <PINMUX_GPIO130__FUNC_GPIO130>;
577			input-enable;
578			bias-pull-up;
579		};
580	};
581};
582
583&pmic {
584	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
585};
586
587&spi0 {
588	status = "okay";
589
590	pinctrl-names = "default";
591	pinctrl-0 = <&spi0_pins>;
592	mediatek,pad-select = <0>;
593};
594
595&u3phy0 {
596	status = "okay";
597};
598
599&u3phy1 {
600	status = "okay";
601};
602
603&u3phy2 {
604	status = "okay";
605};
606
607&u3phy3 {
608	status = "okay";
609};
610
611&uart0 {
612	status = "okay";
613};
614
615&xhci0 {
616	status = "okay";
617
618	vusb33-supply = <&mt6359_vusb_ldo_reg>;
619	vbus-supply = <&usb_vbus>;
620};
621
622&xhci1 {
623	status = "okay";
624
625	vusb33-supply = <&mt6359_vusb_ldo_reg>;
626	vbus-supply = <&usb_vbus>;
627};
628
629&xhci2 {
630	status = "okay";
631
632	vusb33-supply = <&mt6359_vusb_ldo_reg>;
633	vbus-supply = <&usb_vbus>;
634};
635
636&xhci3 {
637	status = "okay";
638
639	/* MT7921's USB Bluetooth has issues with USB2 LPM */
640	usb2-lpm-disable;
641	vusb33-supply = <&mt6359_vusb_ldo_reg>;
642	vbus-supply = <&usb_vbus>;
643};
644