1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include "mt8195.dtsi" 8#include "mt6359.dtsi" 9 10/ { 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 /* system wide LDO 3.3V power rail */ 34 pp3300_z5: regulator-pp3300-ldo-z5 { 35 compatible = "regulator-fixed"; 36 regulator-name = "pp3300_ldo_z5"; 37 regulator-always-on; 38 regulator-boot-on; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 vin-supply = <&ppvar_sys>; 42 }; 43 44 /* separately switched 3.3V power rail */ 45 pp3300_s3: regulator-pp3300-s3 { 46 compatible = "regulator-fixed"; 47 regulator-name = "pp3300_s3"; 48 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 49 regulator-always-on; 50 regulator-boot-on; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; 53 vin-supply = <&pp3300_z2>; 54 }; 55 56 /* system wide 3.3V power rail */ 57 pp3300_z2: regulator-pp3300-z2 { 58 compatible = "regulator-fixed"; 59 regulator-name = "pp3300_z2"; 60 /* EN pin tied to pp4200_z2, which is controlled by EC */ 61 regulator-always-on; 62 regulator-boot-on; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 vin-supply = <&ppvar_sys>; 66 }; 67 68 /* system wide 4.2V power rail */ 69 pp4200_z2: regulator-pp4200-z2 { 70 compatible = "regulator-fixed"; 71 regulator-name = "pp4200_z2"; 72 /* controlled by EC */ 73 regulator-always-on; 74 regulator-boot-on; 75 regulator-min-microvolt = <4200000>; 76 regulator-max-microvolt = <4200000>; 77 vin-supply = <&ppvar_sys>; 78 }; 79 80 /* system wide switching 5.0V power rail */ 81 pp5000_s5: regulator-pp5000-s5 { 82 compatible = "regulator-fixed"; 83 regulator-name = "pp5000_s5"; 84 /* controlled by EC */ 85 regulator-always-on; 86 regulator-boot-on; 87 regulator-min-microvolt = <5000000>; 88 regulator-max-microvolt = <5000000>; 89 vin-supply = <&ppvar_sys>; 90 }; 91 92 /* system wide semi-regulated power rail from battery or USB */ 93 ppvar_sys: regulator-ppvar-sys { 94 compatible = "regulator-fixed"; 95 regulator-name = "ppvar_sys"; 96 regulator-always-on; 97 regulator-boot-on; 98 }; 99 100 usb_vbus: regulator-5v0-usb-vbus { 101 compatible = "regulator-fixed"; 102 regulator-name = "usb-vbus"; 103 regulator-min-microvolt = <5000000>; 104 regulator-max-microvolt = <5000000>; 105 enable-active-high; 106 regulator-always-on; 107 }; 108 109 reserved_memory: reserved-memory { 110 #address-cells = <2>; 111 #size-cells = <2>; 112 ranges; 113 114 scp_mem: memory@50000000 { 115 compatible = "shared-dma-pool"; 116 reg = <0 0x50000000 0 0x2900000>; 117 no-map; 118 }; 119 }; 120}; 121 122&i2c0 { 123 status = "okay"; 124 125 clock-frequency = <400000>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&i2c0_pins>; 128}; 129 130&i2c1 { 131 status = "okay"; 132 133 clock-frequency = <400000>; 134 i2c-scl-internal-delay-ns = <12500>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&i2c1_pins>; 137}; 138 139&i2c2 { 140 status = "okay"; 141 142 clock-frequency = <400000>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&i2c2_pins>; 145}; 146 147&i2c3 { 148 status = "okay"; 149 150 clock-frequency = <400000>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&i2c3_pins>; 153 154 tpm@50 { 155 compatible = "google,cr50"; 156 reg = <0x50>; 157 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&cr50_int>; 160 }; 161}; 162 163&i2c4 { 164 status = "okay"; 165 166 clock-frequency = <400000>; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&i2c4_pins>; 169 170 ts_10: touchscreen@10 { 171 compatible = "hid-over-i2c"; 172 reg = <0x10>; 173 hid-descr-addr = <0x0001>; 174 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&touchscreen_pins>; 177 post-power-on-delay-ms = <10>; 178 vdd-supply = <&pp3300_s3>; 179 status = "disabled"; 180 }; 181}; 182 183&i2c5 { 184 status = "okay"; 185 186 clock-frequency = <400000>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&i2c5_pins>; 189}; 190 191&i2c7 { 192 status = "okay"; 193 194 clock-frequency = <400000>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&i2c7_pins>; 197 198 pmic@34 { 199 #interrupt-cells = <1>; 200 compatible = "mediatek,mt6360"; 201 reg = <0x34>; 202 interrupt-controller; 203 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 204 interrupt-names = "IRQB"; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&subpmic_default>; 207 wakeup-source; 208 }; 209}; 210 211&mmc0 { 212 status = "okay"; 213 214 bus-width = <8>; 215 cap-mmc-highspeed; 216 cap-mmc-hw-reset; 217 hs400-ds-delay = <0x14c11>; 218 max-frequency = <200000000>; 219 mmc-hs200-1_8v; 220 mmc-hs400-1_8v; 221 no-sdio; 222 no-sd; 223 non-removable; 224 pinctrl-names = "default", "state_uhs"; 225 pinctrl-0 = <&mmc0_pins_default>; 226 pinctrl-1 = <&mmc0_pins_uhs>; 227 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 228 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 229}; 230 231&mmc1 { 232 status = "okay"; 233 234 bus-width = <4>; 235 cap-sd-highspeed; 236 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 237 max-frequency = <200000000>; 238 no-mmc; 239 no-sdio; 240 pinctrl-names = "default", "state_uhs"; 241 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 242 pinctrl-1 = <&mmc1_pins_default>; 243 sd-uhs-sdr50; 244 sd-uhs-sdr104; 245 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 246 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 247}; 248 249/* for CPU-L */ 250&mt6359_vcore_buck_reg { 251 regulator-always-on; 252}; 253 254/* for CORE */ 255&mt6359_vgpu11_buck_reg { 256 regulator-always-on; 257}; 258 259&mt6359_vgpu11_sshub_buck_reg { 260 regulator-always-on; 261 regulator-min-microvolt = <550000>; 262 regulator-max-microvolt = <550000>; 263}; 264 265/* for CORE SRAM */ 266&mt6359_vpu_buck_reg { 267 regulator-always-on; 268}; 269 270&mt6359_vrf12_ldo_reg { 271 regulator-always-on; 272}; 273 274/* for GPU SRAM */ 275&mt6359_vsram_others_ldo_reg { 276 regulator-always-on; 277 regulator-min-microvolt = <750000>; 278 regulator-max-microvolt = <750000>; 279}; 280 281&mt6359_vufs_ldo_reg { 282 regulator-always-on; 283}; 284 285&nor_flash { 286 status = "okay"; 287 288 pinctrl-names = "default"; 289 pinctrl-0 = <&nor_pins_default>; 290 291 flash@0 { 292 compatible = "jedec,spi-nor"; 293 reg = <0>; 294 spi-max-frequency = <52000000>; 295 spi-rx-bus-width = <2>; 296 spi-tx-bus-width = <2>; 297 }; 298}; 299 300&pio { 301 mediatek,rsel-resistance-in-si-unit; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pio_default>; 304 305 /* 144 lines */ 306 gpio-line-names = 307 "I2S_SPKR_MCLK", 308 "I2S_SPKR_DATAIN", 309 "I2S_SPKR_LRCK", 310 "I2S_SPKR_BCLK", 311 "EC_AP_INT_ODL", 312 /* 313 * AP_FLASH_WP_L is crossystem ABI. Schematics 314 * call it AP_FLASH_WP_ODL. 315 */ 316 "AP_FLASH_WP_L", 317 "TCHPAD_INT_ODL", 318 "EDP_HPD_1V8", 319 "AP_I2C_CAM_SDA", 320 "AP_I2C_CAM_SCL", 321 "AP_I2C_TCHPAD_SDA_1V8", 322 "AP_I2C_TCHPAD_SCL_1V8", 323 "AP_I2C_AUD_SDA", 324 "AP_I2C_AUD_SCL", 325 "AP_I2C_TPM_SDA_1V8", 326 "AP_I2C_TPM_SCL_1V8", 327 "AP_I2C_TCHSCR_SDA_1V8", 328 "AP_I2C_TCHSCR_SCL_1V8", 329 "EC_AP_HPD_OD", 330 "", 331 "PCIE_NVME_RST_L", 332 "PCIE_NVME_CLKREQ_ODL", 333 "PCIE_RST_1V8_L", 334 "PCIE_CLKREQ_1V8_ODL", 335 "PCIE_WAKE_1V8_ODL", 336 "CLK_24M_CAM0", 337 "CAM1_SEN_EN", 338 "AP_I2C_PWR_SCL_1V8", 339 "AP_I2C_PWR_SDA_1V8", 340 "AP_I2C_MISC_SCL", 341 "AP_I2C_MISC_SDA", 342 "EN_PP5000_HDMI_X", 343 "AP_HDMITX_HTPLG", 344 "", 345 "AP_HDMITX_SCL_1V8", 346 "AP_HDMITX_SDA_1V8", 347 "AP_RTC_CLK32K", 348 "AP_EC_WATCHDOG_L", 349 "SRCLKENA0", 350 "SRCLKENA1", 351 "PWRAP_SPI0_CS_L", 352 "PWRAP_SPI0_CK", 353 "PWRAP_SPI0_MOSI", 354 "PWRAP_SPI0_MISO", 355 "SPMI_SCL", 356 "SPMI_SDA", 357 "", 358 "", 359 "", 360 "I2S_HP_DATAIN", 361 "I2S_HP_MCLK", 362 "I2S_HP_BCK", 363 "I2S_HP_LRCK", 364 "I2S_HP_DATAOUT", 365 "SD_CD_ODL", 366 "EN_PP3300_DISP_X", 367 "TCHSCR_RST_1V8_L", 368 "TCHSCR_REPORT_DISABLE", 369 "EN_PP3300_WLAN_X", 370 "BT_KILL_1V8_L", 371 "I2S_SPKR_DATAOUT", 372 "WIFI_KILL_1V8_L", 373 "BEEP_ON", 374 "SCP_I2C_SENSOR_SCL_1V8", 375 "SCP_I2C_SENSOR_SDA_1V8", 376 "", 377 "", 378 "", 379 "", 380 "AUD_CLK_MOSI", 381 "AUD_SYNC_MOSI", 382 "AUD_DAT_MOSI0", 383 "AUD_DAT_MOSI1", 384 "AUD_DAT_MISO0", 385 "AUD_DAT_MISO1", 386 "AUD_DAT_MISO2", 387 "SCP_VREQ_VAO", 388 "AP_SPI_GSC_TPM_CLK", 389 "AP_SPI_GSC_TPM_MOSI", 390 "AP_SPI_GSC_TPM_CS_L", 391 "AP_SPI_GSC_TPM_MISO", 392 "EN_PP1000_CAM_X", 393 "AP_EDP_BKLTEN", 394 "", 395 "USB3_HUB_RST_L", 396 "", 397 "WLAN_ALERT_ODL", 398 "EC_IN_RW_ODL", 399 "GSC_AP_INT_ODL", 400 "HP_INT_ODL", 401 "CAM0_RST_L", 402 "CAM1_RST_L", 403 "TCHSCR_INT_1V8_L", 404 "CAM1_DET_L", 405 "RST_ALC1011_L", 406 "", 407 "", 408 "BL_PWM_1V8", 409 "UART_AP_TX_DBG_RX", 410 "UART_DBG_TX_AP_RX", 411 "EN_SPKR", 412 "AP_EC_WARM_RST_REQ", 413 "UART_SCP_TX_DBGCON_RX", 414 "UART_DBGCON_TX_SCP_RX", 415 "", 416 "", 417 "KPCOL0", 418 "", 419 "MT6315_GPU_INT", 420 "MT6315_PROC_BC_INT", 421 "SD_CMD", 422 "SD_CLK", 423 "SD_DAT0", 424 "SD_DAT1", 425 "SD_DAT2", 426 "SD_DAT3", 427 "EMMC_DAT7", 428 "EMMC_DAT6", 429 "EMMC_DAT5", 430 "EMMC_DAT4", 431 "EMMC_RSTB", 432 "EMMC_CMD", 433 "EMMC_CLK", 434 "EMMC_DAT3", 435 "EMMC_DAT2", 436 "EMMC_DAT1", 437 "EMMC_DAT0", 438 "EMMC_DSL", 439 "", 440 "", 441 "MT6360_INT_ODL", 442 "SCP_JTAG0_TRSTN", 443 "AP_SPI_EC_CS_L", 444 "AP_SPI_EC_CLK", 445 "AP_SPI_EC_MOSI", 446 "AP_SPI_EC_MISO", 447 "SCP_JTAG0_TMS", 448 "SCP_JTAG0_TCK", 449 "SCP_JTAG0_TDO", 450 "SCP_JTAG0_TDI", 451 "AP_SPI_FLASH_CS_L", 452 "AP_SPI_FLASH_CLK", 453 "AP_SPI_FLASH_MOSI", 454 "AP_SPI_FLASH_MISO"; 455 456 cr50_int: cr50-irq-default-pins { 457 pins-gsc-ap-int-odl { 458 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 459 input-enable; 460 }; 461 }; 462 463 cros_ec_int: cros-ec-irq-default-pins { 464 pins-ec-ap-int-odl { 465 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 466 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 467 input-enable; 468 }; 469 }; 470 471 i2c0_pins: i2c0-default-pins { 472 pins-bus { 473 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 474 <PINMUX_GPIO9__FUNC_SCL0>; 475 bias-disable; 476 drive-strength-microamp = <1000>; 477 }; 478 }; 479 480 i2c1_pins: i2c1-default-pins { 481 pins-bus { 482 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 483 <PINMUX_GPIO11__FUNC_SCL1>; 484 bias-pull-up = <1000>; 485 drive-strength-microamp = <1000>; 486 }; 487 }; 488 489 i2c2_pins: i2c2-default-pins { 490 pins-bus { 491 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 492 <PINMUX_GPIO13__FUNC_SCL2>; 493 bias-disable; 494 drive-strength-microamp = <1000>; 495 }; 496 }; 497 498 i2c3_pins: i2c3-default-pins { 499 pins-bus { 500 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 501 <PINMUX_GPIO15__FUNC_SCL3>; 502 bias-pull-up = <1000>; 503 drive-strength-microamp = <1000>; 504 }; 505 }; 506 507 i2c4_pins: i2c4-default-pins { 508 pins-bus { 509 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 510 <PINMUX_GPIO17__FUNC_SCL4>; 511 bias-pull-up = <1000>; 512 drive-strength = <4>; 513 }; 514 }; 515 516 i2c5_pins: i2c5-default-pins { 517 pins-bus { 518 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 519 <PINMUX_GPIO30__FUNC_SDA5>; 520 bias-disable; 521 drive-strength-microamp = <1000>; 522 }; 523 }; 524 525 i2c7_pins: i2c7-default-pins { 526 pins-bus { 527 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 528 <PINMUX_GPIO28__FUNC_SDA7>; 529 bias-disable; 530 }; 531 }; 532 533 mmc0_pins_default: mmc0-default-pins { 534 pins-cmd-dat { 535 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 536 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 537 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 538 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 539 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 540 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 541 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 542 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 543 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 544 input-enable; 545 drive-strength = <6>; 546 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 547 }; 548 549 pins-clk { 550 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 551 drive-strength = <6>; 552 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 553 }; 554 555 pins-rst { 556 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 557 drive-strength = <6>; 558 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 559 }; 560 }; 561 562 mmc0_pins_uhs: mmc0-uhs-pins { 563 pins-cmd-dat { 564 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 565 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 566 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 567 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 568 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 569 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 570 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 571 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 572 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 573 input-enable; 574 drive-strength = <8>; 575 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 576 }; 577 578 pins-clk { 579 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 580 drive-strength = <8>; 581 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 582 }; 583 584 pins-ds { 585 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 586 drive-strength = <8>; 587 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 588 }; 589 590 pins-rst { 591 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 592 drive-strength = <8>; 593 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 594 }; 595 }; 596 597 mmc1_pins_detect: mmc1-detect-pins { 598 pins-insert { 599 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 600 bias-pull-up; 601 }; 602 }; 603 604 mmc1_pins_default: mmc1-default-pins { 605 pins-cmd-dat { 606 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 607 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 608 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 609 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 610 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 611 input-enable; 612 drive-strength = <8>; 613 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 614 }; 615 616 pins-clk { 617 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 618 drive-strength = <8>; 619 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 620 }; 621 }; 622 623 nor_pins_default: nor-default-pins { 624 pins-ck-io { 625 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 626 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 627 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 628 drive-strength = <6>; 629 bias-pull-down; 630 }; 631 632 pins-cs { 633 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 634 drive-strength = <6>; 635 bias-pull-up; 636 }; 637 }; 638 639 pio_default: pio-default-pins { 640 pins-wifi-enable { 641 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 642 output-high; 643 drive-strength = <14>; 644 }; 645 646 pins-low-power-pd { 647 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 648 <PINMUX_GPIO26__FUNC_GPIO26>, 649 <PINMUX_GPIO46__FUNC_GPIO46>, 650 <PINMUX_GPIO47__FUNC_GPIO47>, 651 <PINMUX_GPIO48__FUNC_GPIO48>, 652 <PINMUX_GPIO65__FUNC_GPIO65>, 653 <PINMUX_GPIO66__FUNC_GPIO66>, 654 <PINMUX_GPIO67__FUNC_GPIO67>, 655 <PINMUX_GPIO68__FUNC_GPIO68>, 656 <PINMUX_GPIO128__FUNC_GPIO128>, 657 <PINMUX_GPIO129__FUNC_GPIO129>; 658 input-enable; 659 bias-pull-down; 660 }; 661 662 pins-low-power-pupd { 663 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 664 <PINMUX_GPIO78__FUNC_GPIO78>, 665 <PINMUX_GPIO79__FUNC_GPIO79>, 666 <PINMUX_GPIO80__FUNC_GPIO80>, 667 <PINMUX_GPIO83__FUNC_GPIO83>, 668 <PINMUX_GPIO85__FUNC_GPIO85>, 669 <PINMUX_GPIO90__FUNC_GPIO90>, 670 <PINMUX_GPIO91__FUNC_GPIO91>, 671 <PINMUX_GPIO93__FUNC_GPIO93>, 672 <PINMUX_GPIO94__FUNC_GPIO94>, 673 <PINMUX_GPIO95__FUNC_GPIO95>, 674 <PINMUX_GPIO96__FUNC_GPIO96>, 675 <PINMUX_GPIO104__FUNC_GPIO104>, 676 <PINMUX_GPIO105__FUNC_GPIO105>, 677 <PINMUX_GPIO107__FUNC_GPIO107>; 678 input-enable; 679 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 680 }; 681 }; 682 683 scp_pins: scp-default-pins { 684 pins-vreq { 685 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 686 bias-disable; 687 input-enable; 688 }; 689 }; 690 691 spi0_pins: spi0-default-pins { 692 pins-cs-mosi-clk { 693 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 694 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 695 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 696 bias-disable; 697 }; 698 699 pins-miso { 700 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 701 bias-pull-down; 702 }; 703 }; 704 705 subpmic_default: subpmic-default-pins { 706 subpmic_pin_irq: pins-subpmic-int-n { 707 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 708 input-enable; 709 bias-pull-up; 710 }; 711 }; 712 713 touchscreen_pins: touchscreen-default-pins { 714 pins-int-n { 715 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 716 input-enable; 717 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 718 }; 719 pins-rst { 720 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 721 output-high; 722 }; 723 pins-report-sw { 724 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 725 output-low; 726 }; 727 }; 728}; 729 730&pmic { 731 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 732}; 733 734&scp { 735 status = "okay"; 736 737 firmware-name = "mediatek/mt8195/scp.img"; 738 memory-region = <&scp_mem>; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&scp_pins>; 741 742 cros-ec-rpmsg { 743 compatible = "google,cros-ec-rpmsg"; 744 mediatek,rpmsg-name = "cros-ec-rpmsg"; 745 }; 746}; 747 748&spi0 { 749 status = "okay"; 750 751 pinctrl-names = "default"; 752 pinctrl-0 = <&spi0_pins>; 753 mediatek,pad-select = <0>; 754 755 cros_ec: ec@0 { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 759 compatible = "google,cros-ec-spi"; 760 reg = <0>; 761 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 762 pinctrl-names = "default"; 763 pinctrl-0 = <&cros_ec_int>; 764 spi-max-frequency = <3000000>; 765 766 keyboard-backlight { 767 compatible = "google,cros-kbd-led-backlight"; 768 }; 769 770 i2c_tunnel: i2c-tunnel { 771 compatible = "google,cros-ec-i2c-tunnel"; 772 google,remote-bus = <0>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 }; 776 777 mt_pmic_vmc_ldo_reg: regulator@0 { 778 compatible = "google,cros-ec-regulator"; 779 reg = <0>; 780 regulator-name = "mt_pmic_vmc_ldo"; 781 regulator-min-microvolt = <1200000>; 782 regulator-max-microvolt = <3600000>; 783 }; 784 785 mt_pmic_vmch_ldo_reg: regulator@1 { 786 compatible = "google,cros-ec-regulator"; 787 reg = <1>; 788 regulator-name = "mt_pmic_vmch_ldo"; 789 regulator-min-microvolt = <2700000>; 790 regulator-max-microvolt = <3600000>; 791 }; 792 793 typec { 794 compatible = "google,cros-ec-typec"; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 798 usb_c0: connector@0 { 799 compatible = "usb-c-connector"; 800 reg = <0>; 801 power-role = "dual"; 802 data-role = "host"; 803 try-power-role = "source"; 804 }; 805 806 usb_c1: connector@1 { 807 compatible = "usb-c-connector"; 808 reg = <1>; 809 power-role = "dual"; 810 data-role = "host"; 811 try-power-role = "source"; 812 }; 813 }; 814 }; 815}; 816 817&u3phy0 { 818 status = "okay"; 819}; 820 821&u3phy1 { 822 status = "okay"; 823}; 824 825&u3phy2 { 826 status = "okay"; 827}; 828 829&u3phy3 { 830 status = "okay"; 831}; 832 833&uart0 { 834 status = "okay"; 835}; 836 837&xhci0 { 838 status = "okay"; 839 840 vusb33-supply = <&mt6359_vusb_ldo_reg>; 841 vbus-supply = <&usb_vbus>; 842}; 843 844&xhci1 { 845 status = "okay"; 846 847 vusb33-supply = <&mt6359_vusb_ldo_reg>; 848 vbus-supply = <&usb_vbus>; 849}; 850 851&xhci2 { 852 status = "okay"; 853 854 vusb33-supply = <&mt6359_vusb_ldo_reg>; 855 vbus-supply = <&usb_vbus>; 856}; 857 858&xhci3 { 859 status = "okay"; 860 861 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 862 usb2-lpm-disable; 863 vusb33-supply = <&mt6359_vusb_ldo_reg>; 864 vbus-supply = <&usb_vbus>; 865}; 866 867#include <arm/cros-ec-keyboard.dtsi> 868#include <arm/cros-ec-sbs.dtsi> 869 870&keyboard_controller { 871 function-row-physmap = < 872 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 873 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 874 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 875 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 876 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 877 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 878 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 879 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 880 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 881 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 882 >; 883 884 linux,keymap = < 885 MATRIX_KEY(0x00, 0x02, KEY_BACK) 886 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 887 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 888 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 889 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 890 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 891 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 892 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 893 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 894 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 895 896 CROS_STD_MAIN_KEYMAP 897 >; 898}; 899