148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 9b4b75bacSAllen-KH Cheng#include <dt-bindings/gce/mt8192-gce.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1148489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 124a65b0f1SAllen-KH Cheng#include <dt-bindings/memory/mt8192-larb-port.h> 1348489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h> 15994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 167d355378SAllen-KH Cheng#include <dt-bindings/reset/mt8192-resets.h> 1748489980SSeiya Wang 1848489980SSeiya Wang/ { 1948489980SSeiya Wang compatible = "mediatek,mt8192"; 2048489980SSeiya Wang interrupt-parent = <&gic>; 2148489980SSeiya Wang #address-cells = <2>; 2248489980SSeiya Wang #size-cells = <2>; 2348489980SSeiya Wang 24b4b75bacSAllen-KH Cheng aliases { 25b4b75bacSAllen-KH Cheng ovl0 = &ovl0; 26b4b75bacSAllen-KH Cheng ovl-2l0 = &ovl_2l0; 27b4b75bacSAllen-KH Cheng ovl-2l2 = &ovl_2l2; 28b4b75bacSAllen-KH Cheng rdma0 = &rdma0; 29b4b75bacSAllen-KH Cheng rdma4 = &rdma4; 30b4b75bacSAllen-KH Cheng }; 31b4b75bacSAllen-KH Cheng 32*f19f68e5SChen-Yu Tsai clk13m: fixed-factor-clock-13m { 33*f19f68e5SChen-Yu Tsai compatible = "fixed-factor-clock"; 34*f19f68e5SChen-Yu Tsai #clock-cells = <0>; 35*f19f68e5SChen-Yu Tsai clocks = <&clk26m>; 36*f19f68e5SChen-Yu Tsai clock-div = <2>; 37*f19f68e5SChen-Yu Tsai clock-mult = <1>; 38*f19f68e5SChen-Yu Tsai clock-output-names = "clk13m"; 39*f19f68e5SChen-Yu Tsai }; 40*f19f68e5SChen-Yu Tsai 4148489980SSeiya Wang clk26m: oscillator0 { 4248489980SSeiya Wang compatible = "fixed-clock"; 4348489980SSeiya Wang #clock-cells = <0>; 4448489980SSeiya Wang clock-frequency = <26000000>; 4548489980SSeiya Wang clock-output-names = "clk26m"; 4648489980SSeiya Wang }; 4748489980SSeiya Wang 4848489980SSeiya Wang clk32k: oscillator1 { 4948489980SSeiya Wang compatible = "fixed-clock"; 5048489980SSeiya Wang #clock-cells = <0>; 5148489980SSeiya Wang clock-frequency = <32768>; 5248489980SSeiya Wang clock-output-names = "clk32k"; 5348489980SSeiya Wang }; 5448489980SSeiya Wang 5548489980SSeiya Wang cpus { 5648489980SSeiya Wang #address-cells = <1>; 5748489980SSeiya Wang #size-cells = <0>; 5848489980SSeiya Wang 5948489980SSeiya Wang cpu0: cpu@0 { 6048489980SSeiya Wang device_type = "cpu"; 6148489980SSeiya Wang compatible = "arm,cortex-a55"; 6248489980SSeiya Wang reg = <0x000>; 6348489980SSeiya Wang enable-method = "psci"; 6448489980SSeiya Wang clock-frequency = <1701000000>; 65399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 6648489980SSeiya Wang next-level-cache = <&l2_0>; 6748489980SSeiya Wang capacity-dmips-mhz = <530>; 6848489980SSeiya Wang }; 6948489980SSeiya Wang 7048489980SSeiya Wang cpu1: cpu@100 { 7148489980SSeiya Wang device_type = "cpu"; 7248489980SSeiya Wang compatible = "arm,cortex-a55"; 7348489980SSeiya Wang reg = <0x100>; 7448489980SSeiya Wang enable-method = "psci"; 7548489980SSeiya Wang clock-frequency = <1701000000>; 76399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 7748489980SSeiya Wang next-level-cache = <&l2_0>; 7848489980SSeiya Wang capacity-dmips-mhz = <530>; 7948489980SSeiya Wang }; 8048489980SSeiya Wang 8148489980SSeiya Wang cpu2: cpu@200 { 8248489980SSeiya Wang device_type = "cpu"; 8348489980SSeiya Wang compatible = "arm,cortex-a55"; 8448489980SSeiya Wang reg = <0x200>; 8548489980SSeiya Wang enable-method = "psci"; 8648489980SSeiya Wang clock-frequency = <1701000000>; 87399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 8848489980SSeiya Wang next-level-cache = <&l2_0>; 8948489980SSeiya Wang capacity-dmips-mhz = <530>; 9048489980SSeiya Wang }; 9148489980SSeiya Wang 9248489980SSeiya Wang cpu3: cpu@300 { 9348489980SSeiya Wang device_type = "cpu"; 9448489980SSeiya Wang compatible = "arm,cortex-a55"; 9548489980SSeiya Wang reg = <0x300>; 9648489980SSeiya Wang enable-method = "psci"; 9748489980SSeiya Wang clock-frequency = <1701000000>; 98399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 9948489980SSeiya Wang next-level-cache = <&l2_0>; 10048489980SSeiya Wang capacity-dmips-mhz = <530>; 10148489980SSeiya Wang }; 10248489980SSeiya Wang 10348489980SSeiya Wang cpu4: cpu@400 { 10448489980SSeiya Wang device_type = "cpu"; 10548489980SSeiya Wang compatible = "arm,cortex-a76"; 10648489980SSeiya Wang reg = <0x400>; 10748489980SSeiya Wang enable-method = "psci"; 10848489980SSeiya Wang clock-frequency = <2171000000>; 109399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 11048489980SSeiya Wang next-level-cache = <&l2_1>; 11148489980SSeiya Wang capacity-dmips-mhz = <1024>; 11248489980SSeiya Wang }; 11348489980SSeiya Wang 11448489980SSeiya Wang cpu5: cpu@500 { 11548489980SSeiya Wang device_type = "cpu"; 11648489980SSeiya Wang compatible = "arm,cortex-a76"; 11748489980SSeiya Wang reg = <0x500>; 11848489980SSeiya Wang enable-method = "psci"; 11948489980SSeiya Wang clock-frequency = <2171000000>; 120399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 12148489980SSeiya Wang next-level-cache = <&l2_1>; 12248489980SSeiya Wang capacity-dmips-mhz = <1024>; 12348489980SSeiya Wang }; 12448489980SSeiya Wang 12548489980SSeiya Wang cpu6: cpu@600 { 12648489980SSeiya Wang device_type = "cpu"; 12748489980SSeiya Wang compatible = "arm,cortex-a76"; 12848489980SSeiya Wang reg = <0x600>; 12948489980SSeiya Wang enable-method = "psci"; 13048489980SSeiya Wang clock-frequency = <2171000000>; 131399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 13248489980SSeiya Wang next-level-cache = <&l2_1>; 13348489980SSeiya Wang capacity-dmips-mhz = <1024>; 13448489980SSeiya Wang }; 13548489980SSeiya Wang 13648489980SSeiya Wang cpu7: cpu@700 { 13748489980SSeiya Wang device_type = "cpu"; 13848489980SSeiya Wang compatible = "arm,cortex-a76"; 13948489980SSeiya Wang reg = <0x700>; 14048489980SSeiya Wang enable-method = "psci"; 14148489980SSeiya Wang clock-frequency = <2171000000>; 142399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 14348489980SSeiya Wang next-level-cache = <&l2_1>; 14448489980SSeiya Wang capacity-dmips-mhz = <1024>; 14548489980SSeiya Wang }; 14648489980SSeiya Wang 14748489980SSeiya Wang cpu-map { 14848489980SSeiya Wang cluster0 { 14948489980SSeiya Wang core0 { 15048489980SSeiya Wang cpu = <&cpu0>; 15148489980SSeiya Wang }; 15248489980SSeiya Wang core1 { 15348489980SSeiya Wang cpu = <&cpu1>; 15448489980SSeiya Wang }; 15548489980SSeiya Wang core2 { 15648489980SSeiya Wang cpu = <&cpu2>; 15748489980SSeiya Wang }; 15848489980SSeiya Wang core3 { 15948489980SSeiya Wang cpu = <&cpu3>; 16048489980SSeiya Wang }; 16148489980SSeiya Wang }; 16248489980SSeiya Wang 16348489980SSeiya Wang cluster1 { 16448489980SSeiya Wang core0 { 16548489980SSeiya Wang cpu = <&cpu4>; 16648489980SSeiya Wang }; 16748489980SSeiya Wang core1 { 16848489980SSeiya Wang cpu = <&cpu5>; 16948489980SSeiya Wang }; 17048489980SSeiya Wang core2 { 17148489980SSeiya Wang cpu = <&cpu6>; 17248489980SSeiya Wang }; 17348489980SSeiya Wang core3 { 17448489980SSeiya Wang cpu = <&cpu7>; 17548489980SSeiya Wang }; 17648489980SSeiya Wang }; 17748489980SSeiya Wang }; 17848489980SSeiya Wang 17948489980SSeiya Wang l2_0: l2-cache0 { 18048489980SSeiya Wang compatible = "cache"; 181ce459b1dSPierre Gondois cache-level = <2>; 18248489980SSeiya Wang next-level-cache = <&l3_0>; 18348489980SSeiya Wang }; 18448489980SSeiya Wang 18548489980SSeiya Wang l2_1: l2-cache1 { 18648489980SSeiya Wang compatible = "cache"; 187ce459b1dSPierre Gondois cache-level = <2>; 18848489980SSeiya Wang next-level-cache = <&l3_0>; 18948489980SSeiya Wang }; 19048489980SSeiya Wang 19148489980SSeiya Wang l3_0: l3-cache { 19248489980SSeiya Wang compatible = "cache"; 193ce459b1dSPierre Gondois cache-level = <3>; 19448489980SSeiya Wang }; 1959260918dSJames Liao 1969260918dSJames Liao idle-states { 1972e599740SNícolas F. R. A. Prado entry-method = "psci"; 198399e23adSNícolas F. R. A. Prado cpu_sleep_l: cpu-sleep-l { 1999260918dSJames Liao compatible = "arm,idle-state"; 2009260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 2019260918dSJames Liao local-timer-stop; 2029260918dSJames Liao entry-latency-us = <55>; 2039260918dSJames Liao exit-latency-us = <140>; 2049260918dSJames Liao min-residency-us = <780>; 2059260918dSJames Liao }; 206399e23adSNícolas F. R. A. Prado cpu_sleep_b: cpu-sleep-b { 2079260918dSJames Liao compatible = "arm,idle-state"; 2089260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 2099260918dSJames Liao local-timer-stop; 2109260918dSJames Liao entry-latency-us = <35>; 2119260918dSJames Liao exit-latency-us = <145>; 2129260918dSJames Liao min-residency-us = <720>; 2139260918dSJames Liao }; 214399e23adSNícolas F. R. A. Prado cluster_sleep_l: cluster-sleep-l { 2159260918dSJames Liao compatible = "arm,idle-state"; 2169260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2179260918dSJames Liao local-timer-stop; 2189260918dSJames Liao entry-latency-us = <60>; 2199260918dSJames Liao exit-latency-us = <155>; 2209260918dSJames Liao min-residency-us = <860>; 2219260918dSJames Liao }; 222399e23adSNícolas F. R. A. Prado cluster_sleep_b: cluster-sleep-b { 2239260918dSJames Liao compatible = "arm,idle-state"; 2249260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2259260918dSJames Liao local-timer-stop; 2269260918dSJames Liao entry-latency-us = <40>; 2279260918dSJames Liao exit-latency-us = <155>; 2289260918dSJames Liao min-residency-us = <780>; 2299260918dSJames Liao }; 2309260918dSJames Liao }; 23148489980SSeiya Wang }; 23248489980SSeiya Wang 23348489980SSeiya Wang pmu-a55 { 23448489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 23548489980SSeiya Wang interrupt-parent = <&gic>; 23648489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 23748489980SSeiya Wang }; 23848489980SSeiya Wang 23948489980SSeiya Wang pmu-a76 { 24048489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 24148489980SSeiya Wang interrupt-parent = <&gic>; 24248489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 24348489980SSeiya Wang }; 24448489980SSeiya Wang 24548489980SSeiya Wang psci { 24648489980SSeiya Wang compatible = "arm,psci-1.0"; 24748489980SSeiya Wang method = "smc"; 24848489980SSeiya Wang }; 24948489980SSeiya Wang 25048489980SSeiya Wang timer: timer { 25148489980SSeiya Wang compatible = "arm,armv8-timer"; 25248489980SSeiya Wang interrupt-parent = <&gic>; 25348489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 25448489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 25548489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 25648489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 25748489980SSeiya Wang clock-frequency = <13000000>; 25848489980SSeiya Wang }; 25948489980SSeiya Wang 26048489980SSeiya Wang soc { 26148489980SSeiya Wang #address-cells = <2>; 26248489980SSeiya Wang #size-cells = <2>; 26348489980SSeiya Wang compatible = "simple-bus"; 26448489980SSeiya Wang ranges; 26548489980SSeiya Wang 26648489980SSeiya Wang gic: interrupt-controller@c000000 { 26748489980SSeiya Wang compatible = "arm,gic-v3"; 26848489980SSeiya Wang #interrupt-cells = <4>; 26948489980SSeiya Wang #redistributor-regions = <1>; 27048489980SSeiya Wang interrupt-parent = <&gic>; 27148489980SSeiya Wang interrupt-controller; 27248489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 27348489980SSeiya Wang <0 0x0c040000 0 0x200000>; 27448489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 27548489980SSeiya Wang 27648489980SSeiya Wang ppi-partitions { 27748489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 27848489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 27948489980SSeiya Wang }; 28048489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 28148489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 28248489980SSeiya Wang }; 28348489980SSeiya Wang }; 28448489980SSeiya Wang }; 28548489980SSeiya Wang 2865d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 2875d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 2885d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 2895d2b897bSChun-Jie Chen #clock-cells = <1>; 2905d2b897bSChun-Jie Chen }; 2915d2b897bSChun-Jie Chen 2925d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 2935d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 2945d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 2955d2b897bSChun-Jie Chen #clock-cells = <1>; 296a30cc07fSRex-BC Chen #reset-cells = <1>; 2975d2b897bSChun-Jie Chen }; 2985d2b897bSChun-Jie Chen 2995d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 3005d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 3015d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 3025d2b897bSChun-Jie Chen #clock-cells = <1>; 3035d2b897bSChun-Jie Chen }; 3045d2b897bSChun-Jie Chen 30548489980SSeiya Wang pio: pinctrl@10005000 { 30648489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 30748489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 30848489980SSeiya Wang <0 0x11c20000 0 0x1000>, 30948489980SSeiya Wang <0 0x11d10000 0 0x1000>, 31048489980SSeiya Wang <0 0x11d30000 0 0x1000>, 31148489980SSeiya Wang <0 0x11d40000 0 0x1000>, 31248489980SSeiya Wang <0 0x11e20000 0 0x1000>, 31348489980SSeiya Wang <0 0x11e70000 0 0x1000>, 31448489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 31548489980SSeiya Wang <0 0x11f20000 0 0x1000>, 31648489980SSeiya Wang <0 0x11f30000 0 0x1000>, 31748489980SSeiya Wang <0 0x1000b000 0 0x1000>; 31848489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 31948489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 32048489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 32148489980SSeiya Wang "iocfg_tl", "eint"; 32248489980SSeiya Wang gpio-controller; 32348489980SSeiya Wang #gpio-cells = <2>; 32448489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 32548489980SSeiya Wang interrupt-controller; 32648489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 32748489980SSeiya Wang #interrupt-cells = <2>; 32848489980SSeiya Wang }; 32948489980SSeiya Wang 330994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 331d3dfd468STinghan Shen compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 332994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 333994a71a3SChun-Jie Chen 334994a71a3SChun-Jie Chen /* System Power Manager */ 335994a71a3SChun-Jie Chen spm: power-controller { 336994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 337994a71a3SChun-Jie Chen #address-cells = <1>; 338994a71a3SChun-Jie Chen #size-cells = <0>; 339994a71a3SChun-Jie Chen #power-domain-cells = <1>; 340994a71a3SChun-Jie Chen 341994a71a3SChun-Jie Chen /* power domain of the SoC */ 342994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 343994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 344994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 345994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 346994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 347994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 348994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 349994a71a3SChun-Jie Chen #power-domain-cells = <0>; 350994a71a3SChun-Jie Chen }; 351994a71a3SChun-Jie Chen 352994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 353994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 354994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 355994a71a3SChun-Jie Chen clock-names = "conn"; 356994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 357994a71a3SChun-Jie Chen #power-domain-cells = <0>; 358994a71a3SChun-Jie Chen }; 359994a71a3SChun-Jie Chen 360994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG0 { 361994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 362994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 363994a71a3SChun-Jie Chen clock-names = "mfg"; 364994a71a3SChun-Jie Chen #address-cells = <1>; 365994a71a3SChun-Jie Chen #size-cells = <0>; 366994a71a3SChun-Jie Chen #power-domain-cells = <1>; 367994a71a3SChun-Jie Chen 368994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG1 { 369994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 370994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 371994a71a3SChun-Jie Chen #address-cells = <1>; 372994a71a3SChun-Jie Chen #size-cells = <0>; 373994a71a3SChun-Jie Chen #power-domain-cells = <1>; 374994a71a3SChun-Jie Chen 375994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 376994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 377994a71a3SChun-Jie Chen #power-domain-cells = <0>; 378994a71a3SChun-Jie Chen }; 379994a71a3SChun-Jie Chen 380994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 381994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 382994a71a3SChun-Jie Chen #power-domain-cells = <0>; 383994a71a3SChun-Jie Chen }; 384994a71a3SChun-Jie Chen 385994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 386994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 387994a71a3SChun-Jie Chen #power-domain-cells = <0>; 388994a71a3SChun-Jie Chen }; 389994a71a3SChun-Jie Chen 390994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 391994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 392994a71a3SChun-Jie Chen #power-domain-cells = <0>; 393994a71a3SChun-Jie Chen }; 394994a71a3SChun-Jie Chen 395994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 396994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 397994a71a3SChun-Jie Chen #power-domain-cells = <0>; 398994a71a3SChun-Jie Chen }; 399994a71a3SChun-Jie Chen }; 400994a71a3SChun-Jie Chen }; 401994a71a3SChun-Jie Chen 402994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 403994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 404994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 405994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 406994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 407994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 408994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 409994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 410994a71a3SChun-Jie Chen "disp-3"; 411994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 412994a71a3SChun-Jie Chen #address-cells = <1>; 413994a71a3SChun-Jie Chen #size-cells = <0>; 414994a71a3SChun-Jie Chen #power-domain-cells = <1>; 415994a71a3SChun-Jie Chen 416994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 417994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 418994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 419994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 420994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 421994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 422994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 423994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 424994a71a3SChun-Jie Chen "ipe-3"; 425994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 426994a71a3SChun-Jie Chen #power-domain-cells = <0>; 427994a71a3SChun-Jie Chen }; 428994a71a3SChun-Jie Chen 429994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 430994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 431994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 432994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 433994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 434994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 435994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 436994a71a3SChun-Jie Chen #power-domain-cells = <0>; 437994a71a3SChun-Jie Chen }; 438994a71a3SChun-Jie Chen 439994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 440994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 441994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 442994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 443994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 444994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 445994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 446994a71a3SChun-Jie Chen #power-domain-cells = <0>; 447994a71a3SChun-Jie Chen }; 448994a71a3SChun-Jie Chen 449994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 450994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 451994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 452994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 453994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 454994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 455994a71a3SChun-Jie Chen #power-domain-cells = <0>; 456994a71a3SChun-Jie Chen }; 457994a71a3SChun-Jie Chen 458994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 459994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 460994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 461994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 462994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 463994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 464994a71a3SChun-Jie Chen #power-domain-cells = <0>; 465994a71a3SChun-Jie Chen }; 466994a71a3SChun-Jie Chen 467994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 468994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 469994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 470994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 471994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 472994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 473994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 474994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 475994a71a3SChun-Jie Chen #address-cells = <1>; 476994a71a3SChun-Jie Chen #size-cells = <0>; 477994a71a3SChun-Jie Chen #power-domain-cells = <1>; 478994a71a3SChun-Jie Chen 479994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 480994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 481994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 482994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 483994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 484994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 485994a71a3SChun-Jie Chen "vdec2-2"; 486994a71a3SChun-Jie Chen #power-domain-cells = <0>; 487994a71a3SChun-Jie Chen }; 488994a71a3SChun-Jie Chen }; 489994a71a3SChun-Jie Chen 490994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 491994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 492994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 493994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 494994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 495994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 496994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 497994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 498994a71a3SChun-Jie Chen "cam-3"; 499994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 500994a71a3SChun-Jie Chen #address-cells = <1>; 501994a71a3SChun-Jie Chen #size-cells = <0>; 502994a71a3SChun-Jie Chen #power-domain-cells = <1>; 503994a71a3SChun-Jie Chen 504994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 505994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 506994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 507994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 508994a71a3SChun-Jie Chen #power-domain-cells = <0>; 509994a71a3SChun-Jie Chen }; 510994a71a3SChun-Jie Chen 511994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 512994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 513994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 514994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 515994a71a3SChun-Jie Chen #power-domain-cells = <0>; 516994a71a3SChun-Jie Chen }; 517994a71a3SChun-Jie Chen 518994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 519994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 520994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 521994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 522994a71a3SChun-Jie Chen #power-domain-cells = <0>; 523994a71a3SChun-Jie Chen }; 524994a71a3SChun-Jie Chen }; 525994a71a3SChun-Jie Chen }; 526994a71a3SChun-Jie Chen }; 527994a71a3SChun-Jie Chen }; 528994a71a3SChun-Jie Chen 529d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 530d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 531d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 532d1986fbdSAllen-KH Cheng #reset-cells = <1>; 533d1986fbdSAllen-KH Cheng }; 534d1986fbdSAllen-KH Cheng 5355d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 5365d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 5375d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 5385d2b897bSChun-Jie Chen #clock-cells = <1>; 5395d2b897bSChun-Jie Chen }; 5405d2b897bSChun-Jie Chen 54148489980SSeiya Wang systimer: timer@10017000 { 54248489980SSeiya Wang compatible = "mediatek,mt8192-timer", 54348489980SSeiya Wang "mediatek,mt6765-timer"; 54448489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 54548489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 546*f19f68e5SChen-Yu Tsai clocks = <&clk13m>; 54748489980SSeiya Wang }; 54848489980SSeiya Wang 549261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 550261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 551261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 552261691b4SAllen-KH Cheng reg-names = "pwrap"; 553261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 554261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 555261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 556261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 557261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 558261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 559261691b4SAllen-KH Cheng }; 560261691b4SAllen-KH Cheng 561a8bbcf70SAllen-KH Cheng spmi: spmi@10027000 { 562a8bbcf70SAllen-KH Cheng compatible = "mediatek,mt6873-spmi"; 563a8bbcf70SAllen-KH Cheng reg = <0 0x10027000 0 0x000e00>, 564a8bbcf70SAllen-KH Cheng <0 0x10029000 0 0x000100>; 565a8bbcf70SAllen-KH Cheng reg-names = "pmif", "spmimst"; 566a8bbcf70SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 567a8bbcf70SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>, 568a8bbcf70SAllen-KH Cheng <&topckgen CLK_TOP_SPMI_MST_SEL>; 569a8bbcf70SAllen-KH Cheng clock-names = "pmif_sys_ck", 570a8bbcf70SAllen-KH Cheng "pmif_tmr_ck", 571a8bbcf70SAllen-KH Cheng "spmimst_clk_mux"; 572a8bbcf70SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 573a8bbcf70SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 574a8bbcf70SAllen-KH Cheng }; 575a8bbcf70SAllen-KH Cheng 576b4b75bacSAllen-KH Cheng gce: mailbox@10228000 { 577b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-gce"; 578b4b75bacSAllen-KH Cheng reg = <0 0x10228000 0 0x4000>; 579b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 580b4b75bacSAllen-KH Cheng #mbox-cells = <2>; 581b4b75bacSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_GCE>; 582b4b75bacSAllen-KH Cheng clock-names = "gce"; 583b4b75bacSAllen-KH Cheng }; 584b4b75bacSAllen-KH Cheng 5855d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 5865d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 5875d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 5885d2b897bSChun-Jie Chen #clock-cells = <1>; 5895d2b897bSChun-Jie Chen }; 5905d2b897bSChun-Jie Chen 59148489980SSeiya Wang uart0: serial@11002000 { 59248489980SSeiya Wang compatible = "mediatek,mt8192-uart", 59348489980SSeiya Wang "mediatek,mt6577-uart"; 59448489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 59548489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 59673ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 59748489980SSeiya Wang clock-names = "baud", "bus"; 59848489980SSeiya Wang status = "disabled"; 59948489980SSeiya Wang }; 60048489980SSeiya Wang 60148489980SSeiya Wang uart1: serial@11003000 { 60248489980SSeiya Wang compatible = "mediatek,mt8192-uart", 60348489980SSeiya Wang "mediatek,mt6577-uart"; 60448489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 60548489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 60673ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 60748489980SSeiya Wang clock-names = "baud", "bus"; 60848489980SSeiya Wang status = "disabled"; 60948489980SSeiya Wang }; 61048489980SSeiya Wang 6115d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 6125d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 6135d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 6145d2b897bSChun-Jie Chen #clock-cells = <1>; 6155d2b897bSChun-Jie Chen }; 6165d2b897bSChun-Jie Chen 61748489980SSeiya Wang spi0: spi@1100a000 { 61848489980SSeiya Wang compatible = "mediatek,mt8192-spi", 61948489980SSeiya Wang "mediatek,mt6765-spi"; 62048489980SSeiya Wang #address-cells = <1>; 62148489980SSeiya Wang #size-cells = <0>; 62248489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 62348489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 6247f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6257f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6267f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 62748489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 62848489980SSeiya Wang status = "disabled"; 62948489980SSeiya Wang }; 63048489980SSeiya Wang 63118222e05SAllen-KH Cheng pwm0: pwm@1100e000 { 63218222e05SAllen-KH Cheng compatible = "mediatek,mt8183-disp-pwm"; 63318222e05SAllen-KH Cheng reg = <0 0x1100e000 0 0x1000>; 63418222e05SAllen-KH Cheng interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 63518222e05SAllen-KH Cheng #pwm-cells = <2>; 63618222e05SAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 63718222e05SAllen-KH Cheng <&infracfg CLK_INFRA_DISP_PWM>; 63818222e05SAllen-KH Cheng clock-names = "main", "mm"; 63918222e05SAllen-KH Cheng status = "disabled"; 64018222e05SAllen-KH Cheng }; 64118222e05SAllen-KH Cheng 64248489980SSeiya Wang spi1: spi@11010000 { 64348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 64448489980SSeiya Wang "mediatek,mt6765-spi"; 64548489980SSeiya Wang #address-cells = <1>; 64648489980SSeiya Wang #size-cells = <0>; 64748489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 64848489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 6497f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6507f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6517f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 65248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 65348489980SSeiya Wang status = "disabled"; 65448489980SSeiya Wang }; 65548489980SSeiya Wang 65648489980SSeiya Wang spi2: spi@11012000 { 65748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 65848489980SSeiya Wang "mediatek,mt6765-spi"; 65948489980SSeiya Wang #address-cells = <1>; 66048489980SSeiya Wang #size-cells = <0>; 66148489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 66248489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 6637f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6647f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6657f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 66648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 66748489980SSeiya Wang status = "disabled"; 66848489980SSeiya Wang }; 66948489980SSeiya Wang 67048489980SSeiya Wang spi3: spi@11013000 { 67148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 67248489980SSeiya Wang "mediatek,mt6765-spi"; 67348489980SSeiya Wang #address-cells = <1>; 67448489980SSeiya Wang #size-cells = <0>; 67548489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 67648489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 6777f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6787f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6797f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 68048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 68148489980SSeiya Wang status = "disabled"; 68248489980SSeiya Wang }; 68348489980SSeiya Wang 68448489980SSeiya Wang spi4: spi@11018000 { 68548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 68648489980SSeiya Wang "mediatek,mt6765-spi"; 68748489980SSeiya Wang #address-cells = <1>; 68848489980SSeiya Wang #size-cells = <0>; 68948489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 69048489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 6917f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6927f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6937f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 69448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 69548489980SSeiya Wang status = "disabled"; 69648489980SSeiya Wang }; 69748489980SSeiya Wang 69848489980SSeiya Wang spi5: spi@11019000 { 69948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 70048489980SSeiya Wang "mediatek,mt6765-spi"; 70148489980SSeiya Wang #address-cells = <1>; 70248489980SSeiya Wang #size-cells = <0>; 70348489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 70448489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 7057f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7067f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7077f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 70848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 70948489980SSeiya Wang status = "disabled"; 71048489980SSeiya Wang }; 71148489980SSeiya Wang 71248489980SSeiya Wang spi6: spi@1101d000 { 71348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 71448489980SSeiya Wang "mediatek,mt6765-spi"; 71548489980SSeiya Wang #address-cells = <1>; 71648489980SSeiya Wang #size-cells = <0>; 71748489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 71848489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 7197f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7207f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7217f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 72248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 72348489980SSeiya Wang status = "disabled"; 72448489980SSeiya Wang }; 72548489980SSeiya Wang 72648489980SSeiya Wang spi7: spi@1101e000 { 72748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 72848489980SSeiya Wang "mediatek,mt6765-spi"; 72948489980SSeiya Wang #address-cells = <1>; 73048489980SSeiya Wang #size-cells = <0>; 73148489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 73248489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 7337f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7347f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7357f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 73648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 73748489980SSeiya Wang status = "disabled"; 73848489980SSeiya Wang }; 73948489980SSeiya Wang 740c63556ecSAllen-KH Cheng scp: scp@10500000 { 741c63556ecSAllen-KH Cheng compatible = "mediatek,mt8192-scp"; 742c63556ecSAllen-KH Cheng reg = <0 0x10500000 0 0x100000>, 743c7510476SNícolas F. R. A. Prado <0 0x10720000 0 0xe0000>, 744c7510476SNícolas F. R. A. Prado <0 0x10700000 0 0x8000>; 745c7510476SNícolas F. R. A. Prado reg-names = "sram", "cfg", "l1tcm"; 746c63556ecSAllen-KH Cheng interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 747c63556ecSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SCPSYS>; 748c63556ecSAllen-KH Cheng clock-names = "main"; 749c63556ecSAllen-KH Cheng status = "disabled"; 750c63556ecSAllen-KH Cheng }; 751c63556ecSAllen-KH Cheng 752e5aac225SAllen-KH Cheng xhci: usb@11200000 { 753e5aac225SAllen-KH Cheng compatible = "mediatek,mt8192-xhci", 754e5aac225SAllen-KH Cheng "mediatek,mtk-xhci"; 755e5aac225SAllen-KH Cheng reg = <0 0x11200000 0 0x1000>, 756e5aac225SAllen-KH Cheng <0 0x11203e00 0 0x0100>; 757e5aac225SAllen-KH Cheng reg-names = "mac", "ippc"; 758e5aac225SAllen-KH Cheng interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 759e5aac225SAllen-KH Cheng interrupt-names = "host"; 760e5aac225SAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>, 761e5aac225SAllen-KH Cheng <&u3port0 PHY_TYPE_USB3>; 762e5aac225SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 763e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 764e5aac225SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 765e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 766e5aac225SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SSUSB>, 7676210fc2eSNícolas F. R. A. Prado <&apmixedsys CLK_APMIXED_USBPLL>, 7686210fc2eSNícolas F. R. A. Prado <&clk26m>, 7696210fc2eSNícolas F. R. A. Prado <&clk26m>, 7706210fc2eSNícolas F. R. A. Prado <&infracfg CLK_INFRA_SSUSB_XHCI>; 7716210fc2eSNícolas F. R. A. Prado clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 7726210fc2eSNícolas F. R. A. Prado "xhci_ck"; 773e5aac225SAllen-KH Cheng wakeup-source; 774e5aac225SAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 102>; 775e5aac225SAllen-KH Cheng status = "disabled"; 776e5aac225SAllen-KH Cheng }; 777e5aac225SAllen-KH Cheng 7781afd9b62SAllen-KH Cheng audsys: syscon@11210000 { 7791afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audsys", "syscon"; 7801afd9b62SAllen-KH Cheng reg = <0 0x11210000 0 0x2000>; 7811afd9b62SAllen-KH Cheng #clock-cells = <1>; 7821afd9b62SAllen-KH Cheng 7831afd9b62SAllen-KH Cheng afe: mt8192-afe-pcm { 7841afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audio"; 7851afd9b62SAllen-KH Cheng interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 7861afd9b62SAllen-KH Cheng resets = <&watchdog 17>; 7871afd9b62SAllen-KH Cheng reset-names = "audiosys"; 7881afd9b62SAllen-KH Cheng mediatek,apmixedsys = <&apmixedsys>; 7891afd9b62SAllen-KH Cheng mediatek,infracfg = <&infracfg>; 7901afd9b62SAllen-KH Cheng mediatek,topckgen = <&topckgen>; 7911afd9b62SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 7921afd9b62SAllen-KH Cheng clocks = <&audsys CLK_AUD_AFE>, 7931afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC>, 7941afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_PREDIS>, 7951afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC>, 7961afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC>, 7971afd9b62SAllen-KH Cheng <&audsys CLK_AUD_22M>, 7981afd9b62SAllen-KH Cheng <&audsys CLK_AUD_24M>, 7991afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL_TUNER>, 8001afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL2_TUNER>, 8011afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TDM>, 8021afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TML>, 8031afd9b62SAllen-KH Cheng <&audsys CLK_AUD_NLE>, 8041afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_HIRES>, 8051afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES>, 8061afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES_TML>, 8071afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 8081afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC>, 8091afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_PREDIS>, 8101afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_TML>, 8111afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_HIRES>, 8121afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO>, 8131afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO_26M_B>, 8141afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_SEL>, 8151afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 8161afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D4_D4>, 8171afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_1_SEL>, 8181afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1>, 8191afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_2_SEL>, 8201afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2>, 8211afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 8221afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1_D4>, 8231afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 8241afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2_D4>, 8251afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 8261afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 8271afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 8281afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 8291afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 8301afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 8311afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 8321afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 8331afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 8341afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 8351afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV0>, 8361afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV1>, 8371afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV2>, 8381afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV3>, 8391afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV4>, 8401afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIVB>, 8411afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV5>, 8421afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV6>, 8431afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV7>, 8441afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV8>, 8451afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV9>, 8461afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_H_SEL>, 8471afd9b62SAllen-KH Cheng <&clk26m>; 8481afd9b62SAllen-KH Cheng clock-names = "aud_afe_clk", 8491afd9b62SAllen-KH Cheng "aud_dac_clk", 8501afd9b62SAllen-KH Cheng "aud_dac_predis_clk", 8511afd9b62SAllen-KH Cheng "aud_adc_clk", 8521afd9b62SAllen-KH Cheng "aud_adda6_adc_clk", 8531afd9b62SAllen-KH Cheng "aud_apll22m_clk", 8541afd9b62SAllen-KH Cheng "aud_apll24m_clk", 8551afd9b62SAllen-KH Cheng "aud_apll1_tuner_clk", 8561afd9b62SAllen-KH Cheng "aud_apll2_tuner_clk", 8571afd9b62SAllen-KH Cheng "aud_tdm_clk", 8581afd9b62SAllen-KH Cheng "aud_tml_clk", 8591afd9b62SAllen-KH Cheng "aud_nle", 8601afd9b62SAllen-KH Cheng "aud_dac_hires_clk", 8611afd9b62SAllen-KH Cheng "aud_adc_hires_clk", 8621afd9b62SAllen-KH Cheng "aud_adc_hires_tml", 8631afd9b62SAllen-KH Cheng "aud_adda6_adc_hires_clk", 8641afd9b62SAllen-KH Cheng "aud_3rd_dac_clk", 8651afd9b62SAllen-KH Cheng "aud_3rd_dac_predis_clk", 8661afd9b62SAllen-KH Cheng "aud_3rd_dac_tml", 8671afd9b62SAllen-KH Cheng "aud_3rd_dac_hires_clk", 8681afd9b62SAllen-KH Cheng "aud_infra_clk", 8691afd9b62SAllen-KH Cheng "aud_infra_26m_clk", 8701afd9b62SAllen-KH Cheng "top_mux_audio", 8711afd9b62SAllen-KH Cheng "top_mux_audio_int", 8721afd9b62SAllen-KH Cheng "top_mainpll_d4_d4", 8731afd9b62SAllen-KH Cheng "top_mux_aud_1", 8741afd9b62SAllen-KH Cheng "top_apll1_ck", 8751afd9b62SAllen-KH Cheng "top_mux_aud_2", 8761afd9b62SAllen-KH Cheng "top_apll2_ck", 8771afd9b62SAllen-KH Cheng "top_mux_aud_eng1", 8781afd9b62SAllen-KH Cheng "top_apll1_d4", 8791afd9b62SAllen-KH Cheng "top_mux_aud_eng2", 8801afd9b62SAllen-KH Cheng "top_apll2_d4", 8811afd9b62SAllen-KH Cheng "top_i2s0_m_sel", 8821afd9b62SAllen-KH Cheng "top_i2s1_m_sel", 8831afd9b62SAllen-KH Cheng "top_i2s2_m_sel", 8841afd9b62SAllen-KH Cheng "top_i2s3_m_sel", 8851afd9b62SAllen-KH Cheng "top_i2s4_m_sel", 8861afd9b62SAllen-KH Cheng "top_i2s5_m_sel", 8871afd9b62SAllen-KH Cheng "top_i2s6_m_sel", 8881afd9b62SAllen-KH Cheng "top_i2s7_m_sel", 8891afd9b62SAllen-KH Cheng "top_i2s8_m_sel", 8901afd9b62SAllen-KH Cheng "top_i2s9_m_sel", 8911afd9b62SAllen-KH Cheng "top_apll12_div0", 8921afd9b62SAllen-KH Cheng "top_apll12_div1", 8931afd9b62SAllen-KH Cheng "top_apll12_div2", 8941afd9b62SAllen-KH Cheng "top_apll12_div3", 8951afd9b62SAllen-KH Cheng "top_apll12_div4", 8961afd9b62SAllen-KH Cheng "top_apll12_divb", 8971afd9b62SAllen-KH Cheng "top_apll12_div5", 8981afd9b62SAllen-KH Cheng "top_apll12_div6", 8991afd9b62SAllen-KH Cheng "top_apll12_div7", 9001afd9b62SAllen-KH Cheng "top_apll12_div8", 9011afd9b62SAllen-KH Cheng "top_apll12_div9", 9021afd9b62SAllen-KH Cheng "top_mux_audio_h", 9031afd9b62SAllen-KH Cheng "top_clk26m_clk"; 9041afd9b62SAllen-KH Cheng }; 9051afd9b62SAllen-KH Cheng }; 9061afd9b62SAllen-KH Cheng 907e530d080SAllen-KH Cheng pcie: pcie@11230000 { 908e530d080SAllen-KH Cheng compatible = "mediatek,mt8192-pcie"; 909e530d080SAllen-KH Cheng device_type = "pci"; 910e530d080SAllen-KH Cheng reg = <0 0x11230000 0 0x2000>; 911e530d080SAllen-KH Cheng reg-names = "pcie-mac"; 912e530d080SAllen-KH Cheng #address-cells = <3>; 913e530d080SAllen-KH Cheng #size-cells = <2>; 914e530d080SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 915e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_26M>, 916e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_96M>, 917e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_32K>, 918e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_PERI_26M>, 919e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 920e530d080SAllen-KH Cheng clock-names = "pl_250m", "tl_26m", "tl_96m", 921e530d080SAllen-KH Cheng "tl_32k", "peri_26m", "top_133m"; 922e530d080SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 923e530d080SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 924e530d080SAllen-KH Cheng interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 925e530d080SAllen-KH Cheng bus-range = <0x00 0xff>; 926e530d080SAllen-KH Cheng ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 927e530d080SAllen-KH Cheng <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 928e530d080SAllen-KH Cheng #interrupt-cells = <1>; 929e530d080SAllen-KH Cheng interrupt-map-mask = <0 0 0 7>; 930e530d080SAllen-KH Cheng interrupt-map = <0 0 0 1 &pcie_intc0 0>, 931e530d080SAllen-KH Cheng <0 0 0 2 &pcie_intc0 1>, 932e530d080SAllen-KH Cheng <0 0 0 3 &pcie_intc0 2>, 933e530d080SAllen-KH Cheng <0 0 0 4 &pcie_intc0 3>; 934e530d080SAllen-KH Cheng 935e530d080SAllen-KH Cheng pcie_intc0: interrupt-controller { 936e530d080SAllen-KH Cheng interrupt-controller; 937e530d080SAllen-KH Cheng #address-cells = <0>; 938e530d080SAllen-KH Cheng #interrupt-cells = <1>; 939e530d080SAllen-KH Cheng }; 940e530d080SAllen-KH Cheng }; 941e530d080SAllen-KH Cheng 942d0a197a0Sbayi cheng nor_flash: spi@11234000 { 943d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 944d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 945d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 946aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 947aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 948aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 949d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 950aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 951aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 952d0a197a0Sbayi cheng #address-cells = <1>; 953d0a197a0Sbayi cheng #size-cells = <0>; 95427f0eb16SAllen-KH Cheng status = "disabled"; 955d0a197a0Sbayi cheng }; 956d0a197a0Sbayi cheng 9574d50a433SAllen-KH Cheng efuse: efuse@11c10000 { 958fda0541cSChunfeng Yun compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 9594d50a433SAllen-KH Cheng reg = <0 0x11c10000 0 0x1000>; 9604d50a433SAllen-KH Cheng #address-cells = <1>; 9614d50a433SAllen-KH Cheng #size-cells = <1>; 9624d50a433SAllen-KH Cheng 9634d50a433SAllen-KH Cheng lvts_e_data1: data1@1c0 { 9644d50a433SAllen-KH Cheng reg = <0x1c0 0x58>; 9654d50a433SAllen-KH Cheng }; 9664d50a433SAllen-KH Cheng 9674d50a433SAllen-KH Cheng svs_calibration: calib@580 { 9684d50a433SAllen-KH Cheng reg = <0x580 0x68>; 9694d50a433SAllen-KH Cheng }; 9704d50a433SAllen-KH Cheng }; 9714d50a433SAllen-KH Cheng 9727f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 97348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 97448489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 97548489980SSeiya Wang <0 0x10217300 0 0x80>; 97648489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 97722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 97822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 97948489980SSeiya Wang clock-names = "main", "dma"; 98048489980SSeiya Wang clock-div = <1>; 98148489980SSeiya Wang #address-cells = <1>; 98248489980SSeiya Wang #size-cells = <0>; 98348489980SSeiya Wang status = "disabled"; 98448489980SSeiya Wang }; 98548489980SSeiya Wang 9865d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 9875d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 9885d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 9895d2b897bSChun-Jie Chen #clock-cells = <1>; 9905d2b897bSChun-Jie Chen }; 9915d2b897bSChun-Jie Chen 9927f1a9f47SFabien Parent i2c7: i2c@11d00000 { 99348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 99448489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 99548489980SSeiya Wang <0 0x10217600 0 0x180>; 99648489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 99722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 99822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 99948489980SSeiya Wang clock-names = "main", "dma"; 100048489980SSeiya Wang clock-div = <1>; 100148489980SSeiya Wang #address-cells = <1>; 100248489980SSeiya Wang #size-cells = <0>; 100348489980SSeiya Wang status = "disabled"; 100448489980SSeiya Wang }; 100548489980SSeiya Wang 10067f1a9f47SFabien Parent i2c8: i2c@11d01000 { 100748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 100848489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 100948489980SSeiya Wang <0 0x10217780 0 0x180>; 101048489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 101122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 101222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 101348489980SSeiya Wang clock-names = "main", "dma"; 101448489980SSeiya Wang clock-div = <1>; 101548489980SSeiya Wang #address-cells = <1>; 101648489980SSeiya Wang #size-cells = <0>; 101748489980SSeiya Wang status = "disabled"; 101848489980SSeiya Wang }; 101948489980SSeiya Wang 10207f1a9f47SFabien Parent i2c9: i2c@11d02000 { 102148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 102248489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 102348489980SSeiya Wang <0 0x10217900 0 0x180>; 102448489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 102522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 102622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 102748489980SSeiya Wang clock-names = "main", "dma"; 102848489980SSeiya Wang clock-div = <1>; 102948489980SSeiya Wang #address-cells = <1>; 103048489980SSeiya Wang #size-cells = <0>; 103148489980SSeiya Wang status = "disabled"; 103248489980SSeiya Wang }; 103348489980SSeiya Wang 10345d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 10355d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 10365d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 10375d2b897bSChun-Jie Chen #clock-cells = <1>; 10385d2b897bSChun-Jie Chen }; 10395d2b897bSChun-Jie Chen 10407f1a9f47SFabien Parent i2c1: i2c@11d20000 { 104148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 104248489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 104348489980SSeiya Wang <0 0x10217100 0 0x80>; 104448489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 104522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 104622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 104748489980SSeiya Wang clock-names = "main", "dma"; 104848489980SSeiya Wang clock-div = <1>; 104948489980SSeiya Wang #address-cells = <1>; 105048489980SSeiya Wang #size-cells = <0>; 105148489980SSeiya Wang status = "disabled"; 105248489980SSeiya Wang }; 105348489980SSeiya Wang 10547f1a9f47SFabien Parent i2c2: i2c@11d21000 { 105548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 105648489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 105748489980SSeiya Wang <0 0x10217180 0 0x180>; 105848489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 105922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 106022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 106148489980SSeiya Wang clock-names = "main", "dma"; 106248489980SSeiya Wang clock-div = <1>; 106348489980SSeiya Wang #address-cells = <1>; 106448489980SSeiya Wang #size-cells = <0>; 106548489980SSeiya Wang status = "disabled"; 106648489980SSeiya Wang }; 106748489980SSeiya Wang 10687f1a9f47SFabien Parent i2c4: i2c@11d22000 { 106948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 107048489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 107148489980SSeiya Wang <0 0x10217380 0 0x180>; 107248489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 107322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 107422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 107548489980SSeiya Wang clock-names = "main", "dma"; 107648489980SSeiya Wang clock-div = <1>; 107748489980SSeiya Wang #address-cells = <1>; 107848489980SSeiya Wang #size-cells = <0>; 107948489980SSeiya Wang status = "disabled"; 108048489980SSeiya Wang }; 108148489980SSeiya Wang 10825d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 10835d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 10845d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 10855d2b897bSChun-Jie Chen #clock-cells = <1>; 10865d2b897bSChun-Jie Chen }; 10875d2b897bSChun-Jie Chen 10887f1a9f47SFabien Parent i2c5: i2c@11e00000 { 108948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 109048489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 109148489980SSeiya Wang <0 0x10217500 0 0x80>; 109248489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 109322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 109422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 109548489980SSeiya Wang clock-names = "main", "dma"; 109648489980SSeiya Wang clock-div = <1>; 109748489980SSeiya Wang #address-cells = <1>; 109848489980SSeiya Wang #size-cells = <0>; 109948489980SSeiya Wang status = "disabled"; 110048489980SSeiya Wang }; 110148489980SSeiya Wang 11025d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 11035d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 11045d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 11055d2b897bSChun-Jie Chen #clock-cells = <1>; 11065d2b897bSChun-Jie Chen }; 11075d2b897bSChun-Jie Chen 110840de66b8SAllen-KH Cheng u3phy0: t-phy@11e40000 { 110940de66b8SAllen-KH Cheng compatible = "mediatek,mt8192-tphy", 111040de66b8SAllen-KH Cheng "mediatek,generic-tphy-v2"; 111140de66b8SAllen-KH Cheng #address-cells = <1>; 111240de66b8SAllen-KH Cheng #size-cells = <1>; 111340de66b8SAllen-KH Cheng ranges = <0x0 0x0 0x11e40000 0x1000>; 111440de66b8SAllen-KH Cheng 111540de66b8SAllen-KH Cheng u2port0: usb-phy@0 { 111640de66b8SAllen-KH Cheng reg = <0x0 0x700>; 111740de66b8SAllen-KH Cheng clocks = <&clk26m>; 111840de66b8SAllen-KH Cheng clock-names = "ref"; 111940de66b8SAllen-KH Cheng #phy-cells = <1>; 112040de66b8SAllen-KH Cheng }; 112140de66b8SAllen-KH Cheng 112240de66b8SAllen-KH Cheng u3port0: usb-phy@700 { 112340de66b8SAllen-KH Cheng reg = <0x700 0x900>; 112440de66b8SAllen-KH Cheng clocks = <&clk26m>; 112540de66b8SAllen-KH Cheng clock-names = "ref"; 112640de66b8SAllen-KH Cheng #phy-cells = <1>; 112740de66b8SAllen-KH Cheng }; 112840de66b8SAllen-KH Cheng }; 112940de66b8SAllen-KH Cheng 113085c4ec6fSAllen-KH Cheng mipi_tx0: dsi-phy@11e50000 { 113185c4ec6fSAllen-KH Cheng compatible = "mediatek,mt8183-mipi-tx"; 113285c4ec6fSAllen-KH Cheng reg = <0 0x11e50000 0 0x1000>; 113385c4ec6fSAllen-KH Cheng clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 113485c4ec6fSAllen-KH Cheng #clock-cells = <0>; 113585c4ec6fSAllen-KH Cheng #phy-cells = <0>; 113685c4ec6fSAllen-KH Cheng clock-output-names = "mipi_tx0_pll"; 113785c4ec6fSAllen-KH Cheng status = "disabled"; 113885c4ec6fSAllen-KH Cheng }; 113985c4ec6fSAllen-KH Cheng 11407f1a9f47SFabien Parent i2c0: i2c@11f00000 { 114148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 114248489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 114348489980SSeiya Wang <0 0x10217080 0 0x80>; 114448489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 114522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 114622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 114748489980SSeiya Wang clock-names = "main", "dma"; 114848489980SSeiya Wang clock-div = <1>; 114948489980SSeiya Wang #address-cells = <1>; 115048489980SSeiya Wang #size-cells = <0>; 115148489980SSeiya Wang status = "disabled"; 115248489980SSeiya Wang }; 115348489980SSeiya Wang 11547f1a9f47SFabien Parent i2c6: i2c@11f01000 { 115548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 115648489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 115748489980SSeiya Wang <0 0x10217580 0 0x80>; 115848489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 115922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 116022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 116148489980SSeiya Wang clock-names = "main", "dma"; 116248489980SSeiya Wang clock-div = <1>; 116348489980SSeiya Wang #address-cells = <1>; 116448489980SSeiya Wang #size-cells = <0>; 116548489980SSeiya Wang status = "disabled"; 116648489980SSeiya Wang }; 11675d2b897bSChun-Jie Chen 11685d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 11695d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 11705d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 11715d2b897bSChun-Jie Chen #clock-cells = <1>; 11725d2b897bSChun-Jie Chen }; 11735d2b897bSChun-Jie Chen 11745d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 11755d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 11765d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 11775d2b897bSChun-Jie Chen #clock-cells = <1>; 11785d2b897bSChun-Jie Chen }; 11795d2b897bSChun-Jie Chen 1180db61337eSAllen-KH Cheng mmc0: mmc@11f60000 { 1181db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1182db61337eSAllen-KH Cheng reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1183db61337eSAllen-KH Cheng interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1184db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1185db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1186db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1187db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1188db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1189db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1190db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1191db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1192db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1193db61337eSAllen-KH Cheng status = "disabled"; 1194db61337eSAllen-KH Cheng }; 1195db61337eSAllen-KH Cheng 1196db61337eSAllen-KH Cheng mmc1: mmc@11f70000 { 1197db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1198db61337eSAllen-KH Cheng reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1199db61337eSAllen-KH Cheng interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1200db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1201db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1202db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1203db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1204db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1205db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1206db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1207db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1208db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1209db61337eSAllen-KH Cheng status = "disabled"; 12105d2b897bSChun-Jie Chen }; 12115d2b897bSChun-Jie Chen 12125d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 12135d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 12145d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 12155d2b897bSChun-Jie Chen #clock-cells = <1>; 12165d2b897bSChun-Jie Chen }; 12175d2b897bSChun-Jie Chen 12185d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 12195d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 12205d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 12215d2b897bSChun-Jie Chen #clock-cells = <1>; 12227d355378SAllen-KH Cheng #reset-cells = <1>; 1223b4b75bacSAllen-KH Cheng mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1224b4b75bacSAllen-KH Cheng <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1225b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1226b4b75bacSAllen-KH Cheng }; 1227b4b75bacSAllen-KH Cheng 1228b4b75bacSAllen-KH Cheng mutex: mutex@14001000 { 1229b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-mutex"; 1230b4b75bacSAllen-KH Cheng reg = <0 0x14001000 0 0x1000>; 1231b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1232b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1233b4b75bacSAllen-KH Cheng mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1234b4b75bacSAllen-KH Cheng <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1235b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12365d2b897bSChun-Jie Chen }; 12375d2b897bSChun-Jie Chen 12384a65b0f1SAllen-KH Cheng smi_common: smi@14002000 { 12394a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-common"; 12404a65b0f1SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 12414a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 12424a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 12434a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 12444a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>; 12454a65b0f1SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 12464a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12474a65b0f1SAllen-KH Cheng }; 12484a65b0f1SAllen-KH Cheng 12494a65b0f1SAllen-KH Cheng larb0: larb@14003000 { 12504a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12514a65b0f1SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 12524a65b0f1SAllen-KH Cheng mediatek,larb-id = <0>; 12534a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12544a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 12554a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12564a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12574a65b0f1SAllen-KH Cheng }; 12584a65b0f1SAllen-KH Cheng 12594a65b0f1SAllen-KH Cheng larb1: larb@14004000 { 12604a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12614a65b0f1SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 12624a65b0f1SAllen-KH Cheng mediatek,larb-id = <1>; 12634a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12644a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 12654a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12664a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12674a65b0f1SAllen-KH Cheng }; 12684a65b0f1SAllen-KH Cheng 1269b4b75bacSAllen-KH Cheng ovl0: ovl@14005000 { 1270b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl"; 1271b4b75bacSAllen-KH Cheng reg = <0 0x14005000 0 0x1000>; 1272b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1273b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0>; 1274b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1275b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1276b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1277b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1278b4b75bacSAllen-KH Cheng }; 1279b4b75bacSAllen-KH Cheng 1280b4b75bacSAllen-KH Cheng ovl_2l0: ovl@14006000 { 1281b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1282b4b75bacSAllen-KH Cheng reg = <0 0x14006000 0 0x1000>; 1283b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1284b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1285b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1286b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1287b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1288b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1289b4b75bacSAllen-KH Cheng }; 1290b4b75bacSAllen-KH Cheng 1291b4b75bacSAllen-KH Cheng rdma0: rdma@14007000 { 1292b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1293b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1294b4b75bacSAllen-KH Cheng reg = <0 0x14007000 0 0x1000>; 1295b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1296b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1297b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1298b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <5120>; 1299b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1300b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1301b4b75bacSAllen-KH Cheng }; 1302b4b75bacSAllen-KH Cheng 1303b4b75bacSAllen-KH Cheng color0: color@14009000 { 1304b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-color", 1305b4b75bacSAllen-KH Cheng "mediatek,mt8173-disp-color"; 1306b4b75bacSAllen-KH Cheng reg = <0 0x14009000 0 0x1000>; 1307b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1308b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1309b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1310b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1311b4b75bacSAllen-KH Cheng }; 1312b4b75bacSAllen-KH Cheng 1313b4b75bacSAllen-KH Cheng ccorr0: ccorr@1400a000 { 1314b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ccorr"; 1315b4b75bacSAllen-KH Cheng reg = <0 0x1400a000 0 0x1000>; 1316b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1317b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1318b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1319b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1320b4b75bacSAllen-KH Cheng }; 1321b4b75bacSAllen-KH Cheng 1322b4b75bacSAllen-KH Cheng aal0: aal@1400b000 { 1323b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-aal", 1324b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-aal"; 1325b4b75bacSAllen-KH Cheng reg = <0 0x1400b000 0 0x1000>; 1326b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1327b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1328b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_AAL0>; 1329b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1330b4b75bacSAllen-KH Cheng }; 1331b4b75bacSAllen-KH Cheng 1332b4b75bacSAllen-KH Cheng gamma0: gamma@1400c000 { 1333b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-gamma", 1334b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-gamma"; 1335b4b75bacSAllen-KH Cheng reg = <0 0x1400c000 0 0x1000>; 1336b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1337b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1338b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1339b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1340b4b75bacSAllen-KH Cheng }; 1341b4b75bacSAllen-KH Cheng 1342b4b75bacSAllen-KH Cheng postmask0: postmask@1400d000 { 1343b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-postmask"; 1344b4b75bacSAllen-KH Cheng reg = <0 0x1400d000 0 0x1000>; 1345b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1346b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1347b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1348b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1349b4b75bacSAllen-KH Cheng }; 1350b4b75bacSAllen-KH Cheng 1351b4b75bacSAllen-KH Cheng dither0: dither@1400e000 { 1352b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-dither", 1353b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-dither"; 1354b4b75bacSAllen-KH Cheng reg = <0 0x1400e000 0 0x1000>; 1355b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1356b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1357b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1358b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1359b4b75bacSAllen-KH Cheng }; 1360b4b75bacSAllen-KH Cheng 13610708ed7cSAllen-KH Cheng dsi0: dsi@14010000 { 13620708ed7cSAllen-KH Cheng compatible = "mediatek,mt8183-dsi"; 13630708ed7cSAllen-KH Cheng reg = <0 0x14010000 0 0x1000>; 13640708ed7cSAllen-KH Cheng interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 13650708ed7cSAllen-KH Cheng clocks = <&mmsys CLK_MM_DSI0>, 13660708ed7cSAllen-KH Cheng <&mmsys CLK_MM_DSI_DSI0>, 13670708ed7cSAllen-KH Cheng <&mipi_tx0>; 13680708ed7cSAllen-KH Cheng clock-names = "engine", "digital", "hs"; 13690708ed7cSAllen-KH Cheng phys = <&mipi_tx0>; 13700708ed7cSAllen-KH Cheng phy-names = "dphy"; 13710708ed7cSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 13720708ed7cSAllen-KH Cheng resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 13730708ed7cSAllen-KH Cheng status = "disabled"; 13740708ed7cSAllen-KH Cheng 13750708ed7cSAllen-KH Cheng port { 13760708ed7cSAllen-KH Cheng dsi_out: endpoint { }; 13770708ed7cSAllen-KH Cheng }; 13780708ed7cSAllen-KH Cheng }; 13790708ed7cSAllen-KH Cheng 1380b4b75bacSAllen-KH Cheng ovl_2l2: ovl@14014000 { 1381b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1382b4b75bacSAllen-KH Cheng reg = <0 0x14014000 0 0x1000>; 1383b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1384b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1385b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1386b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1387b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1388b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1389b4b75bacSAllen-KH Cheng }; 1390b4b75bacSAllen-KH Cheng 1391b4b75bacSAllen-KH Cheng rdma4: rdma@14015000 { 1392b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1393b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1394b4b75bacSAllen-KH Cheng reg = <0 0x14015000 0 0x1000>; 1395b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1396b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1397b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1398b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1399b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <2048>; 1400b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1401b4b75bacSAllen-KH Cheng }; 1402b4b75bacSAllen-KH Cheng 1403b2edd519SAllen-KH Cheng dpi0: dpi@14016000 { 1404b2edd519SAllen-KH Cheng compatible = "mediatek,mt8192-dpi"; 1405b2edd519SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1406b2edd519SAllen-KH Cheng interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1407b2edd519SAllen-KH Cheng clocks = <&mmsys CLK_MM_DPI_DPI0>, 1408b2edd519SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI0>, 1409b2edd519SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 1410b2edd519SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 1411b2edd519SAllen-KH Cheng status = "disabled"; 1412b2edd519SAllen-KH Cheng }; 1413b2edd519SAllen-KH Cheng 14144a65b0f1SAllen-KH Cheng iommu0: m4u@1401d000 { 14154a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-m4u"; 14164a65b0f1SAllen-KH Cheng reg = <0 0x1401d000 0 0x1000>; 14174a65b0f1SAllen-KH Cheng mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 14184a65b0f1SAllen-KH Cheng <&larb4>, <&larb5>, <&larb7>, 14194a65b0f1SAllen-KH Cheng <&larb9>, <&larb11>, <&larb13>, 14204a65b0f1SAllen-KH Cheng <&larb14>, <&larb16>, <&larb17>, 14214a65b0f1SAllen-KH Cheng <&larb18>, <&larb19>, <&larb20>; 14224a65b0f1SAllen-KH Cheng interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 14234a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 14244a65b0f1SAllen-KH Cheng clock-names = "bclk"; 14254a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14264a65b0f1SAllen-KH Cheng #iommu-cells = <1>; 14274a65b0f1SAllen-KH Cheng }; 14284a65b0f1SAllen-KH Cheng 14295d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 14305d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 14315d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 14325d2b897bSChun-Jie Chen #clock-cells = <1>; 14335d2b897bSChun-Jie Chen }; 14345d2b897bSChun-Jie Chen 14354a65b0f1SAllen-KH Cheng larb9: larb@1502e000 { 14364a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14374a65b0f1SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 14384a65b0f1SAllen-KH Cheng mediatek,larb-id = <9>; 14394a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14404a65b0f1SAllen-KH Cheng clocks = <&imgsys CLK_IMG_LARB9>, 14414a65b0f1SAllen-KH Cheng <&imgsys CLK_IMG_LARB9>; 14424a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14434a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 14444a65b0f1SAllen-KH Cheng }; 14454a65b0f1SAllen-KH Cheng 14465d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 14475d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 14485d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 14495d2b897bSChun-Jie Chen #clock-cells = <1>; 14505d2b897bSChun-Jie Chen }; 14515d2b897bSChun-Jie Chen 14524a65b0f1SAllen-KH Cheng larb11: larb@1582e000 { 14534a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14544a65b0f1SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 14554a65b0f1SAllen-KH Cheng mediatek,larb-id = <11>; 14564a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14574a65b0f1SAllen-KH Cheng clocks = <&imgsys2 CLK_IMG2_LARB11>, 14584a65b0f1SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB11>; 14594a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14604a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 14614a65b0f1SAllen-KH Cheng }; 14624a65b0f1SAllen-KH Cheng 14634a65b0f1SAllen-KH Cheng larb5: larb@1600d000 { 14644a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14654a65b0f1SAllen-KH Cheng reg = <0 0x1600d000 0 0x1000>; 14664a65b0f1SAllen-KH Cheng mediatek,larb-id = <5>; 14674a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14684a65b0f1SAllen-KH Cheng clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 14694a65b0f1SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 14704a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14714a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 14724a65b0f1SAllen-KH Cheng }; 14734a65b0f1SAllen-KH Cheng 14745d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 14755d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 14765d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 14775d2b897bSChun-Jie Chen #clock-cells = <1>; 14785d2b897bSChun-Jie Chen }; 14795d2b897bSChun-Jie Chen 14804a65b0f1SAllen-KH Cheng larb4: larb@1602e000 { 14814a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14824a65b0f1SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 14834a65b0f1SAllen-KH Cheng mediatek,larb-id = <4>; 14844a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14854a65b0f1SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 14864a65b0f1SAllen-KH Cheng <&vdecsys CLK_VDEC_SOC_LARB1>; 14874a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14884a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 14894a65b0f1SAllen-KH Cheng }; 14904a65b0f1SAllen-KH Cheng 14915d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 14925d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 14935d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 14945d2b897bSChun-Jie Chen #clock-cells = <1>; 14955d2b897bSChun-Jie Chen }; 14965d2b897bSChun-Jie Chen 14975d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 14985d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 14995d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 15005d2b897bSChun-Jie Chen #clock-cells = <1>; 15015d2b897bSChun-Jie Chen }; 15025d2b897bSChun-Jie Chen 15034a65b0f1SAllen-KH Cheng larb7: larb@17010000 { 15044a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15054a65b0f1SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 15064a65b0f1SAllen-KH Cheng mediatek,larb-id = <7>; 15074a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15084a65b0f1SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET0_LARB>, 15094a65b0f1SAllen-KH Cheng <&vencsys CLK_VENC_SET1_VENC>; 15104a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15114a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 15124a65b0f1SAllen-KH Cheng }; 15134a65b0f1SAllen-KH Cheng 1514aa8f3711SAllen-KH Cheng vcodec_enc: vcodec@17020000 { 1515aa8f3711SAllen-KH Cheng compatible = "mediatek,mt8192-vcodec-enc"; 1516aa8f3711SAllen-KH Cheng reg = <0 0x17020000 0 0x2000>; 1517aa8f3711SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1518aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REC>, 1519aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1520aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1521aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1522aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1523aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1524aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1525aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1526aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1527aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1528aa8f3711SAllen-KH Cheng interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1529aa8f3711SAllen-KH Cheng mediatek,scp = <&scp>; 1530aa8f3711SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1531aa8f3711SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET1_VENC>; 1532aa8f3711SAllen-KH Cheng clock-names = "venc-set1"; 1533aa8f3711SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1534aa8f3711SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1535aa8f3711SAllen-KH Cheng }; 1536aa8f3711SAllen-KH Cheng 15375d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 15385d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 15395d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 15405d2b897bSChun-Jie Chen #clock-cells = <1>; 15415d2b897bSChun-Jie Chen }; 15425d2b897bSChun-Jie Chen 15434a65b0f1SAllen-KH Cheng larb13: larb@1a001000 { 15444a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15454a65b0f1SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 15464a65b0f1SAllen-KH Cheng mediatek,larb-id = <13>; 15474a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15484a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 15494a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB13>; 15504a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15514a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 15524a65b0f1SAllen-KH Cheng }; 15534a65b0f1SAllen-KH Cheng 15544a65b0f1SAllen-KH Cheng larb14: larb@1a002000 { 15554a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15564a65b0f1SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 15574a65b0f1SAllen-KH Cheng mediatek,larb-id = <14>; 15584a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15594a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 15604a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB14>; 15614a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15624a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 15634a65b0f1SAllen-KH Cheng }; 15644a65b0f1SAllen-KH Cheng 15654a65b0f1SAllen-KH Cheng larb16: larb@1a00f000 { 15664a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15674a65b0f1SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 15684a65b0f1SAllen-KH Cheng mediatek,larb-id = <16>; 15694a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15704a65b0f1SAllen-KH Cheng clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 15714a65b0f1SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX>; 15724a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15734a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 15744a65b0f1SAllen-KH Cheng }; 15754a65b0f1SAllen-KH Cheng 15764a65b0f1SAllen-KH Cheng larb17: larb@1a010000 { 15774a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15784a65b0f1SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 15794a65b0f1SAllen-KH Cheng mediatek,larb-id = <17>; 15804a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15814a65b0f1SAllen-KH Cheng clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 15824a65b0f1SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX>; 15834a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15844a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 15854a65b0f1SAllen-KH Cheng }; 15864a65b0f1SAllen-KH Cheng 15874a65b0f1SAllen-KH Cheng larb18: larb@1a011000 { 15884a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15894a65b0f1SAllen-KH Cheng reg = <0 0x1a011000 0 0x1000>; 15904a65b0f1SAllen-KH Cheng mediatek,larb-id = <18>; 15914a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15924a65b0f1SAllen-KH Cheng clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 15934a65b0f1SAllen-KH Cheng <&camsys_rawc CLK_CAM_RAWC_CAM>; 15944a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15954a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 15964a65b0f1SAllen-KH Cheng }; 15974a65b0f1SAllen-KH Cheng 15985d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 15995d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 16005d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 16015d2b897bSChun-Jie Chen #clock-cells = <1>; 16025d2b897bSChun-Jie Chen }; 16035d2b897bSChun-Jie Chen 16045d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 16055d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 16065d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 16075d2b897bSChun-Jie Chen #clock-cells = <1>; 16085d2b897bSChun-Jie Chen }; 16095d2b897bSChun-Jie Chen 16105d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 16115d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 16125d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 16135d2b897bSChun-Jie Chen #clock-cells = <1>; 16145d2b897bSChun-Jie Chen }; 16155d2b897bSChun-Jie Chen 16165d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 16175d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 16185d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 16195d2b897bSChun-Jie Chen #clock-cells = <1>; 16205d2b897bSChun-Jie Chen }; 16215d2b897bSChun-Jie Chen 16224a65b0f1SAllen-KH Cheng larb20: larb@1b00f000 { 16234a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16244a65b0f1SAllen-KH Cheng reg = <0 0x1b00f000 0 0x1000>; 16254a65b0f1SAllen-KH Cheng mediatek,larb-id = <20>; 16264a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16274a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 16284a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB20>; 16294a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16304a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 16314a65b0f1SAllen-KH Cheng }; 16324a65b0f1SAllen-KH Cheng 16334a65b0f1SAllen-KH Cheng larb19: larb@1b10f000 { 16344a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16354a65b0f1SAllen-KH Cheng reg = <0 0x1b10f000 0 0x1000>; 16364a65b0f1SAllen-KH Cheng mediatek,larb-id = <19>; 16374a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16384a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 16394a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB19>; 16404a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16414a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 16424a65b0f1SAllen-KH Cheng }; 16434a65b0f1SAllen-KH Cheng 16445d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 16455d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 16465d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 16475d2b897bSChun-Jie Chen #clock-cells = <1>; 16485d2b897bSChun-Jie Chen }; 16494a65b0f1SAllen-KH Cheng 16504a65b0f1SAllen-KH Cheng larb2: larb@1f002000 { 16514a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16524a65b0f1SAllen-KH Cheng reg = <0 0x1f002000 0 0x1000>; 16534a65b0f1SAllen-KH Cheng mediatek,larb-id = <2>; 16544a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16554a65b0f1SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, 16564a65b0f1SAllen-KH Cheng <&mdpsys CLK_MDP_SMI0>; 16574a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16584a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 16594a65b0f1SAllen-KH Cheng }; 166048489980SSeiya Wang }; 166148489980SSeiya Wang}; 1662