148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 1148489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 1248489980SSeiya Wang 1348489980SSeiya Wang/ { 1448489980SSeiya Wang compatible = "mediatek,mt8192"; 1548489980SSeiya Wang interrupt-parent = <&gic>; 1648489980SSeiya Wang #address-cells = <2>; 1748489980SSeiya Wang #size-cells = <2>; 1848489980SSeiya Wang 1948489980SSeiya Wang clk26m: oscillator0 { 2048489980SSeiya Wang compatible = "fixed-clock"; 2148489980SSeiya Wang #clock-cells = <0>; 2248489980SSeiya Wang clock-frequency = <26000000>; 2348489980SSeiya Wang clock-output-names = "clk26m"; 2448489980SSeiya Wang }; 2548489980SSeiya Wang 2648489980SSeiya Wang clk32k: oscillator1 { 2748489980SSeiya Wang compatible = "fixed-clock"; 2848489980SSeiya Wang #clock-cells = <0>; 2948489980SSeiya Wang clock-frequency = <32768>; 3048489980SSeiya Wang clock-output-names = "clk32k"; 3148489980SSeiya Wang }; 3248489980SSeiya Wang 3348489980SSeiya Wang cpus { 3448489980SSeiya Wang #address-cells = <1>; 3548489980SSeiya Wang #size-cells = <0>; 3648489980SSeiya Wang 3748489980SSeiya Wang cpu0: cpu@0 { 3848489980SSeiya Wang device_type = "cpu"; 3948489980SSeiya Wang compatible = "arm,cortex-a55"; 4048489980SSeiya Wang reg = <0x000>; 4148489980SSeiya Wang enable-method = "psci"; 4248489980SSeiya Wang clock-frequency = <1701000000>; 439260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 4448489980SSeiya Wang next-level-cache = <&l2_0>; 4548489980SSeiya Wang capacity-dmips-mhz = <530>; 4648489980SSeiya Wang }; 4748489980SSeiya Wang 4848489980SSeiya Wang cpu1: cpu@100 { 4948489980SSeiya Wang device_type = "cpu"; 5048489980SSeiya Wang compatible = "arm,cortex-a55"; 5148489980SSeiya Wang reg = <0x100>; 5248489980SSeiya Wang enable-method = "psci"; 5348489980SSeiya Wang clock-frequency = <1701000000>; 549260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 5548489980SSeiya Wang next-level-cache = <&l2_0>; 5648489980SSeiya Wang capacity-dmips-mhz = <530>; 5748489980SSeiya Wang }; 5848489980SSeiya Wang 5948489980SSeiya Wang cpu2: cpu@200 { 6048489980SSeiya Wang device_type = "cpu"; 6148489980SSeiya Wang compatible = "arm,cortex-a55"; 6248489980SSeiya Wang reg = <0x200>; 6348489980SSeiya Wang enable-method = "psci"; 6448489980SSeiya Wang clock-frequency = <1701000000>; 659260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 6648489980SSeiya Wang next-level-cache = <&l2_0>; 6748489980SSeiya Wang capacity-dmips-mhz = <530>; 6848489980SSeiya Wang }; 6948489980SSeiya Wang 7048489980SSeiya Wang cpu3: cpu@300 { 7148489980SSeiya Wang device_type = "cpu"; 7248489980SSeiya Wang compatible = "arm,cortex-a55"; 7348489980SSeiya Wang reg = <0x300>; 7448489980SSeiya Wang enable-method = "psci"; 7548489980SSeiya Wang clock-frequency = <1701000000>; 769260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 7748489980SSeiya Wang next-level-cache = <&l2_0>; 7848489980SSeiya Wang capacity-dmips-mhz = <530>; 7948489980SSeiya Wang }; 8048489980SSeiya Wang 8148489980SSeiya Wang cpu4: cpu@400 { 8248489980SSeiya Wang device_type = "cpu"; 8348489980SSeiya Wang compatible = "arm,cortex-a76"; 8448489980SSeiya Wang reg = <0x400>; 8548489980SSeiya Wang enable-method = "psci"; 8648489980SSeiya Wang clock-frequency = <2171000000>; 879260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 8848489980SSeiya Wang next-level-cache = <&l2_1>; 8948489980SSeiya Wang capacity-dmips-mhz = <1024>; 9048489980SSeiya Wang }; 9148489980SSeiya Wang 9248489980SSeiya Wang cpu5: cpu@500 { 9348489980SSeiya Wang device_type = "cpu"; 9448489980SSeiya Wang compatible = "arm,cortex-a76"; 9548489980SSeiya Wang reg = <0x500>; 9648489980SSeiya Wang enable-method = "psci"; 9748489980SSeiya Wang clock-frequency = <2171000000>; 989260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 9948489980SSeiya Wang next-level-cache = <&l2_1>; 10048489980SSeiya Wang capacity-dmips-mhz = <1024>; 10148489980SSeiya Wang }; 10248489980SSeiya Wang 10348489980SSeiya Wang cpu6: cpu@600 { 10448489980SSeiya Wang device_type = "cpu"; 10548489980SSeiya Wang compatible = "arm,cortex-a76"; 10648489980SSeiya Wang reg = <0x600>; 10748489980SSeiya Wang enable-method = "psci"; 10848489980SSeiya Wang clock-frequency = <2171000000>; 1099260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 11048489980SSeiya Wang next-level-cache = <&l2_1>; 11148489980SSeiya Wang capacity-dmips-mhz = <1024>; 11248489980SSeiya Wang }; 11348489980SSeiya Wang 11448489980SSeiya Wang cpu7: cpu@700 { 11548489980SSeiya Wang device_type = "cpu"; 11648489980SSeiya Wang compatible = "arm,cortex-a76"; 11748489980SSeiya Wang reg = <0x700>; 11848489980SSeiya Wang enable-method = "psci"; 11948489980SSeiya Wang clock-frequency = <2171000000>; 1209260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 12148489980SSeiya Wang next-level-cache = <&l2_1>; 12248489980SSeiya Wang capacity-dmips-mhz = <1024>; 12348489980SSeiya Wang }; 12448489980SSeiya Wang 12548489980SSeiya Wang cpu-map { 12648489980SSeiya Wang cluster0 { 12748489980SSeiya Wang core0 { 12848489980SSeiya Wang cpu = <&cpu0>; 12948489980SSeiya Wang }; 13048489980SSeiya Wang core1 { 13148489980SSeiya Wang cpu = <&cpu1>; 13248489980SSeiya Wang }; 13348489980SSeiya Wang core2 { 13448489980SSeiya Wang cpu = <&cpu2>; 13548489980SSeiya Wang }; 13648489980SSeiya Wang core3 { 13748489980SSeiya Wang cpu = <&cpu3>; 13848489980SSeiya Wang }; 13948489980SSeiya Wang }; 14048489980SSeiya Wang 14148489980SSeiya Wang cluster1 { 14248489980SSeiya Wang core0 { 14348489980SSeiya Wang cpu = <&cpu4>; 14448489980SSeiya Wang }; 14548489980SSeiya Wang core1 { 14648489980SSeiya Wang cpu = <&cpu5>; 14748489980SSeiya Wang }; 14848489980SSeiya Wang core2 { 14948489980SSeiya Wang cpu = <&cpu6>; 15048489980SSeiya Wang }; 15148489980SSeiya Wang core3 { 15248489980SSeiya Wang cpu = <&cpu7>; 15348489980SSeiya Wang }; 15448489980SSeiya Wang }; 15548489980SSeiya Wang }; 15648489980SSeiya Wang 15748489980SSeiya Wang l2_0: l2-cache0 { 15848489980SSeiya Wang compatible = "cache"; 15948489980SSeiya Wang next-level-cache = <&l3_0>; 16048489980SSeiya Wang }; 16148489980SSeiya Wang 16248489980SSeiya Wang l2_1: l2-cache1 { 16348489980SSeiya Wang compatible = "cache"; 16448489980SSeiya Wang next-level-cache = <&l3_0>; 16548489980SSeiya Wang }; 16648489980SSeiya Wang 16748489980SSeiya Wang l3_0: l3-cache { 16848489980SSeiya Wang compatible = "cache"; 16948489980SSeiya Wang }; 1709260918dSJames Liao 1719260918dSJames Liao idle-states { 1729260918dSJames Liao entry-method = "arm,psci"; 1739260918dSJames Liao cpuoff_l: cpuoff_l { 1749260918dSJames Liao compatible = "arm,idle-state"; 1759260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1769260918dSJames Liao local-timer-stop; 1779260918dSJames Liao entry-latency-us = <55>; 1789260918dSJames Liao exit-latency-us = <140>; 1799260918dSJames Liao min-residency-us = <780>; 1809260918dSJames Liao }; 1819260918dSJames Liao cpuoff_b: cpuoff_b { 1829260918dSJames Liao compatible = "arm,idle-state"; 1839260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1849260918dSJames Liao local-timer-stop; 1859260918dSJames Liao entry-latency-us = <35>; 1869260918dSJames Liao exit-latency-us = <145>; 1879260918dSJames Liao min-residency-us = <720>; 1889260918dSJames Liao }; 1899260918dSJames Liao clusteroff_l: clusteroff_l { 1909260918dSJames Liao compatible = "arm,idle-state"; 1919260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 1929260918dSJames Liao local-timer-stop; 1939260918dSJames Liao entry-latency-us = <60>; 1949260918dSJames Liao exit-latency-us = <155>; 1959260918dSJames Liao min-residency-us = <860>; 1969260918dSJames Liao }; 1979260918dSJames Liao clusteroff_b: clusteroff_b { 1989260918dSJames Liao compatible = "arm,idle-state"; 1999260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2009260918dSJames Liao local-timer-stop; 2019260918dSJames Liao entry-latency-us = <40>; 2029260918dSJames Liao exit-latency-us = <155>; 2039260918dSJames Liao min-residency-us = <780>; 2049260918dSJames Liao }; 2059260918dSJames Liao }; 20648489980SSeiya Wang }; 20748489980SSeiya Wang 20848489980SSeiya Wang pmu-a55 { 20948489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 21048489980SSeiya Wang interrupt-parent = <&gic>; 21148489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 21248489980SSeiya Wang }; 21348489980SSeiya Wang 21448489980SSeiya Wang pmu-a76 { 21548489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 21648489980SSeiya Wang interrupt-parent = <&gic>; 21748489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 21848489980SSeiya Wang }; 21948489980SSeiya Wang 22048489980SSeiya Wang psci { 22148489980SSeiya Wang compatible = "arm,psci-1.0"; 22248489980SSeiya Wang method = "smc"; 22348489980SSeiya Wang }; 22448489980SSeiya Wang 22548489980SSeiya Wang timer: timer { 22648489980SSeiya Wang compatible = "arm,armv8-timer"; 22748489980SSeiya Wang interrupt-parent = <&gic>; 22848489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 22948489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 23048489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 23148489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 23248489980SSeiya Wang clock-frequency = <13000000>; 23348489980SSeiya Wang }; 23448489980SSeiya Wang 23548489980SSeiya Wang soc { 23648489980SSeiya Wang #address-cells = <2>; 23748489980SSeiya Wang #size-cells = <2>; 23848489980SSeiya Wang compatible = "simple-bus"; 23948489980SSeiya Wang ranges; 24048489980SSeiya Wang 24148489980SSeiya Wang gic: interrupt-controller@c000000 { 24248489980SSeiya Wang compatible = "arm,gic-v3"; 24348489980SSeiya Wang #interrupt-cells = <4>; 24448489980SSeiya Wang #redistributor-regions = <1>; 24548489980SSeiya Wang interrupt-parent = <&gic>; 24648489980SSeiya Wang interrupt-controller; 24748489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 24848489980SSeiya Wang <0 0x0c040000 0 0x200000>; 24948489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 25048489980SSeiya Wang 25148489980SSeiya Wang ppi-partitions { 25248489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 25348489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 25448489980SSeiya Wang }; 25548489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 25648489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 25748489980SSeiya Wang }; 25848489980SSeiya Wang }; 25948489980SSeiya Wang }; 26048489980SSeiya Wang 2615d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 2625d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 2635d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 2645d2b897bSChun-Jie Chen #clock-cells = <1>; 2655d2b897bSChun-Jie Chen }; 2665d2b897bSChun-Jie Chen 2675d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 2685d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 2695d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 2705d2b897bSChun-Jie Chen #clock-cells = <1>; 2715d2b897bSChun-Jie Chen }; 2725d2b897bSChun-Jie Chen 2735d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 2745d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 2755d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 2765d2b897bSChun-Jie Chen #clock-cells = <1>; 2775d2b897bSChun-Jie Chen }; 2785d2b897bSChun-Jie Chen 27948489980SSeiya Wang pio: pinctrl@10005000 { 28048489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 28148489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 28248489980SSeiya Wang <0 0x11c20000 0 0x1000>, 28348489980SSeiya Wang <0 0x11d10000 0 0x1000>, 28448489980SSeiya Wang <0 0x11d30000 0 0x1000>, 28548489980SSeiya Wang <0 0x11d40000 0 0x1000>, 28648489980SSeiya Wang <0 0x11e20000 0 0x1000>, 28748489980SSeiya Wang <0 0x11e70000 0 0x1000>, 28848489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 28948489980SSeiya Wang <0 0x11f20000 0 0x1000>, 29048489980SSeiya Wang <0 0x11f30000 0 0x1000>, 29148489980SSeiya Wang <0 0x1000b000 0 0x1000>; 29248489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 29348489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 29448489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 29548489980SSeiya Wang "iocfg_tl", "eint"; 29648489980SSeiya Wang gpio-controller; 29748489980SSeiya Wang #gpio-cells = <2>; 29848489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 29948489980SSeiya Wang interrupt-controller; 30048489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 30148489980SSeiya Wang #interrupt-cells = <2>; 30248489980SSeiya Wang }; 30348489980SSeiya Wang 3045d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 3055d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 3065d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 3075d2b897bSChun-Jie Chen #clock-cells = <1>; 3085d2b897bSChun-Jie Chen }; 3095d2b897bSChun-Jie Chen 31048489980SSeiya Wang systimer: timer@10017000 { 31148489980SSeiya Wang compatible = "mediatek,mt8192-timer", 31248489980SSeiya Wang "mediatek,mt6765-timer"; 31348489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 31448489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 315*dde3c175SAllen-KH Cheng clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 31648489980SSeiya Wang clock-names = "clk13m"; 31748489980SSeiya Wang }; 31848489980SSeiya Wang 3195d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 3205d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 3215d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 3225d2b897bSChun-Jie Chen #clock-cells = <1>; 3235d2b897bSChun-Jie Chen }; 3245d2b897bSChun-Jie Chen 32548489980SSeiya Wang uart0: serial@11002000 { 32648489980SSeiya Wang compatible = "mediatek,mt8192-uart", 32748489980SSeiya Wang "mediatek,mt6577-uart"; 32848489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 32948489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 33073ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 33148489980SSeiya Wang clock-names = "baud", "bus"; 33248489980SSeiya Wang status = "disabled"; 33348489980SSeiya Wang }; 33448489980SSeiya Wang 33548489980SSeiya Wang uart1: serial@11003000 { 33648489980SSeiya Wang compatible = "mediatek,mt8192-uart", 33748489980SSeiya Wang "mediatek,mt6577-uart"; 33848489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 33948489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 34073ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 34148489980SSeiya Wang clock-names = "baud", "bus"; 34248489980SSeiya Wang status = "disabled"; 34348489980SSeiya Wang }; 34448489980SSeiya Wang 3455d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 3465d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 3475d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 3485d2b897bSChun-Jie Chen #clock-cells = <1>; 3495d2b897bSChun-Jie Chen }; 3505d2b897bSChun-Jie Chen 35148489980SSeiya Wang spi0: spi@1100a000 { 35248489980SSeiya Wang compatible = "mediatek,mt8192-spi", 35348489980SSeiya Wang "mediatek,mt6765-spi"; 35448489980SSeiya Wang #address-cells = <1>; 35548489980SSeiya Wang #size-cells = <0>; 35648489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 35748489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 3587f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 3597f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 3607f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 36148489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 36248489980SSeiya Wang status = "disabled"; 36348489980SSeiya Wang }; 36448489980SSeiya Wang 36548489980SSeiya Wang spi1: spi@11010000 { 36648489980SSeiya Wang compatible = "mediatek,mt8192-spi", 36748489980SSeiya Wang "mediatek,mt6765-spi"; 36848489980SSeiya Wang #address-cells = <1>; 36948489980SSeiya Wang #size-cells = <0>; 37048489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 37148489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 3727f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 3737f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 3747f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 37548489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 37648489980SSeiya Wang status = "disabled"; 37748489980SSeiya Wang }; 37848489980SSeiya Wang 37948489980SSeiya Wang spi2: spi@11012000 { 38048489980SSeiya Wang compatible = "mediatek,mt8192-spi", 38148489980SSeiya Wang "mediatek,mt6765-spi"; 38248489980SSeiya Wang #address-cells = <1>; 38348489980SSeiya Wang #size-cells = <0>; 38448489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 38548489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 3867f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 3877f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 3887f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 38948489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 39048489980SSeiya Wang status = "disabled"; 39148489980SSeiya Wang }; 39248489980SSeiya Wang 39348489980SSeiya Wang spi3: spi@11013000 { 39448489980SSeiya Wang compatible = "mediatek,mt8192-spi", 39548489980SSeiya Wang "mediatek,mt6765-spi"; 39648489980SSeiya Wang #address-cells = <1>; 39748489980SSeiya Wang #size-cells = <0>; 39848489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 39948489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 4007f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 4017f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 4027f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 40348489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 40448489980SSeiya Wang status = "disabled"; 40548489980SSeiya Wang }; 40648489980SSeiya Wang 40748489980SSeiya Wang spi4: spi@11018000 { 40848489980SSeiya Wang compatible = "mediatek,mt8192-spi", 40948489980SSeiya Wang "mediatek,mt6765-spi"; 41048489980SSeiya Wang #address-cells = <1>; 41148489980SSeiya Wang #size-cells = <0>; 41248489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 41348489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 4147f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 4157f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 4167f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 41748489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 41848489980SSeiya Wang status = "disabled"; 41948489980SSeiya Wang }; 42048489980SSeiya Wang 42148489980SSeiya Wang spi5: spi@11019000 { 42248489980SSeiya Wang compatible = "mediatek,mt8192-spi", 42348489980SSeiya Wang "mediatek,mt6765-spi"; 42448489980SSeiya Wang #address-cells = <1>; 42548489980SSeiya Wang #size-cells = <0>; 42648489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 42748489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 4287f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 4297f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 4307f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 43148489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 43248489980SSeiya Wang status = "disabled"; 43348489980SSeiya Wang }; 43448489980SSeiya Wang 43548489980SSeiya Wang spi6: spi@1101d000 { 43648489980SSeiya Wang compatible = "mediatek,mt8192-spi", 43748489980SSeiya Wang "mediatek,mt6765-spi"; 43848489980SSeiya Wang #address-cells = <1>; 43948489980SSeiya Wang #size-cells = <0>; 44048489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 44148489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 4427f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 4437f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 4447f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 44548489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 44648489980SSeiya Wang status = "disabled"; 44748489980SSeiya Wang }; 44848489980SSeiya Wang 44948489980SSeiya Wang spi7: spi@1101e000 { 45048489980SSeiya Wang compatible = "mediatek,mt8192-spi", 45148489980SSeiya Wang "mediatek,mt6765-spi"; 45248489980SSeiya Wang #address-cells = <1>; 45348489980SSeiya Wang #size-cells = <0>; 45448489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 45548489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 4567f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 4577f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 4587f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 45948489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 46048489980SSeiya Wang status = "disabled"; 46148489980SSeiya Wang }; 46248489980SSeiya Wang 463d0a197a0Sbayi cheng nor_flash: spi@11234000 { 464d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 465d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 466d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 467aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 468aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 469aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 470d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 471aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 472aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 473d0a197a0Sbayi cheng #address-cells = <1>; 474d0a197a0Sbayi cheng #size-cells = <0>; 475d0a197a0Sbayi cheng status = "disable"; 476d0a197a0Sbayi cheng }; 477d0a197a0Sbayi cheng 4785d2b897bSChun-Jie Chen audsys: clock-controller@11210000 { 4795d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-audsys", "syscon"; 4805d2b897bSChun-Jie Chen reg = <0 0x11210000 0 0x1000>; 4815d2b897bSChun-Jie Chen #clock-cells = <1>; 4825d2b897bSChun-Jie Chen }; 4835d2b897bSChun-Jie Chen 4847f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 48548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 48648489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 48748489980SSeiya Wang <0 0x10217300 0 0x80>; 48848489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 48922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 49022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 49148489980SSeiya Wang clock-names = "main", "dma"; 49248489980SSeiya Wang clock-div = <1>; 49348489980SSeiya Wang #address-cells = <1>; 49448489980SSeiya Wang #size-cells = <0>; 49548489980SSeiya Wang status = "disabled"; 49648489980SSeiya Wang }; 49748489980SSeiya Wang 4985d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 4995d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 5005d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 5015d2b897bSChun-Jie Chen #clock-cells = <1>; 5025d2b897bSChun-Jie Chen }; 5035d2b897bSChun-Jie Chen 5047f1a9f47SFabien Parent i2c7: i2c@11d00000 { 50548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 50648489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 50748489980SSeiya Wang <0 0x10217600 0 0x180>; 50848489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 50922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 51022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 51148489980SSeiya Wang clock-names = "main", "dma"; 51248489980SSeiya Wang clock-div = <1>; 51348489980SSeiya Wang #address-cells = <1>; 51448489980SSeiya Wang #size-cells = <0>; 51548489980SSeiya Wang status = "disabled"; 51648489980SSeiya Wang }; 51748489980SSeiya Wang 5187f1a9f47SFabien Parent i2c8: i2c@11d01000 { 51948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 52048489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 52148489980SSeiya Wang <0 0x10217780 0 0x180>; 52248489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 52322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 52422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 52548489980SSeiya Wang clock-names = "main", "dma"; 52648489980SSeiya Wang clock-div = <1>; 52748489980SSeiya Wang #address-cells = <1>; 52848489980SSeiya Wang #size-cells = <0>; 52948489980SSeiya Wang status = "disabled"; 53048489980SSeiya Wang }; 53148489980SSeiya Wang 5327f1a9f47SFabien Parent i2c9: i2c@11d02000 { 53348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 53448489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 53548489980SSeiya Wang <0 0x10217900 0 0x180>; 53648489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 53722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 53822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 53948489980SSeiya Wang clock-names = "main", "dma"; 54048489980SSeiya Wang clock-div = <1>; 54148489980SSeiya Wang #address-cells = <1>; 54248489980SSeiya Wang #size-cells = <0>; 54348489980SSeiya Wang status = "disabled"; 54448489980SSeiya Wang }; 54548489980SSeiya Wang 5465d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 5475d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 5485d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 5495d2b897bSChun-Jie Chen #clock-cells = <1>; 5505d2b897bSChun-Jie Chen }; 5515d2b897bSChun-Jie Chen 5527f1a9f47SFabien Parent i2c1: i2c@11d20000 { 55348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 55448489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 55548489980SSeiya Wang <0 0x10217100 0 0x80>; 55648489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 55722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 55822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 55948489980SSeiya Wang clock-names = "main", "dma"; 56048489980SSeiya Wang clock-div = <1>; 56148489980SSeiya Wang #address-cells = <1>; 56248489980SSeiya Wang #size-cells = <0>; 56348489980SSeiya Wang status = "disabled"; 56448489980SSeiya Wang }; 56548489980SSeiya Wang 5667f1a9f47SFabien Parent i2c2: i2c@11d21000 { 56748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 56848489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 56948489980SSeiya Wang <0 0x10217180 0 0x180>; 57048489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 57122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 57222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 57348489980SSeiya Wang clock-names = "main", "dma"; 57448489980SSeiya Wang clock-div = <1>; 57548489980SSeiya Wang #address-cells = <1>; 57648489980SSeiya Wang #size-cells = <0>; 57748489980SSeiya Wang status = "disabled"; 57848489980SSeiya Wang }; 57948489980SSeiya Wang 5807f1a9f47SFabien Parent i2c4: i2c@11d22000 { 58148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 58248489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 58348489980SSeiya Wang <0 0x10217380 0 0x180>; 58448489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 58522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 58622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 58748489980SSeiya Wang clock-names = "main", "dma"; 58848489980SSeiya Wang clock-div = <1>; 58948489980SSeiya Wang #address-cells = <1>; 59048489980SSeiya Wang #size-cells = <0>; 59148489980SSeiya Wang status = "disabled"; 59248489980SSeiya Wang }; 59348489980SSeiya Wang 5945d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 5955d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 5965d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 5975d2b897bSChun-Jie Chen #clock-cells = <1>; 5985d2b897bSChun-Jie Chen }; 5995d2b897bSChun-Jie Chen 6007f1a9f47SFabien Parent i2c5: i2c@11e00000 { 60148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 60248489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 60348489980SSeiya Wang <0 0x10217500 0 0x80>; 60448489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 60522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 60622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 60748489980SSeiya Wang clock-names = "main", "dma"; 60848489980SSeiya Wang clock-div = <1>; 60948489980SSeiya Wang #address-cells = <1>; 61048489980SSeiya Wang #size-cells = <0>; 61148489980SSeiya Wang status = "disabled"; 61248489980SSeiya Wang }; 61348489980SSeiya Wang 6145d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 6155d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 6165d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 6175d2b897bSChun-Jie Chen #clock-cells = <1>; 6185d2b897bSChun-Jie Chen }; 6195d2b897bSChun-Jie Chen 6207f1a9f47SFabien Parent i2c0: i2c@11f00000 { 62148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 62248489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 62348489980SSeiya Wang <0 0x10217080 0 0x80>; 62448489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 62522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 62622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 62748489980SSeiya Wang clock-names = "main", "dma"; 62848489980SSeiya Wang clock-div = <1>; 62948489980SSeiya Wang #address-cells = <1>; 63048489980SSeiya Wang #size-cells = <0>; 63148489980SSeiya Wang status = "disabled"; 63248489980SSeiya Wang }; 63348489980SSeiya Wang 6347f1a9f47SFabien Parent i2c6: i2c@11f01000 { 63548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 63648489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 63748489980SSeiya Wang <0 0x10217580 0 0x80>; 63848489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 63922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 64022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 64148489980SSeiya Wang clock-names = "main", "dma"; 64248489980SSeiya Wang clock-div = <1>; 64348489980SSeiya Wang #address-cells = <1>; 64448489980SSeiya Wang #size-cells = <0>; 64548489980SSeiya Wang status = "disabled"; 64648489980SSeiya Wang }; 6475d2b897bSChun-Jie Chen 6485d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 6495d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 6505d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 6515d2b897bSChun-Jie Chen #clock-cells = <1>; 6525d2b897bSChun-Jie Chen }; 6535d2b897bSChun-Jie Chen 6545d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 6555d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 6565d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 6575d2b897bSChun-Jie Chen #clock-cells = <1>; 6585d2b897bSChun-Jie Chen }; 6595d2b897bSChun-Jie Chen 6605d2b897bSChun-Jie Chen msdc: clock-controller@11f60000 { 6615d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc"; 6625d2b897bSChun-Jie Chen reg = <0 0x11f60000 0 0x1000>; 6635d2b897bSChun-Jie Chen #clock-cells = <1>; 6645d2b897bSChun-Jie Chen }; 6655d2b897bSChun-Jie Chen 6665d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 6675d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 6685d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 6695d2b897bSChun-Jie Chen #clock-cells = <1>; 6705d2b897bSChun-Jie Chen }; 6715d2b897bSChun-Jie Chen 6725d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 6735d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 6745d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 6755d2b897bSChun-Jie Chen #clock-cells = <1>; 6765d2b897bSChun-Jie Chen }; 6775d2b897bSChun-Jie Chen 6785d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 6795d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 6805d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 6815d2b897bSChun-Jie Chen #clock-cells = <1>; 6825d2b897bSChun-Jie Chen }; 6835d2b897bSChun-Jie Chen 6845d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 6855d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 6865d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 6875d2b897bSChun-Jie Chen #clock-cells = <1>; 6885d2b897bSChun-Jie Chen }; 6895d2b897bSChun-Jie Chen 6905d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 6915d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 6925d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 6935d2b897bSChun-Jie Chen #clock-cells = <1>; 6945d2b897bSChun-Jie Chen }; 6955d2b897bSChun-Jie Chen 6965d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 6975d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 6985d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 6995d2b897bSChun-Jie Chen #clock-cells = <1>; 7005d2b897bSChun-Jie Chen }; 7015d2b897bSChun-Jie Chen 7025d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 7035d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 7045d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 7055d2b897bSChun-Jie Chen #clock-cells = <1>; 7065d2b897bSChun-Jie Chen }; 7075d2b897bSChun-Jie Chen 7085d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 7095d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 7105d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 7115d2b897bSChun-Jie Chen #clock-cells = <1>; 7125d2b897bSChun-Jie Chen }; 7135d2b897bSChun-Jie Chen 7145d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 7155d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 7165d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 7175d2b897bSChun-Jie Chen #clock-cells = <1>; 7185d2b897bSChun-Jie Chen }; 7195d2b897bSChun-Jie Chen 7205d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 7215d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 7225d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 7235d2b897bSChun-Jie Chen #clock-cells = <1>; 7245d2b897bSChun-Jie Chen }; 7255d2b897bSChun-Jie Chen 7265d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 7275d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 7285d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 7295d2b897bSChun-Jie Chen #clock-cells = <1>; 7305d2b897bSChun-Jie Chen }; 7315d2b897bSChun-Jie Chen 7325d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 7335d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 7345d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 7355d2b897bSChun-Jie Chen #clock-cells = <1>; 7365d2b897bSChun-Jie Chen }; 7375d2b897bSChun-Jie Chen 7385d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 7395d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 7405d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 7415d2b897bSChun-Jie Chen #clock-cells = <1>; 7425d2b897bSChun-Jie Chen }; 74348489980SSeiya Wang }; 74448489980SSeiya Wang}; 745