148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 848489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 1048489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 1148489980SSeiya Wang 1248489980SSeiya Wang/ { 1348489980SSeiya Wang compatible = "mediatek,mt8192"; 1448489980SSeiya Wang interrupt-parent = <&gic>; 1548489980SSeiya Wang #address-cells = <2>; 1648489980SSeiya Wang #size-cells = <2>; 1748489980SSeiya Wang 1848489980SSeiya Wang clk26m: oscillator0 { 1948489980SSeiya Wang compatible = "fixed-clock"; 2048489980SSeiya Wang #clock-cells = <0>; 2148489980SSeiya Wang clock-frequency = <26000000>; 2248489980SSeiya Wang clock-output-names = "clk26m"; 2348489980SSeiya Wang }; 2448489980SSeiya Wang 2548489980SSeiya Wang clk32k: oscillator1 { 2648489980SSeiya Wang compatible = "fixed-clock"; 2748489980SSeiya Wang #clock-cells = <0>; 2848489980SSeiya Wang clock-frequency = <32768>; 2948489980SSeiya Wang clock-output-names = "clk32k"; 3048489980SSeiya Wang }; 3148489980SSeiya Wang 3248489980SSeiya Wang cpus { 3348489980SSeiya Wang #address-cells = <1>; 3448489980SSeiya Wang #size-cells = <0>; 3548489980SSeiya Wang 3648489980SSeiya Wang cpu0: cpu@0 { 3748489980SSeiya Wang device_type = "cpu"; 3848489980SSeiya Wang compatible = "arm,cortex-a55"; 3948489980SSeiya Wang reg = <0x000>; 4048489980SSeiya Wang enable-method = "psci"; 4148489980SSeiya Wang clock-frequency = <1701000000>; 4248489980SSeiya Wang next-level-cache = <&l2_0>; 4348489980SSeiya Wang capacity-dmips-mhz = <530>; 4448489980SSeiya Wang }; 4548489980SSeiya Wang 4648489980SSeiya Wang cpu1: cpu@100 { 4748489980SSeiya Wang device_type = "cpu"; 4848489980SSeiya Wang compatible = "arm,cortex-a55"; 4948489980SSeiya Wang reg = <0x100>; 5048489980SSeiya Wang enable-method = "psci"; 5148489980SSeiya Wang clock-frequency = <1701000000>; 5248489980SSeiya Wang next-level-cache = <&l2_0>; 5348489980SSeiya Wang capacity-dmips-mhz = <530>; 5448489980SSeiya Wang }; 5548489980SSeiya Wang 5648489980SSeiya Wang cpu2: cpu@200 { 5748489980SSeiya Wang device_type = "cpu"; 5848489980SSeiya Wang compatible = "arm,cortex-a55"; 5948489980SSeiya Wang reg = <0x200>; 6048489980SSeiya Wang enable-method = "psci"; 6148489980SSeiya Wang clock-frequency = <1701000000>; 6248489980SSeiya Wang next-level-cache = <&l2_0>; 6348489980SSeiya Wang capacity-dmips-mhz = <530>; 6448489980SSeiya Wang }; 6548489980SSeiya Wang 6648489980SSeiya Wang cpu3: cpu@300 { 6748489980SSeiya Wang device_type = "cpu"; 6848489980SSeiya Wang compatible = "arm,cortex-a55"; 6948489980SSeiya Wang reg = <0x300>; 7048489980SSeiya Wang enable-method = "psci"; 7148489980SSeiya Wang clock-frequency = <1701000000>; 7248489980SSeiya Wang next-level-cache = <&l2_0>; 7348489980SSeiya Wang capacity-dmips-mhz = <530>; 7448489980SSeiya Wang }; 7548489980SSeiya Wang 7648489980SSeiya Wang cpu4: cpu@400 { 7748489980SSeiya Wang device_type = "cpu"; 7848489980SSeiya Wang compatible = "arm,cortex-a76"; 7948489980SSeiya Wang reg = <0x400>; 8048489980SSeiya Wang enable-method = "psci"; 8148489980SSeiya Wang clock-frequency = <2171000000>; 8248489980SSeiya Wang next-level-cache = <&l2_1>; 8348489980SSeiya Wang capacity-dmips-mhz = <1024>; 8448489980SSeiya Wang }; 8548489980SSeiya Wang 8648489980SSeiya Wang cpu5: cpu@500 { 8748489980SSeiya Wang device_type = "cpu"; 8848489980SSeiya Wang compatible = "arm,cortex-a76"; 8948489980SSeiya Wang reg = <0x500>; 9048489980SSeiya Wang enable-method = "psci"; 9148489980SSeiya Wang clock-frequency = <2171000000>; 9248489980SSeiya Wang next-level-cache = <&l2_1>; 9348489980SSeiya Wang capacity-dmips-mhz = <1024>; 9448489980SSeiya Wang }; 9548489980SSeiya Wang 9648489980SSeiya Wang cpu6: cpu@600 { 9748489980SSeiya Wang device_type = "cpu"; 9848489980SSeiya Wang compatible = "arm,cortex-a76"; 9948489980SSeiya Wang reg = <0x600>; 10048489980SSeiya Wang enable-method = "psci"; 10148489980SSeiya Wang clock-frequency = <2171000000>; 10248489980SSeiya Wang next-level-cache = <&l2_1>; 10348489980SSeiya Wang capacity-dmips-mhz = <1024>; 10448489980SSeiya Wang }; 10548489980SSeiya Wang 10648489980SSeiya Wang cpu7: cpu@700 { 10748489980SSeiya Wang device_type = "cpu"; 10848489980SSeiya Wang compatible = "arm,cortex-a76"; 10948489980SSeiya Wang reg = <0x700>; 11048489980SSeiya Wang enable-method = "psci"; 11148489980SSeiya Wang clock-frequency = <2171000000>; 11248489980SSeiya Wang next-level-cache = <&l2_1>; 11348489980SSeiya Wang capacity-dmips-mhz = <1024>; 11448489980SSeiya Wang }; 11548489980SSeiya Wang 11648489980SSeiya Wang cpu-map { 11748489980SSeiya Wang cluster0 { 11848489980SSeiya Wang core0 { 11948489980SSeiya Wang cpu = <&cpu0>; 12048489980SSeiya Wang }; 12148489980SSeiya Wang core1 { 12248489980SSeiya Wang cpu = <&cpu1>; 12348489980SSeiya Wang }; 12448489980SSeiya Wang core2 { 12548489980SSeiya Wang cpu = <&cpu2>; 12648489980SSeiya Wang }; 12748489980SSeiya Wang core3 { 12848489980SSeiya Wang cpu = <&cpu3>; 12948489980SSeiya Wang }; 13048489980SSeiya Wang }; 13148489980SSeiya Wang 13248489980SSeiya Wang cluster1 { 13348489980SSeiya Wang core0 { 13448489980SSeiya Wang cpu = <&cpu4>; 13548489980SSeiya Wang }; 13648489980SSeiya Wang core1 { 13748489980SSeiya Wang cpu = <&cpu5>; 13848489980SSeiya Wang }; 13948489980SSeiya Wang core2 { 14048489980SSeiya Wang cpu = <&cpu6>; 14148489980SSeiya Wang }; 14248489980SSeiya Wang core3 { 14348489980SSeiya Wang cpu = <&cpu7>; 14448489980SSeiya Wang }; 14548489980SSeiya Wang }; 14648489980SSeiya Wang }; 14748489980SSeiya Wang 14848489980SSeiya Wang l2_0: l2-cache0 { 14948489980SSeiya Wang compatible = "cache"; 15048489980SSeiya Wang next-level-cache = <&l3_0>; 15148489980SSeiya Wang }; 15248489980SSeiya Wang 15348489980SSeiya Wang l2_1: l2-cache1 { 15448489980SSeiya Wang compatible = "cache"; 15548489980SSeiya Wang next-level-cache = <&l3_0>; 15648489980SSeiya Wang }; 15748489980SSeiya Wang 15848489980SSeiya Wang l3_0: l3-cache { 15948489980SSeiya Wang compatible = "cache"; 16048489980SSeiya Wang }; 16148489980SSeiya Wang }; 16248489980SSeiya Wang 16348489980SSeiya Wang pmu-a55 { 16448489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 16548489980SSeiya Wang interrupt-parent = <&gic>; 16648489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 16748489980SSeiya Wang }; 16848489980SSeiya Wang 16948489980SSeiya Wang pmu-a76 { 17048489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 17148489980SSeiya Wang interrupt-parent = <&gic>; 17248489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 17348489980SSeiya Wang }; 17448489980SSeiya Wang 17548489980SSeiya Wang psci { 17648489980SSeiya Wang compatible = "arm,psci-1.0"; 17748489980SSeiya Wang method = "smc"; 17848489980SSeiya Wang }; 17948489980SSeiya Wang 18048489980SSeiya Wang timer: timer { 18148489980SSeiya Wang compatible = "arm,armv8-timer"; 18248489980SSeiya Wang interrupt-parent = <&gic>; 18348489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 18448489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 18548489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 18648489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 18748489980SSeiya Wang clock-frequency = <13000000>; 18848489980SSeiya Wang }; 18948489980SSeiya Wang 19048489980SSeiya Wang soc { 19148489980SSeiya Wang #address-cells = <2>; 19248489980SSeiya Wang #size-cells = <2>; 19348489980SSeiya Wang compatible = "simple-bus"; 19448489980SSeiya Wang ranges; 19548489980SSeiya Wang 19648489980SSeiya Wang gic: interrupt-controller@c000000 { 19748489980SSeiya Wang compatible = "arm,gic-v3"; 19848489980SSeiya Wang #interrupt-cells = <4>; 19948489980SSeiya Wang #redistributor-regions = <1>; 20048489980SSeiya Wang interrupt-parent = <&gic>; 20148489980SSeiya Wang interrupt-controller; 20248489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 20348489980SSeiya Wang <0 0x0c040000 0 0x200000>; 20448489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 20548489980SSeiya Wang 20648489980SSeiya Wang ppi-partitions { 20748489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 20848489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 20948489980SSeiya Wang }; 21048489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 21148489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 21248489980SSeiya Wang }; 21348489980SSeiya Wang }; 21448489980SSeiya Wang }; 21548489980SSeiya Wang 21648489980SSeiya Wang pio: pinctrl@10005000 { 21748489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 21848489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 21948489980SSeiya Wang <0 0x11c20000 0 0x1000>, 22048489980SSeiya Wang <0 0x11d10000 0 0x1000>, 22148489980SSeiya Wang <0 0x11d30000 0 0x1000>, 22248489980SSeiya Wang <0 0x11d40000 0 0x1000>, 22348489980SSeiya Wang <0 0x11e20000 0 0x1000>, 22448489980SSeiya Wang <0 0x11e70000 0 0x1000>, 22548489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 22648489980SSeiya Wang <0 0x11f20000 0 0x1000>, 22748489980SSeiya Wang <0 0x11f30000 0 0x1000>, 22848489980SSeiya Wang <0 0x1000b000 0 0x1000>; 22948489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 23048489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 23148489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 23248489980SSeiya Wang "iocfg_tl", "eint"; 23348489980SSeiya Wang gpio-controller; 23448489980SSeiya Wang #gpio-cells = <2>; 23548489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 23648489980SSeiya Wang interrupt-controller; 23748489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 23848489980SSeiya Wang #interrupt-cells = <2>; 23948489980SSeiya Wang }; 24048489980SSeiya Wang 24148489980SSeiya Wang systimer: timer@10017000 { 24248489980SSeiya Wang compatible = "mediatek,mt8192-timer", 24348489980SSeiya Wang "mediatek,mt6765-timer"; 24448489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 24548489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 24648489980SSeiya Wang clocks = <&clk26m>; 24748489980SSeiya Wang clock-names = "clk13m"; 24848489980SSeiya Wang }; 24948489980SSeiya Wang 25048489980SSeiya Wang uart0: serial@11002000 { 25148489980SSeiya Wang compatible = "mediatek,mt8192-uart", 25248489980SSeiya Wang "mediatek,mt6577-uart"; 25348489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 25448489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 25548489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 25648489980SSeiya Wang clock-names = "baud", "bus"; 25748489980SSeiya Wang status = "disabled"; 25848489980SSeiya Wang }; 25948489980SSeiya Wang 26048489980SSeiya Wang uart1: serial@11003000 { 26148489980SSeiya Wang compatible = "mediatek,mt8192-uart", 26248489980SSeiya Wang "mediatek,mt6577-uart"; 26348489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 26448489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 26548489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 26648489980SSeiya Wang clock-names = "baud", "bus"; 26748489980SSeiya Wang status = "disabled"; 26848489980SSeiya Wang }; 26948489980SSeiya Wang 27048489980SSeiya Wang spi0: spi@1100a000 { 27148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 27248489980SSeiya Wang "mediatek,mt6765-spi"; 27348489980SSeiya Wang #address-cells = <1>; 27448489980SSeiya Wang #size-cells = <0>; 27548489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 27648489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 27748489980SSeiya Wang clocks = <&clk26m>, 27848489980SSeiya Wang <&clk26m>, 27948489980SSeiya Wang <&clk26m>; 28048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 28148489980SSeiya Wang status = "disabled"; 28248489980SSeiya Wang }; 28348489980SSeiya Wang 28448489980SSeiya Wang spi1: spi@11010000 { 28548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 28648489980SSeiya Wang "mediatek,mt6765-spi"; 28748489980SSeiya Wang #address-cells = <1>; 28848489980SSeiya Wang #size-cells = <0>; 28948489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 29048489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 29148489980SSeiya Wang clocks = <&clk26m>, 29248489980SSeiya Wang <&clk26m>, 29348489980SSeiya Wang <&clk26m>; 29448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 29548489980SSeiya Wang status = "disabled"; 29648489980SSeiya Wang }; 29748489980SSeiya Wang 29848489980SSeiya Wang spi2: spi@11012000 { 29948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 30048489980SSeiya Wang "mediatek,mt6765-spi"; 30148489980SSeiya Wang #address-cells = <1>; 30248489980SSeiya Wang #size-cells = <0>; 30348489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 30448489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 30548489980SSeiya Wang clocks = <&clk26m>, 30648489980SSeiya Wang <&clk26m>, 30748489980SSeiya Wang <&clk26m>; 30848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 30948489980SSeiya Wang status = "disabled"; 31048489980SSeiya Wang }; 31148489980SSeiya Wang 31248489980SSeiya Wang spi3: spi@11013000 { 31348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 31448489980SSeiya Wang "mediatek,mt6765-spi"; 31548489980SSeiya Wang #address-cells = <1>; 31648489980SSeiya Wang #size-cells = <0>; 31748489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 31848489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 31948489980SSeiya Wang clocks = <&clk26m>, 32048489980SSeiya Wang <&clk26m>, 32148489980SSeiya Wang <&clk26m>; 32248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 32348489980SSeiya Wang status = "disabled"; 32448489980SSeiya Wang }; 32548489980SSeiya Wang 32648489980SSeiya Wang spi4: spi@11018000 { 32748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 32848489980SSeiya Wang "mediatek,mt6765-spi"; 32948489980SSeiya Wang #address-cells = <1>; 33048489980SSeiya Wang #size-cells = <0>; 33148489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 33248489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 33348489980SSeiya Wang clocks = <&clk26m>, 33448489980SSeiya Wang <&clk26m>, 33548489980SSeiya Wang <&clk26m>; 33648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 33748489980SSeiya Wang status = "disabled"; 33848489980SSeiya Wang }; 33948489980SSeiya Wang 34048489980SSeiya Wang spi5: spi@11019000 { 34148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 34248489980SSeiya Wang "mediatek,mt6765-spi"; 34348489980SSeiya Wang #address-cells = <1>; 34448489980SSeiya Wang #size-cells = <0>; 34548489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 34648489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 34748489980SSeiya Wang clocks = <&clk26m>, 34848489980SSeiya Wang <&clk26m>, 34948489980SSeiya Wang <&clk26m>; 35048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 35148489980SSeiya Wang status = "disabled"; 35248489980SSeiya Wang }; 35348489980SSeiya Wang 35448489980SSeiya Wang spi6: spi@1101d000 { 35548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 35648489980SSeiya Wang "mediatek,mt6765-spi"; 35748489980SSeiya Wang #address-cells = <1>; 35848489980SSeiya Wang #size-cells = <0>; 35948489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 36048489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 36148489980SSeiya Wang clocks = <&clk26m>, 36248489980SSeiya Wang <&clk26m>, 36348489980SSeiya Wang <&clk26m>; 36448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 36548489980SSeiya Wang status = "disabled"; 36648489980SSeiya Wang }; 36748489980SSeiya Wang 36848489980SSeiya Wang spi7: spi@1101e000 { 36948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 37048489980SSeiya Wang "mediatek,mt6765-spi"; 37148489980SSeiya Wang #address-cells = <1>; 37248489980SSeiya Wang #size-cells = <0>; 37348489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 37448489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 37548489980SSeiya Wang clocks = <&clk26m>, 37648489980SSeiya Wang <&clk26m>, 37748489980SSeiya Wang <&clk26m>; 37848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 37948489980SSeiya Wang status = "disabled"; 38048489980SSeiya Wang }; 38148489980SSeiya Wang 382*d0a197a0Sbayi cheng nor_flash: spi@11234000 { 383*d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 384*d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 385*d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 386*d0a197a0Sbayi cheng clocks = <&clk26m>, 387*d0a197a0Sbayi cheng <&clk26m>, 388*d0a197a0Sbayi cheng <&clk26m>; 389*d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 390*d0a197a0Sbayi cheng #address-cells = <1>; 391*d0a197a0Sbayi cheng #size-cells = <0>; 392*d0a197a0Sbayi cheng status = "disable"; 393*d0a197a0Sbayi cheng }; 394*d0a197a0Sbayi cheng 39548489980SSeiya Wang i2c3: i2c3@11cb0000 { 39648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 39748489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 39848489980SSeiya Wang <0 0x10217300 0 0x80>; 39948489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 40048489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 40148489980SSeiya Wang clock-names = "main", "dma"; 40248489980SSeiya Wang clock-div = <1>; 40348489980SSeiya Wang #address-cells = <1>; 40448489980SSeiya Wang #size-cells = <0>; 40548489980SSeiya Wang status = "disabled"; 40648489980SSeiya Wang }; 40748489980SSeiya Wang 40848489980SSeiya Wang i2c7: i2c7@11d00000 { 40948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 41048489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 41148489980SSeiya Wang <0 0x10217600 0 0x180>; 41248489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 41348489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 41448489980SSeiya Wang clock-names = "main", "dma"; 41548489980SSeiya Wang clock-div = <1>; 41648489980SSeiya Wang #address-cells = <1>; 41748489980SSeiya Wang #size-cells = <0>; 41848489980SSeiya Wang status = "disabled"; 41948489980SSeiya Wang }; 42048489980SSeiya Wang 42148489980SSeiya Wang i2c8: i2c8@11d01000 { 42248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 42348489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 42448489980SSeiya Wang <0 0x10217780 0 0x180>; 42548489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 42648489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 42748489980SSeiya Wang clock-names = "main", "dma"; 42848489980SSeiya Wang clock-div = <1>; 42948489980SSeiya Wang #address-cells = <1>; 43048489980SSeiya Wang #size-cells = <0>; 43148489980SSeiya Wang status = "disabled"; 43248489980SSeiya Wang }; 43348489980SSeiya Wang 43448489980SSeiya Wang i2c9: i2c9@11d02000 { 43548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 43648489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 43748489980SSeiya Wang <0 0x10217900 0 0x180>; 43848489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 43948489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 44048489980SSeiya Wang clock-names = "main", "dma"; 44148489980SSeiya Wang clock-div = <1>; 44248489980SSeiya Wang #address-cells = <1>; 44348489980SSeiya Wang #size-cells = <0>; 44448489980SSeiya Wang status = "disabled"; 44548489980SSeiya Wang }; 44648489980SSeiya Wang 44748489980SSeiya Wang i2c1: i2c1@11d20000 { 44848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 44948489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 45048489980SSeiya Wang <0 0x10217100 0 0x80>; 45148489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 45248489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 45348489980SSeiya Wang clock-names = "main", "dma"; 45448489980SSeiya Wang clock-div = <1>; 45548489980SSeiya Wang #address-cells = <1>; 45648489980SSeiya Wang #size-cells = <0>; 45748489980SSeiya Wang status = "disabled"; 45848489980SSeiya Wang }; 45948489980SSeiya Wang 46048489980SSeiya Wang i2c2: i2c2@11d21000 { 46148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 46248489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 46348489980SSeiya Wang <0 0x10217180 0 0x180>; 46448489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 46548489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 46648489980SSeiya Wang clock-names = "main", "dma"; 46748489980SSeiya Wang clock-div = <1>; 46848489980SSeiya Wang #address-cells = <1>; 46948489980SSeiya Wang #size-cells = <0>; 47048489980SSeiya Wang status = "disabled"; 47148489980SSeiya Wang }; 47248489980SSeiya Wang 47348489980SSeiya Wang i2c4: i2c4@11d22000 { 47448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 47548489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 47648489980SSeiya Wang <0 0x10217380 0 0x180>; 47748489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 47848489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 47948489980SSeiya Wang clock-names = "main", "dma"; 48048489980SSeiya Wang clock-div = <1>; 48148489980SSeiya Wang #address-cells = <1>; 48248489980SSeiya Wang #size-cells = <0>; 48348489980SSeiya Wang status = "disabled"; 48448489980SSeiya Wang }; 48548489980SSeiya Wang 48648489980SSeiya Wang i2c5: i2c5@11e00000 { 48748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 48848489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 48948489980SSeiya Wang <0 0x10217500 0 0x80>; 49048489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 49148489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 49248489980SSeiya Wang clock-names = "main", "dma"; 49348489980SSeiya Wang clock-div = <1>; 49448489980SSeiya Wang #address-cells = <1>; 49548489980SSeiya Wang #size-cells = <0>; 49648489980SSeiya Wang status = "disabled"; 49748489980SSeiya Wang }; 49848489980SSeiya Wang 49948489980SSeiya Wang i2c0: i2c0@11f00000 { 50048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 50148489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 50248489980SSeiya Wang <0 0x10217080 0 0x80>; 50348489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 50448489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 50548489980SSeiya Wang clock-names = "main", "dma"; 50648489980SSeiya Wang clock-div = <1>; 50748489980SSeiya Wang #address-cells = <1>; 50848489980SSeiya Wang #size-cells = <0>; 50948489980SSeiya Wang status = "disabled"; 51048489980SSeiya Wang }; 51148489980SSeiya Wang 51248489980SSeiya Wang i2c6: i2c6@11f01000 { 51348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 51448489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 51548489980SSeiya Wang <0 0x10217580 0 0x80>; 51648489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 51748489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 51848489980SSeiya Wang clock-names = "main", "dma"; 51948489980SSeiya Wang clock-div = <1>; 52048489980SSeiya Wang #address-cells = <1>; 52148489980SSeiya Wang #size-cells = <0>; 52248489980SSeiya Wang status = "disabled"; 52348489980SSeiya Wang }; 52448489980SSeiya Wang }; 52548489980SSeiya Wang}; 526