148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 9b4b75bacSAllen-KH Cheng#include <dt-bindings/gce/mt8192-gce.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1148489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 124a65b0f1SAllen-KH Cheng#include <dt-bindings/memory/mt8192-larb-port.h> 1348489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h> 15994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 167d355378SAllen-KH Cheng#include <dt-bindings/reset/mt8192-resets.h> 1748489980SSeiya Wang 1848489980SSeiya Wang/ { 1948489980SSeiya Wang compatible = "mediatek,mt8192"; 2048489980SSeiya Wang interrupt-parent = <&gic>; 2148489980SSeiya Wang #address-cells = <2>; 2248489980SSeiya Wang #size-cells = <2>; 2348489980SSeiya Wang 24b4b75bacSAllen-KH Cheng aliases { 25b4b75bacSAllen-KH Cheng ovl0 = &ovl0; 26b4b75bacSAllen-KH Cheng ovl-2l0 = &ovl_2l0; 27b4b75bacSAllen-KH Cheng ovl-2l2 = &ovl_2l2; 28b4b75bacSAllen-KH Cheng rdma0 = &rdma0; 29b4b75bacSAllen-KH Cheng rdma4 = &rdma4; 30b4b75bacSAllen-KH Cheng }; 31b4b75bacSAllen-KH Cheng 3248489980SSeiya Wang clk26m: oscillator0 { 3348489980SSeiya Wang compatible = "fixed-clock"; 3448489980SSeiya Wang #clock-cells = <0>; 3548489980SSeiya Wang clock-frequency = <26000000>; 3648489980SSeiya Wang clock-output-names = "clk26m"; 3748489980SSeiya Wang }; 3848489980SSeiya Wang 3948489980SSeiya Wang clk32k: oscillator1 { 4048489980SSeiya Wang compatible = "fixed-clock"; 4148489980SSeiya Wang #clock-cells = <0>; 4248489980SSeiya Wang clock-frequency = <32768>; 4348489980SSeiya Wang clock-output-names = "clk32k"; 4448489980SSeiya Wang }; 4548489980SSeiya Wang 4648489980SSeiya Wang cpus { 4748489980SSeiya Wang #address-cells = <1>; 4848489980SSeiya Wang #size-cells = <0>; 4948489980SSeiya Wang 5048489980SSeiya Wang cpu0: cpu@0 { 5148489980SSeiya Wang device_type = "cpu"; 5248489980SSeiya Wang compatible = "arm,cortex-a55"; 5348489980SSeiya Wang reg = <0x000>; 5448489980SSeiya Wang enable-method = "psci"; 5548489980SSeiya Wang clock-frequency = <1701000000>; 56399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 5748489980SSeiya Wang next-level-cache = <&l2_0>; 5848489980SSeiya Wang capacity-dmips-mhz = <530>; 5948489980SSeiya Wang }; 6048489980SSeiya Wang 6148489980SSeiya Wang cpu1: cpu@100 { 6248489980SSeiya Wang device_type = "cpu"; 6348489980SSeiya Wang compatible = "arm,cortex-a55"; 6448489980SSeiya Wang reg = <0x100>; 6548489980SSeiya Wang enable-method = "psci"; 6648489980SSeiya Wang clock-frequency = <1701000000>; 67399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 6848489980SSeiya Wang next-level-cache = <&l2_0>; 6948489980SSeiya Wang capacity-dmips-mhz = <530>; 7048489980SSeiya Wang }; 7148489980SSeiya Wang 7248489980SSeiya Wang cpu2: cpu@200 { 7348489980SSeiya Wang device_type = "cpu"; 7448489980SSeiya Wang compatible = "arm,cortex-a55"; 7548489980SSeiya Wang reg = <0x200>; 7648489980SSeiya Wang enable-method = "psci"; 7748489980SSeiya Wang clock-frequency = <1701000000>; 78399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 7948489980SSeiya Wang next-level-cache = <&l2_0>; 8048489980SSeiya Wang capacity-dmips-mhz = <530>; 8148489980SSeiya Wang }; 8248489980SSeiya Wang 8348489980SSeiya Wang cpu3: cpu@300 { 8448489980SSeiya Wang device_type = "cpu"; 8548489980SSeiya Wang compatible = "arm,cortex-a55"; 8648489980SSeiya Wang reg = <0x300>; 8748489980SSeiya Wang enable-method = "psci"; 8848489980SSeiya Wang clock-frequency = <1701000000>; 89399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 9048489980SSeiya Wang next-level-cache = <&l2_0>; 9148489980SSeiya Wang capacity-dmips-mhz = <530>; 9248489980SSeiya Wang }; 9348489980SSeiya Wang 9448489980SSeiya Wang cpu4: cpu@400 { 9548489980SSeiya Wang device_type = "cpu"; 9648489980SSeiya Wang compatible = "arm,cortex-a76"; 9748489980SSeiya Wang reg = <0x400>; 9848489980SSeiya Wang enable-method = "psci"; 9948489980SSeiya Wang clock-frequency = <2171000000>; 100399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 10148489980SSeiya Wang next-level-cache = <&l2_1>; 10248489980SSeiya Wang capacity-dmips-mhz = <1024>; 10348489980SSeiya Wang }; 10448489980SSeiya Wang 10548489980SSeiya Wang cpu5: cpu@500 { 10648489980SSeiya Wang device_type = "cpu"; 10748489980SSeiya Wang compatible = "arm,cortex-a76"; 10848489980SSeiya Wang reg = <0x500>; 10948489980SSeiya Wang enable-method = "psci"; 11048489980SSeiya Wang clock-frequency = <2171000000>; 111399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 11248489980SSeiya Wang next-level-cache = <&l2_1>; 11348489980SSeiya Wang capacity-dmips-mhz = <1024>; 11448489980SSeiya Wang }; 11548489980SSeiya Wang 11648489980SSeiya Wang cpu6: cpu@600 { 11748489980SSeiya Wang device_type = "cpu"; 11848489980SSeiya Wang compatible = "arm,cortex-a76"; 11948489980SSeiya Wang reg = <0x600>; 12048489980SSeiya Wang enable-method = "psci"; 12148489980SSeiya Wang clock-frequency = <2171000000>; 122399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 12348489980SSeiya Wang next-level-cache = <&l2_1>; 12448489980SSeiya Wang capacity-dmips-mhz = <1024>; 12548489980SSeiya Wang }; 12648489980SSeiya Wang 12748489980SSeiya Wang cpu7: cpu@700 { 12848489980SSeiya Wang device_type = "cpu"; 12948489980SSeiya Wang compatible = "arm,cortex-a76"; 13048489980SSeiya Wang reg = <0x700>; 13148489980SSeiya Wang enable-method = "psci"; 13248489980SSeiya Wang clock-frequency = <2171000000>; 133399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 13448489980SSeiya Wang next-level-cache = <&l2_1>; 13548489980SSeiya Wang capacity-dmips-mhz = <1024>; 13648489980SSeiya Wang }; 13748489980SSeiya Wang 13848489980SSeiya Wang cpu-map { 13948489980SSeiya Wang cluster0 { 14048489980SSeiya Wang core0 { 14148489980SSeiya Wang cpu = <&cpu0>; 14248489980SSeiya Wang }; 14348489980SSeiya Wang core1 { 14448489980SSeiya Wang cpu = <&cpu1>; 14548489980SSeiya Wang }; 14648489980SSeiya Wang core2 { 14748489980SSeiya Wang cpu = <&cpu2>; 14848489980SSeiya Wang }; 14948489980SSeiya Wang core3 { 15048489980SSeiya Wang cpu = <&cpu3>; 15148489980SSeiya Wang }; 15248489980SSeiya Wang }; 15348489980SSeiya Wang 15448489980SSeiya Wang cluster1 { 15548489980SSeiya Wang core0 { 15648489980SSeiya Wang cpu = <&cpu4>; 15748489980SSeiya Wang }; 15848489980SSeiya Wang core1 { 15948489980SSeiya Wang cpu = <&cpu5>; 16048489980SSeiya Wang }; 16148489980SSeiya Wang core2 { 16248489980SSeiya Wang cpu = <&cpu6>; 16348489980SSeiya Wang }; 16448489980SSeiya Wang core3 { 16548489980SSeiya Wang cpu = <&cpu7>; 16648489980SSeiya Wang }; 16748489980SSeiya Wang }; 16848489980SSeiya Wang }; 16948489980SSeiya Wang 17048489980SSeiya Wang l2_0: l2-cache0 { 17148489980SSeiya Wang compatible = "cache"; 172*ce459b1dSPierre Gondois cache-level = <2>; 17348489980SSeiya Wang next-level-cache = <&l3_0>; 17448489980SSeiya Wang }; 17548489980SSeiya Wang 17648489980SSeiya Wang l2_1: l2-cache1 { 17748489980SSeiya Wang compatible = "cache"; 178*ce459b1dSPierre Gondois cache-level = <2>; 17948489980SSeiya Wang next-level-cache = <&l3_0>; 18048489980SSeiya Wang }; 18148489980SSeiya Wang 18248489980SSeiya Wang l3_0: l3-cache { 18348489980SSeiya Wang compatible = "cache"; 184*ce459b1dSPierre Gondois cache-level = <3>; 18548489980SSeiya Wang }; 1869260918dSJames Liao 1879260918dSJames Liao idle-states { 1882e599740SNícolas F. R. A. Prado entry-method = "psci"; 189399e23adSNícolas F. R. A. Prado cpu_sleep_l: cpu-sleep-l { 1909260918dSJames Liao compatible = "arm,idle-state"; 1919260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1929260918dSJames Liao local-timer-stop; 1939260918dSJames Liao entry-latency-us = <55>; 1949260918dSJames Liao exit-latency-us = <140>; 1959260918dSJames Liao min-residency-us = <780>; 1969260918dSJames Liao }; 197399e23adSNícolas F. R. A. Prado cpu_sleep_b: cpu-sleep-b { 1989260918dSJames Liao compatible = "arm,idle-state"; 1999260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 2009260918dSJames Liao local-timer-stop; 2019260918dSJames Liao entry-latency-us = <35>; 2029260918dSJames Liao exit-latency-us = <145>; 2039260918dSJames Liao min-residency-us = <720>; 2049260918dSJames Liao }; 205399e23adSNícolas F. R. A. Prado cluster_sleep_l: cluster-sleep-l { 2069260918dSJames Liao compatible = "arm,idle-state"; 2079260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2089260918dSJames Liao local-timer-stop; 2099260918dSJames Liao entry-latency-us = <60>; 2109260918dSJames Liao exit-latency-us = <155>; 2119260918dSJames Liao min-residency-us = <860>; 2129260918dSJames Liao }; 213399e23adSNícolas F. R. A. Prado cluster_sleep_b: cluster-sleep-b { 2149260918dSJames Liao compatible = "arm,idle-state"; 2159260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2169260918dSJames Liao local-timer-stop; 2179260918dSJames Liao entry-latency-us = <40>; 2189260918dSJames Liao exit-latency-us = <155>; 2199260918dSJames Liao min-residency-us = <780>; 2209260918dSJames Liao }; 2219260918dSJames Liao }; 22248489980SSeiya Wang }; 22348489980SSeiya Wang 22448489980SSeiya Wang pmu-a55 { 22548489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 22648489980SSeiya Wang interrupt-parent = <&gic>; 22748489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 22848489980SSeiya Wang }; 22948489980SSeiya Wang 23048489980SSeiya Wang pmu-a76 { 23148489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 23248489980SSeiya Wang interrupt-parent = <&gic>; 23348489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 23448489980SSeiya Wang }; 23548489980SSeiya Wang 23648489980SSeiya Wang psci { 23748489980SSeiya Wang compatible = "arm,psci-1.0"; 23848489980SSeiya Wang method = "smc"; 23948489980SSeiya Wang }; 24048489980SSeiya Wang 24148489980SSeiya Wang timer: timer { 24248489980SSeiya Wang compatible = "arm,armv8-timer"; 24348489980SSeiya Wang interrupt-parent = <&gic>; 24448489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 24548489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 24648489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 24748489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 24848489980SSeiya Wang clock-frequency = <13000000>; 24948489980SSeiya Wang }; 25048489980SSeiya Wang 25148489980SSeiya Wang soc { 25248489980SSeiya Wang #address-cells = <2>; 25348489980SSeiya Wang #size-cells = <2>; 25448489980SSeiya Wang compatible = "simple-bus"; 25548489980SSeiya Wang ranges; 25648489980SSeiya Wang 25748489980SSeiya Wang gic: interrupt-controller@c000000 { 25848489980SSeiya Wang compatible = "arm,gic-v3"; 25948489980SSeiya Wang #interrupt-cells = <4>; 26048489980SSeiya Wang #redistributor-regions = <1>; 26148489980SSeiya Wang interrupt-parent = <&gic>; 26248489980SSeiya Wang interrupt-controller; 26348489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 26448489980SSeiya Wang <0 0x0c040000 0 0x200000>; 26548489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 26648489980SSeiya Wang 26748489980SSeiya Wang ppi-partitions { 26848489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 26948489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 27048489980SSeiya Wang }; 27148489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 27248489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 27348489980SSeiya Wang }; 27448489980SSeiya Wang }; 27548489980SSeiya Wang }; 27648489980SSeiya Wang 2775d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 2785d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 2795d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 2805d2b897bSChun-Jie Chen #clock-cells = <1>; 2815d2b897bSChun-Jie Chen }; 2825d2b897bSChun-Jie Chen 2835d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 2845d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 2855d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 2865d2b897bSChun-Jie Chen #clock-cells = <1>; 287a30cc07fSRex-BC Chen #reset-cells = <1>; 2885d2b897bSChun-Jie Chen }; 2895d2b897bSChun-Jie Chen 2905d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 2915d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 2925d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 2935d2b897bSChun-Jie Chen #clock-cells = <1>; 2945d2b897bSChun-Jie Chen }; 2955d2b897bSChun-Jie Chen 29648489980SSeiya Wang pio: pinctrl@10005000 { 29748489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 29848489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 29948489980SSeiya Wang <0 0x11c20000 0 0x1000>, 30048489980SSeiya Wang <0 0x11d10000 0 0x1000>, 30148489980SSeiya Wang <0 0x11d30000 0 0x1000>, 30248489980SSeiya Wang <0 0x11d40000 0 0x1000>, 30348489980SSeiya Wang <0 0x11e20000 0 0x1000>, 30448489980SSeiya Wang <0 0x11e70000 0 0x1000>, 30548489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 30648489980SSeiya Wang <0 0x11f20000 0 0x1000>, 30748489980SSeiya Wang <0 0x11f30000 0 0x1000>, 30848489980SSeiya Wang <0 0x1000b000 0 0x1000>; 30948489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 31048489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 31148489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 31248489980SSeiya Wang "iocfg_tl", "eint"; 31348489980SSeiya Wang gpio-controller; 31448489980SSeiya Wang #gpio-cells = <2>; 31548489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 31648489980SSeiya Wang interrupt-controller; 31748489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 31848489980SSeiya Wang #interrupt-cells = <2>; 31948489980SSeiya Wang }; 32048489980SSeiya Wang 321994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 322d3dfd468STinghan Shen compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 323994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 324994a71a3SChun-Jie Chen 325994a71a3SChun-Jie Chen /* System Power Manager */ 326994a71a3SChun-Jie Chen spm: power-controller { 327994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 328994a71a3SChun-Jie Chen #address-cells = <1>; 329994a71a3SChun-Jie Chen #size-cells = <0>; 330994a71a3SChun-Jie Chen #power-domain-cells = <1>; 331994a71a3SChun-Jie Chen 332994a71a3SChun-Jie Chen /* power domain of the SoC */ 333994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 334994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 335994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 336994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 337994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 338994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 339994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 340994a71a3SChun-Jie Chen #power-domain-cells = <0>; 341994a71a3SChun-Jie Chen }; 342994a71a3SChun-Jie Chen 343994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 344994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 345994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 346994a71a3SChun-Jie Chen clock-names = "conn"; 347994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 348994a71a3SChun-Jie Chen #power-domain-cells = <0>; 349994a71a3SChun-Jie Chen }; 350994a71a3SChun-Jie Chen 351994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG0 { 352994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 353994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 354994a71a3SChun-Jie Chen clock-names = "mfg"; 355994a71a3SChun-Jie Chen #address-cells = <1>; 356994a71a3SChun-Jie Chen #size-cells = <0>; 357994a71a3SChun-Jie Chen #power-domain-cells = <1>; 358994a71a3SChun-Jie Chen 359994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG1 { 360994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 361994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 362994a71a3SChun-Jie Chen #address-cells = <1>; 363994a71a3SChun-Jie Chen #size-cells = <0>; 364994a71a3SChun-Jie Chen #power-domain-cells = <1>; 365994a71a3SChun-Jie Chen 366994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 367994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 368994a71a3SChun-Jie Chen #power-domain-cells = <0>; 369994a71a3SChun-Jie Chen }; 370994a71a3SChun-Jie Chen 371994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 372994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 373994a71a3SChun-Jie Chen #power-domain-cells = <0>; 374994a71a3SChun-Jie Chen }; 375994a71a3SChun-Jie Chen 376994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 377994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 378994a71a3SChun-Jie Chen #power-domain-cells = <0>; 379994a71a3SChun-Jie Chen }; 380994a71a3SChun-Jie Chen 381994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 382994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 383994a71a3SChun-Jie Chen #power-domain-cells = <0>; 384994a71a3SChun-Jie Chen }; 385994a71a3SChun-Jie Chen 386994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 387994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 388994a71a3SChun-Jie Chen #power-domain-cells = <0>; 389994a71a3SChun-Jie Chen }; 390994a71a3SChun-Jie Chen }; 391994a71a3SChun-Jie Chen }; 392994a71a3SChun-Jie Chen 393994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 394994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 395994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 396994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 397994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 398994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 399994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 400994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 401994a71a3SChun-Jie Chen "disp-3"; 402994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 403994a71a3SChun-Jie Chen #address-cells = <1>; 404994a71a3SChun-Jie Chen #size-cells = <0>; 405994a71a3SChun-Jie Chen #power-domain-cells = <1>; 406994a71a3SChun-Jie Chen 407994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 408994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 409994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 410994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 411994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 412994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 413994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 414994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 415994a71a3SChun-Jie Chen "ipe-3"; 416994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 417994a71a3SChun-Jie Chen #power-domain-cells = <0>; 418994a71a3SChun-Jie Chen }; 419994a71a3SChun-Jie Chen 420994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 421994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 422994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 423994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 424994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 425994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 426994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 427994a71a3SChun-Jie Chen #power-domain-cells = <0>; 428994a71a3SChun-Jie Chen }; 429994a71a3SChun-Jie Chen 430994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 431994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 432994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 433994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 434994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 435994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 436994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 437994a71a3SChun-Jie Chen #power-domain-cells = <0>; 438994a71a3SChun-Jie Chen }; 439994a71a3SChun-Jie Chen 440994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 441994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 442994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 443994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 444994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 445994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 446994a71a3SChun-Jie Chen #power-domain-cells = <0>; 447994a71a3SChun-Jie Chen }; 448994a71a3SChun-Jie Chen 449994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 450994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 451994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 452994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 453994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 454994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 455994a71a3SChun-Jie Chen #power-domain-cells = <0>; 456994a71a3SChun-Jie Chen }; 457994a71a3SChun-Jie Chen 458994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 459994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 460994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 461994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 462994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 463994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 464994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 465994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 466994a71a3SChun-Jie Chen #address-cells = <1>; 467994a71a3SChun-Jie Chen #size-cells = <0>; 468994a71a3SChun-Jie Chen #power-domain-cells = <1>; 469994a71a3SChun-Jie Chen 470994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 471994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 472994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 473994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 474994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 475994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 476994a71a3SChun-Jie Chen "vdec2-2"; 477994a71a3SChun-Jie Chen #power-domain-cells = <0>; 478994a71a3SChun-Jie Chen }; 479994a71a3SChun-Jie Chen }; 480994a71a3SChun-Jie Chen 481994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 482994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 483994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 484994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 485994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 486994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 487994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 488994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 489994a71a3SChun-Jie Chen "cam-3"; 490994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 491994a71a3SChun-Jie Chen #address-cells = <1>; 492994a71a3SChun-Jie Chen #size-cells = <0>; 493994a71a3SChun-Jie Chen #power-domain-cells = <1>; 494994a71a3SChun-Jie Chen 495994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 496994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 497994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 498994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 499994a71a3SChun-Jie Chen #power-domain-cells = <0>; 500994a71a3SChun-Jie Chen }; 501994a71a3SChun-Jie Chen 502994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 503994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 504994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 505994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 506994a71a3SChun-Jie Chen #power-domain-cells = <0>; 507994a71a3SChun-Jie Chen }; 508994a71a3SChun-Jie Chen 509994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 510994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 511994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 512994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 513994a71a3SChun-Jie Chen #power-domain-cells = <0>; 514994a71a3SChun-Jie Chen }; 515994a71a3SChun-Jie Chen }; 516994a71a3SChun-Jie Chen }; 517994a71a3SChun-Jie Chen }; 518994a71a3SChun-Jie Chen }; 519994a71a3SChun-Jie Chen 520d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 521d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 522d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 523d1986fbdSAllen-KH Cheng #reset-cells = <1>; 524d1986fbdSAllen-KH Cheng }; 525d1986fbdSAllen-KH Cheng 5265d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 5275d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 5285d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 5295d2b897bSChun-Jie Chen #clock-cells = <1>; 5305d2b897bSChun-Jie Chen }; 5315d2b897bSChun-Jie Chen 53248489980SSeiya Wang systimer: timer@10017000 { 53348489980SSeiya Wang compatible = "mediatek,mt8192-timer", 53448489980SSeiya Wang "mediatek,mt6765-timer"; 53548489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 53648489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 537dde3c175SAllen-KH Cheng clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 53848489980SSeiya Wang clock-names = "clk13m"; 53948489980SSeiya Wang }; 54048489980SSeiya Wang 541261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 542261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 543261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 544261691b4SAllen-KH Cheng reg-names = "pwrap"; 545261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 546261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 547261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 548261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 549261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 550261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 551261691b4SAllen-KH Cheng }; 552261691b4SAllen-KH Cheng 553a8bbcf70SAllen-KH Cheng spmi: spmi@10027000 { 554a8bbcf70SAllen-KH Cheng compatible = "mediatek,mt6873-spmi"; 555a8bbcf70SAllen-KH Cheng reg = <0 0x10027000 0 0x000e00>, 556a8bbcf70SAllen-KH Cheng <0 0x10029000 0 0x000100>; 557a8bbcf70SAllen-KH Cheng reg-names = "pmif", "spmimst"; 558a8bbcf70SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 559a8bbcf70SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>, 560a8bbcf70SAllen-KH Cheng <&topckgen CLK_TOP_SPMI_MST_SEL>; 561a8bbcf70SAllen-KH Cheng clock-names = "pmif_sys_ck", 562a8bbcf70SAllen-KH Cheng "pmif_tmr_ck", 563a8bbcf70SAllen-KH Cheng "spmimst_clk_mux"; 564a8bbcf70SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 565a8bbcf70SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 566a8bbcf70SAllen-KH Cheng }; 567a8bbcf70SAllen-KH Cheng 568b4b75bacSAllen-KH Cheng gce: mailbox@10228000 { 569b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-gce"; 570b4b75bacSAllen-KH Cheng reg = <0 0x10228000 0 0x4000>; 571b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 572b4b75bacSAllen-KH Cheng #mbox-cells = <2>; 573b4b75bacSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_GCE>; 574b4b75bacSAllen-KH Cheng clock-names = "gce"; 575b4b75bacSAllen-KH Cheng }; 576b4b75bacSAllen-KH Cheng 5775d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 5785d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 5795d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 5805d2b897bSChun-Jie Chen #clock-cells = <1>; 5815d2b897bSChun-Jie Chen }; 5825d2b897bSChun-Jie Chen 58348489980SSeiya Wang uart0: serial@11002000 { 58448489980SSeiya Wang compatible = "mediatek,mt8192-uart", 58548489980SSeiya Wang "mediatek,mt6577-uart"; 58648489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 58748489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 58873ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 58948489980SSeiya Wang clock-names = "baud", "bus"; 59048489980SSeiya Wang status = "disabled"; 59148489980SSeiya Wang }; 59248489980SSeiya Wang 59348489980SSeiya Wang uart1: serial@11003000 { 59448489980SSeiya Wang compatible = "mediatek,mt8192-uart", 59548489980SSeiya Wang "mediatek,mt6577-uart"; 59648489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 59748489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 59873ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 59948489980SSeiya Wang clock-names = "baud", "bus"; 60048489980SSeiya Wang status = "disabled"; 60148489980SSeiya Wang }; 60248489980SSeiya Wang 6035d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 6045d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 6055d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 6065d2b897bSChun-Jie Chen #clock-cells = <1>; 6075d2b897bSChun-Jie Chen }; 6085d2b897bSChun-Jie Chen 60948489980SSeiya Wang spi0: spi@1100a000 { 61048489980SSeiya Wang compatible = "mediatek,mt8192-spi", 61148489980SSeiya Wang "mediatek,mt6765-spi"; 61248489980SSeiya Wang #address-cells = <1>; 61348489980SSeiya Wang #size-cells = <0>; 61448489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 61548489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 6167f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6177f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6187f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 61948489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 62048489980SSeiya Wang status = "disabled"; 62148489980SSeiya Wang }; 62248489980SSeiya Wang 62318222e05SAllen-KH Cheng pwm0: pwm@1100e000 { 62418222e05SAllen-KH Cheng compatible = "mediatek,mt8183-disp-pwm"; 62518222e05SAllen-KH Cheng reg = <0 0x1100e000 0 0x1000>; 62618222e05SAllen-KH Cheng interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 62718222e05SAllen-KH Cheng #pwm-cells = <2>; 62818222e05SAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 62918222e05SAllen-KH Cheng <&infracfg CLK_INFRA_DISP_PWM>; 63018222e05SAllen-KH Cheng clock-names = "main", "mm"; 63118222e05SAllen-KH Cheng status = "disabled"; 63218222e05SAllen-KH Cheng }; 63318222e05SAllen-KH Cheng 63448489980SSeiya Wang spi1: spi@11010000 { 63548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 63648489980SSeiya Wang "mediatek,mt6765-spi"; 63748489980SSeiya Wang #address-cells = <1>; 63848489980SSeiya Wang #size-cells = <0>; 63948489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 64048489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 6417f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6427f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6437f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 64448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 64548489980SSeiya Wang status = "disabled"; 64648489980SSeiya Wang }; 64748489980SSeiya Wang 64848489980SSeiya Wang spi2: spi@11012000 { 64948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 65048489980SSeiya Wang "mediatek,mt6765-spi"; 65148489980SSeiya Wang #address-cells = <1>; 65248489980SSeiya Wang #size-cells = <0>; 65348489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 65448489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 6557f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6567f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6577f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 65848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 65948489980SSeiya Wang status = "disabled"; 66048489980SSeiya Wang }; 66148489980SSeiya Wang 66248489980SSeiya Wang spi3: spi@11013000 { 66348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 66448489980SSeiya Wang "mediatek,mt6765-spi"; 66548489980SSeiya Wang #address-cells = <1>; 66648489980SSeiya Wang #size-cells = <0>; 66748489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 66848489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 6697f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6707f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6717f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 67248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 67348489980SSeiya Wang status = "disabled"; 67448489980SSeiya Wang }; 67548489980SSeiya Wang 67648489980SSeiya Wang spi4: spi@11018000 { 67748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 67848489980SSeiya Wang "mediatek,mt6765-spi"; 67948489980SSeiya Wang #address-cells = <1>; 68048489980SSeiya Wang #size-cells = <0>; 68148489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 68248489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 6837f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6847f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6857f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 68648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 68748489980SSeiya Wang status = "disabled"; 68848489980SSeiya Wang }; 68948489980SSeiya Wang 69048489980SSeiya Wang spi5: spi@11019000 { 69148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 69248489980SSeiya Wang "mediatek,mt6765-spi"; 69348489980SSeiya Wang #address-cells = <1>; 69448489980SSeiya Wang #size-cells = <0>; 69548489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 69648489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 6977f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6987f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6997f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 70048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 70148489980SSeiya Wang status = "disabled"; 70248489980SSeiya Wang }; 70348489980SSeiya Wang 70448489980SSeiya Wang spi6: spi@1101d000 { 70548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 70648489980SSeiya Wang "mediatek,mt6765-spi"; 70748489980SSeiya Wang #address-cells = <1>; 70848489980SSeiya Wang #size-cells = <0>; 70948489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 71048489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 7117f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7127f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7137f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 71448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 71548489980SSeiya Wang status = "disabled"; 71648489980SSeiya Wang }; 71748489980SSeiya Wang 71848489980SSeiya Wang spi7: spi@1101e000 { 71948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 72048489980SSeiya Wang "mediatek,mt6765-spi"; 72148489980SSeiya Wang #address-cells = <1>; 72248489980SSeiya Wang #size-cells = <0>; 72348489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 72448489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 7257f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7267f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7277f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 72848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 72948489980SSeiya Wang status = "disabled"; 73048489980SSeiya Wang }; 73148489980SSeiya Wang 732c63556ecSAllen-KH Cheng scp: scp@10500000 { 733c63556ecSAllen-KH Cheng compatible = "mediatek,mt8192-scp"; 734c63556ecSAllen-KH Cheng reg = <0 0x10500000 0 0x100000>, 735c7510476SNícolas F. R. A. Prado <0 0x10720000 0 0xe0000>, 736c7510476SNícolas F. R. A. Prado <0 0x10700000 0 0x8000>; 737c7510476SNícolas F. R. A. Prado reg-names = "sram", "cfg", "l1tcm"; 738c63556ecSAllen-KH Cheng interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 739c63556ecSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SCPSYS>; 740c63556ecSAllen-KH Cheng clock-names = "main"; 741c63556ecSAllen-KH Cheng status = "disabled"; 742c63556ecSAllen-KH Cheng }; 743c63556ecSAllen-KH Cheng 744e5aac225SAllen-KH Cheng xhci: usb@11200000 { 745e5aac225SAllen-KH Cheng compatible = "mediatek,mt8192-xhci", 746e5aac225SAllen-KH Cheng "mediatek,mtk-xhci"; 747e5aac225SAllen-KH Cheng reg = <0 0x11200000 0 0x1000>, 748e5aac225SAllen-KH Cheng <0 0x11203e00 0 0x0100>; 749e5aac225SAllen-KH Cheng reg-names = "mac", "ippc"; 750e5aac225SAllen-KH Cheng interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 751e5aac225SAllen-KH Cheng interrupt-names = "host"; 752e5aac225SAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>, 753e5aac225SAllen-KH Cheng <&u3port0 PHY_TYPE_USB3>; 754e5aac225SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 755e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 756e5aac225SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 757e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 758e5aac225SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SSUSB>, 7596210fc2eSNícolas F. R. A. Prado <&apmixedsys CLK_APMIXED_USBPLL>, 7606210fc2eSNícolas F. R. A. Prado <&clk26m>, 7616210fc2eSNícolas F. R. A. Prado <&clk26m>, 7626210fc2eSNícolas F. R. A. Prado <&infracfg CLK_INFRA_SSUSB_XHCI>; 7636210fc2eSNícolas F. R. A. Prado clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 7646210fc2eSNícolas F. R. A. Prado "xhci_ck"; 765e5aac225SAllen-KH Cheng wakeup-source; 766e5aac225SAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 102>; 767e5aac225SAllen-KH Cheng status = "disabled"; 768e5aac225SAllen-KH Cheng }; 769e5aac225SAllen-KH Cheng 7701afd9b62SAllen-KH Cheng audsys: syscon@11210000 { 7711afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audsys", "syscon"; 7721afd9b62SAllen-KH Cheng reg = <0 0x11210000 0 0x2000>; 7731afd9b62SAllen-KH Cheng #clock-cells = <1>; 7741afd9b62SAllen-KH Cheng 7751afd9b62SAllen-KH Cheng afe: mt8192-afe-pcm { 7761afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audio"; 7771afd9b62SAllen-KH Cheng interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 7781afd9b62SAllen-KH Cheng resets = <&watchdog 17>; 7791afd9b62SAllen-KH Cheng reset-names = "audiosys"; 7801afd9b62SAllen-KH Cheng mediatek,apmixedsys = <&apmixedsys>; 7811afd9b62SAllen-KH Cheng mediatek,infracfg = <&infracfg>; 7821afd9b62SAllen-KH Cheng mediatek,topckgen = <&topckgen>; 7831afd9b62SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 7841afd9b62SAllen-KH Cheng clocks = <&audsys CLK_AUD_AFE>, 7851afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC>, 7861afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_PREDIS>, 7871afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC>, 7881afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC>, 7891afd9b62SAllen-KH Cheng <&audsys CLK_AUD_22M>, 7901afd9b62SAllen-KH Cheng <&audsys CLK_AUD_24M>, 7911afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL_TUNER>, 7921afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL2_TUNER>, 7931afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TDM>, 7941afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TML>, 7951afd9b62SAllen-KH Cheng <&audsys CLK_AUD_NLE>, 7961afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_HIRES>, 7971afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES>, 7981afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES_TML>, 7991afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 8001afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC>, 8011afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_PREDIS>, 8021afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_TML>, 8031afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_HIRES>, 8041afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO>, 8051afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO_26M_B>, 8061afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_SEL>, 8071afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 8081afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D4_D4>, 8091afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_1_SEL>, 8101afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1>, 8111afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_2_SEL>, 8121afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2>, 8131afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 8141afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1_D4>, 8151afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 8161afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2_D4>, 8171afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 8181afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 8191afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 8201afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 8211afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 8221afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 8231afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 8241afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 8251afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 8261afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 8271afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV0>, 8281afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV1>, 8291afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV2>, 8301afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV3>, 8311afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV4>, 8321afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIVB>, 8331afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV5>, 8341afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV6>, 8351afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV7>, 8361afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV8>, 8371afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV9>, 8381afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_H_SEL>, 8391afd9b62SAllen-KH Cheng <&clk26m>; 8401afd9b62SAllen-KH Cheng clock-names = "aud_afe_clk", 8411afd9b62SAllen-KH Cheng "aud_dac_clk", 8421afd9b62SAllen-KH Cheng "aud_dac_predis_clk", 8431afd9b62SAllen-KH Cheng "aud_adc_clk", 8441afd9b62SAllen-KH Cheng "aud_adda6_adc_clk", 8451afd9b62SAllen-KH Cheng "aud_apll22m_clk", 8461afd9b62SAllen-KH Cheng "aud_apll24m_clk", 8471afd9b62SAllen-KH Cheng "aud_apll1_tuner_clk", 8481afd9b62SAllen-KH Cheng "aud_apll2_tuner_clk", 8491afd9b62SAllen-KH Cheng "aud_tdm_clk", 8501afd9b62SAllen-KH Cheng "aud_tml_clk", 8511afd9b62SAllen-KH Cheng "aud_nle", 8521afd9b62SAllen-KH Cheng "aud_dac_hires_clk", 8531afd9b62SAllen-KH Cheng "aud_adc_hires_clk", 8541afd9b62SAllen-KH Cheng "aud_adc_hires_tml", 8551afd9b62SAllen-KH Cheng "aud_adda6_adc_hires_clk", 8561afd9b62SAllen-KH Cheng "aud_3rd_dac_clk", 8571afd9b62SAllen-KH Cheng "aud_3rd_dac_predis_clk", 8581afd9b62SAllen-KH Cheng "aud_3rd_dac_tml", 8591afd9b62SAllen-KH Cheng "aud_3rd_dac_hires_clk", 8601afd9b62SAllen-KH Cheng "aud_infra_clk", 8611afd9b62SAllen-KH Cheng "aud_infra_26m_clk", 8621afd9b62SAllen-KH Cheng "top_mux_audio", 8631afd9b62SAllen-KH Cheng "top_mux_audio_int", 8641afd9b62SAllen-KH Cheng "top_mainpll_d4_d4", 8651afd9b62SAllen-KH Cheng "top_mux_aud_1", 8661afd9b62SAllen-KH Cheng "top_apll1_ck", 8671afd9b62SAllen-KH Cheng "top_mux_aud_2", 8681afd9b62SAllen-KH Cheng "top_apll2_ck", 8691afd9b62SAllen-KH Cheng "top_mux_aud_eng1", 8701afd9b62SAllen-KH Cheng "top_apll1_d4", 8711afd9b62SAllen-KH Cheng "top_mux_aud_eng2", 8721afd9b62SAllen-KH Cheng "top_apll2_d4", 8731afd9b62SAllen-KH Cheng "top_i2s0_m_sel", 8741afd9b62SAllen-KH Cheng "top_i2s1_m_sel", 8751afd9b62SAllen-KH Cheng "top_i2s2_m_sel", 8761afd9b62SAllen-KH Cheng "top_i2s3_m_sel", 8771afd9b62SAllen-KH Cheng "top_i2s4_m_sel", 8781afd9b62SAllen-KH Cheng "top_i2s5_m_sel", 8791afd9b62SAllen-KH Cheng "top_i2s6_m_sel", 8801afd9b62SAllen-KH Cheng "top_i2s7_m_sel", 8811afd9b62SAllen-KH Cheng "top_i2s8_m_sel", 8821afd9b62SAllen-KH Cheng "top_i2s9_m_sel", 8831afd9b62SAllen-KH Cheng "top_apll12_div0", 8841afd9b62SAllen-KH Cheng "top_apll12_div1", 8851afd9b62SAllen-KH Cheng "top_apll12_div2", 8861afd9b62SAllen-KH Cheng "top_apll12_div3", 8871afd9b62SAllen-KH Cheng "top_apll12_div4", 8881afd9b62SAllen-KH Cheng "top_apll12_divb", 8891afd9b62SAllen-KH Cheng "top_apll12_div5", 8901afd9b62SAllen-KH Cheng "top_apll12_div6", 8911afd9b62SAllen-KH Cheng "top_apll12_div7", 8921afd9b62SAllen-KH Cheng "top_apll12_div8", 8931afd9b62SAllen-KH Cheng "top_apll12_div9", 8941afd9b62SAllen-KH Cheng "top_mux_audio_h", 8951afd9b62SAllen-KH Cheng "top_clk26m_clk"; 8961afd9b62SAllen-KH Cheng }; 8971afd9b62SAllen-KH Cheng }; 8981afd9b62SAllen-KH Cheng 899e530d080SAllen-KH Cheng pcie: pcie@11230000 { 900e530d080SAllen-KH Cheng compatible = "mediatek,mt8192-pcie"; 901e530d080SAllen-KH Cheng device_type = "pci"; 902e530d080SAllen-KH Cheng reg = <0 0x11230000 0 0x2000>; 903e530d080SAllen-KH Cheng reg-names = "pcie-mac"; 904e530d080SAllen-KH Cheng #address-cells = <3>; 905e530d080SAllen-KH Cheng #size-cells = <2>; 906e530d080SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 907e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_26M>, 908e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_96M>, 909e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_32K>, 910e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_PERI_26M>, 911e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 912e530d080SAllen-KH Cheng clock-names = "pl_250m", "tl_26m", "tl_96m", 913e530d080SAllen-KH Cheng "tl_32k", "peri_26m", "top_133m"; 914e530d080SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 915e530d080SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 916e530d080SAllen-KH Cheng interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 917e530d080SAllen-KH Cheng bus-range = <0x00 0xff>; 918e530d080SAllen-KH Cheng ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 919e530d080SAllen-KH Cheng <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 920e530d080SAllen-KH Cheng #interrupt-cells = <1>; 921e530d080SAllen-KH Cheng interrupt-map-mask = <0 0 0 7>; 922e530d080SAllen-KH Cheng interrupt-map = <0 0 0 1 &pcie_intc0 0>, 923e530d080SAllen-KH Cheng <0 0 0 2 &pcie_intc0 1>, 924e530d080SAllen-KH Cheng <0 0 0 3 &pcie_intc0 2>, 925e530d080SAllen-KH Cheng <0 0 0 4 &pcie_intc0 3>; 926e530d080SAllen-KH Cheng 927e530d080SAllen-KH Cheng pcie_intc0: interrupt-controller { 928e530d080SAllen-KH Cheng interrupt-controller; 929e530d080SAllen-KH Cheng #address-cells = <0>; 930e530d080SAllen-KH Cheng #interrupt-cells = <1>; 931e530d080SAllen-KH Cheng }; 932e530d080SAllen-KH Cheng }; 933e530d080SAllen-KH Cheng 934d0a197a0Sbayi cheng nor_flash: spi@11234000 { 935d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 936d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 937d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 938aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 939aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 940aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 941d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 942aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 943aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 944d0a197a0Sbayi cheng #address-cells = <1>; 945d0a197a0Sbayi cheng #size-cells = <0>; 94627f0eb16SAllen-KH Cheng status = "disabled"; 947d0a197a0Sbayi cheng }; 948d0a197a0Sbayi cheng 9494d50a433SAllen-KH Cheng efuse: efuse@11c10000 { 950fda0541cSChunfeng Yun compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 9514d50a433SAllen-KH Cheng reg = <0 0x11c10000 0 0x1000>; 9524d50a433SAllen-KH Cheng #address-cells = <1>; 9534d50a433SAllen-KH Cheng #size-cells = <1>; 9544d50a433SAllen-KH Cheng 9554d50a433SAllen-KH Cheng lvts_e_data1: data1@1c0 { 9564d50a433SAllen-KH Cheng reg = <0x1c0 0x58>; 9574d50a433SAllen-KH Cheng }; 9584d50a433SAllen-KH Cheng 9594d50a433SAllen-KH Cheng svs_calibration: calib@580 { 9604d50a433SAllen-KH Cheng reg = <0x580 0x68>; 9614d50a433SAllen-KH Cheng }; 9624d50a433SAllen-KH Cheng }; 9634d50a433SAllen-KH Cheng 9647f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 96548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 96648489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 96748489980SSeiya Wang <0 0x10217300 0 0x80>; 96848489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 96922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 97022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 97148489980SSeiya Wang clock-names = "main", "dma"; 97248489980SSeiya Wang clock-div = <1>; 97348489980SSeiya Wang #address-cells = <1>; 97448489980SSeiya Wang #size-cells = <0>; 97548489980SSeiya Wang status = "disabled"; 97648489980SSeiya Wang }; 97748489980SSeiya Wang 9785d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 9795d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 9805d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 9815d2b897bSChun-Jie Chen #clock-cells = <1>; 9825d2b897bSChun-Jie Chen }; 9835d2b897bSChun-Jie Chen 9847f1a9f47SFabien Parent i2c7: i2c@11d00000 { 98548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 98648489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 98748489980SSeiya Wang <0 0x10217600 0 0x180>; 98848489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 98922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 99022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 99148489980SSeiya Wang clock-names = "main", "dma"; 99248489980SSeiya Wang clock-div = <1>; 99348489980SSeiya Wang #address-cells = <1>; 99448489980SSeiya Wang #size-cells = <0>; 99548489980SSeiya Wang status = "disabled"; 99648489980SSeiya Wang }; 99748489980SSeiya Wang 9987f1a9f47SFabien Parent i2c8: i2c@11d01000 { 99948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 100048489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 100148489980SSeiya Wang <0 0x10217780 0 0x180>; 100248489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 100322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 100422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 100548489980SSeiya Wang clock-names = "main", "dma"; 100648489980SSeiya Wang clock-div = <1>; 100748489980SSeiya Wang #address-cells = <1>; 100848489980SSeiya Wang #size-cells = <0>; 100948489980SSeiya Wang status = "disabled"; 101048489980SSeiya Wang }; 101148489980SSeiya Wang 10127f1a9f47SFabien Parent i2c9: i2c@11d02000 { 101348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 101448489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 101548489980SSeiya Wang <0 0x10217900 0 0x180>; 101648489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 101722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 101822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 101948489980SSeiya Wang clock-names = "main", "dma"; 102048489980SSeiya Wang clock-div = <1>; 102148489980SSeiya Wang #address-cells = <1>; 102248489980SSeiya Wang #size-cells = <0>; 102348489980SSeiya Wang status = "disabled"; 102448489980SSeiya Wang }; 102548489980SSeiya Wang 10265d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 10275d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 10285d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 10295d2b897bSChun-Jie Chen #clock-cells = <1>; 10305d2b897bSChun-Jie Chen }; 10315d2b897bSChun-Jie Chen 10327f1a9f47SFabien Parent i2c1: i2c@11d20000 { 103348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 103448489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 103548489980SSeiya Wang <0 0x10217100 0 0x80>; 103648489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 103722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 103822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 103948489980SSeiya Wang clock-names = "main", "dma"; 104048489980SSeiya Wang clock-div = <1>; 104148489980SSeiya Wang #address-cells = <1>; 104248489980SSeiya Wang #size-cells = <0>; 104348489980SSeiya Wang status = "disabled"; 104448489980SSeiya Wang }; 104548489980SSeiya Wang 10467f1a9f47SFabien Parent i2c2: i2c@11d21000 { 104748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 104848489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 104948489980SSeiya Wang <0 0x10217180 0 0x180>; 105048489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 105122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 105222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 105348489980SSeiya Wang clock-names = "main", "dma"; 105448489980SSeiya Wang clock-div = <1>; 105548489980SSeiya Wang #address-cells = <1>; 105648489980SSeiya Wang #size-cells = <0>; 105748489980SSeiya Wang status = "disabled"; 105848489980SSeiya Wang }; 105948489980SSeiya Wang 10607f1a9f47SFabien Parent i2c4: i2c@11d22000 { 106148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 106248489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 106348489980SSeiya Wang <0 0x10217380 0 0x180>; 106448489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 106522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 106622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 106748489980SSeiya Wang clock-names = "main", "dma"; 106848489980SSeiya Wang clock-div = <1>; 106948489980SSeiya Wang #address-cells = <1>; 107048489980SSeiya Wang #size-cells = <0>; 107148489980SSeiya Wang status = "disabled"; 107248489980SSeiya Wang }; 107348489980SSeiya Wang 10745d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 10755d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 10765d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 10775d2b897bSChun-Jie Chen #clock-cells = <1>; 10785d2b897bSChun-Jie Chen }; 10795d2b897bSChun-Jie Chen 10807f1a9f47SFabien Parent i2c5: i2c@11e00000 { 108148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 108248489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 108348489980SSeiya Wang <0 0x10217500 0 0x80>; 108448489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 108522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 108622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 108748489980SSeiya Wang clock-names = "main", "dma"; 108848489980SSeiya Wang clock-div = <1>; 108948489980SSeiya Wang #address-cells = <1>; 109048489980SSeiya Wang #size-cells = <0>; 109148489980SSeiya Wang status = "disabled"; 109248489980SSeiya Wang }; 109348489980SSeiya Wang 10945d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 10955d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 10965d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 10975d2b897bSChun-Jie Chen #clock-cells = <1>; 10985d2b897bSChun-Jie Chen }; 10995d2b897bSChun-Jie Chen 110040de66b8SAllen-KH Cheng u3phy0: t-phy@11e40000 { 110140de66b8SAllen-KH Cheng compatible = "mediatek,mt8192-tphy", 110240de66b8SAllen-KH Cheng "mediatek,generic-tphy-v2"; 110340de66b8SAllen-KH Cheng #address-cells = <1>; 110440de66b8SAllen-KH Cheng #size-cells = <1>; 110540de66b8SAllen-KH Cheng ranges = <0x0 0x0 0x11e40000 0x1000>; 110640de66b8SAllen-KH Cheng 110740de66b8SAllen-KH Cheng u2port0: usb-phy@0 { 110840de66b8SAllen-KH Cheng reg = <0x0 0x700>; 110940de66b8SAllen-KH Cheng clocks = <&clk26m>; 111040de66b8SAllen-KH Cheng clock-names = "ref"; 111140de66b8SAllen-KH Cheng #phy-cells = <1>; 111240de66b8SAllen-KH Cheng }; 111340de66b8SAllen-KH Cheng 111440de66b8SAllen-KH Cheng u3port0: usb-phy@700 { 111540de66b8SAllen-KH Cheng reg = <0x700 0x900>; 111640de66b8SAllen-KH Cheng clocks = <&clk26m>; 111740de66b8SAllen-KH Cheng clock-names = "ref"; 111840de66b8SAllen-KH Cheng #phy-cells = <1>; 111940de66b8SAllen-KH Cheng }; 112040de66b8SAllen-KH Cheng }; 112140de66b8SAllen-KH Cheng 112285c4ec6fSAllen-KH Cheng mipi_tx0: dsi-phy@11e50000 { 112385c4ec6fSAllen-KH Cheng compatible = "mediatek,mt8183-mipi-tx"; 112485c4ec6fSAllen-KH Cheng reg = <0 0x11e50000 0 0x1000>; 112585c4ec6fSAllen-KH Cheng clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 112685c4ec6fSAllen-KH Cheng #clock-cells = <0>; 112785c4ec6fSAllen-KH Cheng #phy-cells = <0>; 112885c4ec6fSAllen-KH Cheng clock-output-names = "mipi_tx0_pll"; 112985c4ec6fSAllen-KH Cheng status = "disabled"; 113085c4ec6fSAllen-KH Cheng }; 113185c4ec6fSAllen-KH Cheng 11327f1a9f47SFabien Parent i2c0: i2c@11f00000 { 113348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 113448489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 113548489980SSeiya Wang <0 0x10217080 0 0x80>; 113648489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 113722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 113822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 113948489980SSeiya Wang clock-names = "main", "dma"; 114048489980SSeiya Wang clock-div = <1>; 114148489980SSeiya Wang #address-cells = <1>; 114248489980SSeiya Wang #size-cells = <0>; 114348489980SSeiya Wang status = "disabled"; 114448489980SSeiya Wang }; 114548489980SSeiya Wang 11467f1a9f47SFabien Parent i2c6: i2c@11f01000 { 114748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 114848489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 114948489980SSeiya Wang <0 0x10217580 0 0x80>; 115048489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 115122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 115222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 115348489980SSeiya Wang clock-names = "main", "dma"; 115448489980SSeiya Wang clock-div = <1>; 115548489980SSeiya Wang #address-cells = <1>; 115648489980SSeiya Wang #size-cells = <0>; 115748489980SSeiya Wang status = "disabled"; 115848489980SSeiya Wang }; 11595d2b897bSChun-Jie Chen 11605d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 11615d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 11625d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 11635d2b897bSChun-Jie Chen #clock-cells = <1>; 11645d2b897bSChun-Jie Chen }; 11655d2b897bSChun-Jie Chen 11665d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 11675d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 11685d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 11695d2b897bSChun-Jie Chen #clock-cells = <1>; 11705d2b897bSChun-Jie Chen }; 11715d2b897bSChun-Jie Chen 1172db61337eSAllen-KH Cheng mmc0: mmc@11f60000 { 1173db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1174db61337eSAllen-KH Cheng reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1175db61337eSAllen-KH Cheng interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1176db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1177db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1178db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1179db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1180db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1181db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1182db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1183db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1184db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1185db61337eSAllen-KH Cheng status = "disabled"; 1186db61337eSAllen-KH Cheng }; 1187db61337eSAllen-KH Cheng 1188db61337eSAllen-KH Cheng mmc1: mmc@11f70000 { 1189db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1190db61337eSAllen-KH Cheng reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1191db61337eSAllen-KH Cheng interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1192db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1193db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1194db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1195db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1196db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1197db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1198db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1199db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1200db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1201db61337eSAllen-KH Cheng status = "disabled"; 12025d2b897bSChun-Jie Chen }; 12035d2b897bSChun-Jie Chen 12045d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 12055d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 12065d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 12075d2b897bSChun-Jie Chen #clock-cells = <1>; 12085d2b897bSChun-Jie Chen }; 12095d2b897bSChun-Jie Chen 12105d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 12115d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 12125d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 12135d2b897bSChun-Jie Chen #clock-cells = <1>; 12147d355378SAllen-KH Cheng #reset-cells = <1>; 1215b4b75bacSAllen-KH Cheng mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1216b4b75bacSAllen-KH Cheng <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1217b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1218b4b75bacSAllen-KH Cheng }; 1219b4b75bacSAllen-KH Cheng 1220b4b75bacSAllen-KH Cheng mutex: mutex@14001000 { 1221b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-mutex"; 1222b4b75bacSAllen-KH Cheng reg = <0 0x14001000 0 0x1000>; 1223b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1224b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1225b4b75bacSAllen-KH Cheng mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1226b4b75bacSAllen-KH Cheng <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1227b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12285d2b897bSChun-Jie Chen }; 12295d2b897bSChun-Jie Chen 12304a65b0f1SAllen-KH Cheng smi_common: smi@14002000 { 12314a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-common"; 12324a65b0f1SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 12334a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 12344a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 12354a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 12364a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>; 12374a65b0f1SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 12384a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12394a65b0f1SAllen-KH Cheng }; 12404a65b0f1SAllen-KH Cheng 12414a65b0f1SAllen-KH Cheng larb0: larb@14003000 { 12424a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12434a65b0f1SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 12444a65b0f1SAllen-KH Cheng mediatek,larb-id = <0>; 12454a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12464a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 12474a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12484a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12494a65b0f1SAllen-KH Cheng }; 12504a65b0f1SAllen-KH Cheng 12514a65b0f1SAllen-KH Cheng larb1: larb@14004000 { 12524a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12534a65b0f1SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 12544a65b0f1SAllen-KH Cheng mediatek,larb-id = <1>; 12554a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12564a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 12574a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12584a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12594a65b0f1SAllen-KH Cheng }; 12604a65b0f1SAllen-KH Cheng 1261b4b75bacSAllen-KH Cheng ovl0: ovl@14005000 { 1262b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl"; 1263b4b75bacSAllen-KH Cheng reg = <0 0x14005000 0 0x1000>; 1264b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1265b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0>; 1266b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1267b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1268b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1269b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1270b4b75bacSAllen-KH Cheng }; 1271b4b75bacSAllen-KH Cheng 1272b4b75bacSAllen-KH Cheng ovl_2l0: ovl@14006000 { 1273b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1274b4b75bacSAllen-KH Cheng reg = <0 0x14006000 0 0x1000>; 1275b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1276b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1277b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1278b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1279b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1280b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1281b4b75bacSAllen-KH Cheng }; 1282b4b75bacSAllen-KH Cheng 1283b4b75bacSAllen-KH Cheng rdma0: rdma@14007000 { 1284b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1285b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1286b4b75bacSAllen-KH Cheng reg = <0 0x14007000 0 0x1000>; 1287b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1288b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1289b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1290b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <5120>; 1291b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1292b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1293b4b75bacSAllen-KH Cheng }; 1294b4b75bacSAllen-KH Cheng 1295b4b75bacSAllen-KH Cheng color0: color@14009000 { 1296b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-color", 1297b4b75bacSAllen-KH Cheng "mediatek,mt8173-disp-color"; 1298b4b75bacSAllen-KH Cheng reg = <0 0x14009000 0 0x1000>; 1299b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1300b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1301b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1302b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1303b4b75bacSAllen-KH Cheng }; 1304b4b75bacSAllen-KH Cheng 1305b4b75bacSAllen-KH Cheng ccorr0: ccorr@1400a000 { 1306b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ccorr"; 1307b4b75bacSAllen-KH Cheng reg = <0 0x1400a000 0 0x1000>; 1308b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1309b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1310b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1311b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1312b4b75bacSAllen-KH Cheng }; 1313b4b75bacSAllen-KH Cheng 1314b4b75bacSAllen-KH Cheng aal0: aal@1400b000 { 1315b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-aal", 1316b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-aal"; 1317b4b75bacSAllen-KH Cheng reg = <0 0x1400b000 0 0x1000>; 1318b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1319b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1320b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_AAL0>; 1321b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1322b4b75bacSAllen-KH Cheng }; 1323b4b75bacSAllen-KH Cheng 1324b4b75bacSAllen-KH Cheng gamma0: gamma@1400c000 { 1325b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-gamma", 1326b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-gamma"; 1327b4b75bacSAllen-KH Cheng reg = <0 0x1400c000 0 0x1000>; 1328b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1329b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1330b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1331b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1332b4b75bacSAllen-KH Cheng }; 1333b4b75bacSAllen-KH Cheng 1334b4b75bacSAllen-KH Cheng postmask0: postmask@1400d000 { 1335b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-postmask"; 1336b4b75bacSAllen-KH Cheng reg = <0 0x1400d000 0 0x1000>; 1337b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1338b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1339b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1340b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1341b4b75bacSAllen-KH Cheng }; 1342b4b75bacSAllen-KH Cheng 1343b4b75bacSAllen-KH Cheng dither0: dither@1400e000 { 1344b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-dither", 1345b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-dither"; 1346b4b75bacSAllen-KH Cheng reg = <0 0x1400e000 0 0x1000>; 1347b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1348b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1349b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1350b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1351b4b75bacSAllen-KH Cheng }; 1352b4b75bacSAllen-KH Cheng 13530708ed7cSAllen-KH Cheng dsi0: dsi@14010000 { 13540708ed7cSAllen-KH Cheng compatible = "mediatek,mt8183-dsi"; 13550708ed7cSAllen-KH Cheng reg = <0 0x14010000 0 0x1000>; 13560708ed7cSAllen-KH Cheng interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 13570708ed7cSAllen-KH Cheng clocks = <&mmsys CLK_MM_DSI0>, 13580708ed7cSAllen-KH Cheng <&mmsys CLK_MM_DSI_DSI0>, 13590708ed7cSAllen-KH Cheng <&mipi_tx0>; 13600708ed7cSAllen-KH Cheng clock-names = "engine", "digital", "hs"; 13610708ed7cSAllen-KH Cheng phys = <&mipi_tx0>; 13620708ed7cSAllen-KH Cheng phy-names = "dphy"; 13630708ed7cSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 13640708ed7cSAllen-KH Cheng resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 13650708ed7cSAllen-KH Cheng status = "disabled"; 13660708ed7cSAllen-KH Cheng 13670708ed7cSAllen-KH Cheng port { 13680708ed7cSAllen-KH Cheng dsi_out: endpoint { }; 13690708ed7cSAllen-KH Cheng }; 13700708ed7cSAllen-KH Cheng }; 13710708ed7cSAllen-KH Cheng 1372b4b75bacSAllen-KH Cheng ovl_2l2: ovl@14014000 { 1373b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1374b4b75bacSAllen-KH Cheng reg = <0 0x14014000 0 0x1000>; 1375b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1376b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1377b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1378b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1379b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1380b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1381b4b75bacSAllen-KH Cheng }; 1382b4b75bacSAllen-KH Cheng 1383b4b75bacSAllen-KH Cheng rdma4: rdma@14015000 { 1384b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1385b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1386b4b75bacSAllen-KH Cheng reg = <0 0x14015000 0 0x1000>; 1387b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1388b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1389b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1390b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1391b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <2048>; 1392b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1393b4b75bacSAllen-KH Cheng }; 1394b4b75bacSAllen-KH Cheng 1395b2edd519SAllen-KH Cheng dpi0: dpi@14016000 { 1396b2edd519SAllen-KH Cheng compatible = "mediatek,mt8192-dpi"; 1397b2edd519SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1398b2edd519SAllen-KH Cheng interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1399b2edd519SAllen-KH Cheng clocks = <&mmsys CLK_MM_DPI_DPI0>, 1400b2edd519SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI0>, 1401b2edd519SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 1402b2edd519SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 1403b2edd519SAllen-KH Cheng status = "disabled"; 1404b2edd519SAllen-KH Cheng }; 1405b2edd519SAllen-KH Cheng 14064a65b0f1SAllen-KH Cheng iommu0: m4u@1401d000 { 14074a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-m4u"; 14084a65b0f1SAllen-KH Cheng reg = <0 0x1401d000 0 0x1000>; 14094a65b0f1SAllen-KH Cheng mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 14104a65b0f1SAllen-KH Cheng <&larb4>, <&larb5>, <&larb7>, 14114a65b0f1SAllen-KH Cheng <&larb9>, <&larb11>, <&larb13>, 14124a65b0f1SAllen-KH Cheng <&larb14>, <&larb16>, <&larb17>, 14134a65b0f1SAllen-KH Cheng <&larb18>, <&larb19>, <&larb20>; 14144a65b0f1SAllen-KH Cheng interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 14154a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 14164a65b0f1SAllen-KH Cheng clock-names = "bclk"; 14174a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14184a65b0f1SAllen-KH Cheng #iommu-cells = <1>; 14194a65b0f1SAllen-KH Cheng }; 14204a65b0f1SAllen-KH Cheng 14215d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 14225d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 14235d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 14245d2b897bSChun-Jie Chen #clock-cells = <1>; 14255d2b897bSChun-Jie Chen }; 14265d2b897bSChun-Jie Chen 14274a65b0f1SAllen-KH Cheng larb9: larb@1502e000 { 14284a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14294a65b0f1SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 14304a65b0f1SAllen-KH Cheng mediatek,larb-id = <9>; 14314a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14324a65b0f1SAllen-KH Cheng clocks = <&imgsys CLK_IMG_LARB9>, 14334a65b0f1SAllen-KH Cheng <&imgsys CLK_IMG_LARB9>; 14344a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14354a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 14364a65b0f1SAllen-KH Cheng }; 14374a65b0f1SAllen-KH Cheng 14385d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 14395d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 14405d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 14415d2b897bSChun-Jie Chen #clock-cells = <1>; 14425d2b897bSChun-Jie Chen }; 14435d2b897bSChun-Jie Chen 14444a65b0f1SAllen-KH Cheng larb11: larb@1582e000 { 14454a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14464a65b0f1SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 14474a65b0f1SAllen-KH Cheng mediatek,larb-id = <11>; 14484a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14494a65b0f1SAllen-KH Cheng clocks = <&imgsys2 CLK_IMG2_LARB11>, 14504a65b0f1SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB11>; 14514a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14524a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 14534a65b0f1SAllen-KH Cheng }; 14544a65b0f1SAllen-KH Cheng 14554a65b0f1SAllen-KH Cheng larb5: larb@1600d000 { 14564a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14574a65b0f1SAllen-KH Cheng reg = <0 0x1600d000 0 0x1000>; 14584a65b0f1SAllen-KH Cheng mediatek,larb-id = <5>; 14594a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14604a65b0f1SAllen-KH Cheng clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 14614a65b0f1SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 14624a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14634a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 14644a65b0f1SAllen-KH Cheng }; 14654a65b0f1SAllen-KH Cheng 14665d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 14675d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 14685d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 14695d2b897bSChun-Jie Chen #clock-cells = <1>; 14705d2b897bSChun-Jie Chen }; 14715d2b897bSChun-Jie Chen 14724a65b0f1SAllen-KH Cheng larb4: larb@1602e000 { 14734a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14744a65b0f1SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 14754a65b0f1SAllen-KH Cheng mediatek,larb-id = <4>; 14764a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14774a65b0f1SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 14784a65b0f1SAllen-KH Cheng <&vdecsys CLK_VDEC_SOC_LARB1>; 14794a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14804a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 14814a65b0f1SAllen-KH Cheng }; 14824a65b0f1SAllen-KH Cheng 14835d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 14845d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 14855d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 14865d2b897bSChun-Jie Chen #clock-cells = <1>; 14875d2b897bSChun-Jie Chen }; 14885d2b897bSChun-Jie Chen 14895d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 14905d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 14915d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 14925d2b897bSChun-Jie Chen #clock-cells = <1>; 14935d2b897bSChun-Jie Chen }; 14945d2b897bSChun-Jie Chen 14954a65b0f1SAllen-KH Cheng larb7: larb@17010000 { 14964a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14974a65b0f1SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 14984a65b0f1SAllen-KH Cheng mediatek,larb-id = <7>; 14994a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15004a65b0f1SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET0_LARB>, 15014a65b0f1SAllen-KH Cheng <&vencsys CLK_VENC_SET1_VENC>; 15024a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15034a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 15044a65b0f1SAllen-KH Cheng }; 15054a65b0f1SAllen-KH Cheng 1506aa8f3711SAllen-KH Cheng vcodec_enc: vcodec@17020000 { 1507aa8f3711SAllen-KH Cheng compatible = "mediatek,mt8192-vcodec-enc"; 1508aa8f3711SAllen-KH Cheng reg = <0 0x17020000 0 0x2000>; 1509aa8f3711SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1510aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REC>, 1511aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1512aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1513aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1514aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1515aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1516aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1517aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1518aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1519aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1520aa8f3711SAllen-KH Cheng interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1521aa8f3711SAllen-KH Cheng mediatek,scp = <&scp>; 1522aa8f3711SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1523aa8f3711SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET1_VENC>; 1524aa8f3711SAllen-KH Cheng clock-names = "venc-set1"; 1525aa8f3711SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1526aa8f3711SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1527aa8f3711SAllen-KH Cheng }; 1528aa8f3711SAllen-KH Cheng 15295d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 15305d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 15315d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 15325d2b897bSChun-Jie Chen #clock-cells = <1>; 15335d2b897bSChun-Jie Chen }; 15345d2b897bSChun-Jie Chen 15354a65b0f1SAllen-KH Cheng larb13: larb@1a001000 { 15364a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15374a65b0f1SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 15384a65b0f1SAllen-KH Cheng mediatek,larb-id = <13>; 15394a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15404a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 15414a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB13>; 15424a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15434a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 15444a65b0f1SAllen-KH Cheng }; 15454a65b0f1SAllen-KH Cheng 15464a65b0f1SAllen-KH Cheng larb14: larb@1a002000 { 15474a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15484a65b0f1SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 15494a65b0f1SAllen-KH Cheng mediatek,larb-id = <14>; 15504a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15514a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 15524a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB14>; 15534a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15544a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 15554a65b0f1SAllen-KH Cheng }; 15564a65b0f1SAllen-KH Cheng 15574a65b0f1SAllen-KH Cheng larb16: larb@1a00f000 { 15584a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15594a65b0f1SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 15604a65b0f1SAllen-KH Cheng mediatek,larb-id = <16>; 15614a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15624a65b0f1SAllen-KH Cheng clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 15634a65b0f1SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX>; 15644a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15654a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 15664a65b0f1SAllen-KH Cheng }; 15674a65b0f1SAllen-KH Cheng 15684a65b0f1SAllen-KH Cheng larb17: larb@1a010000 { 15694a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15704a65b0f1SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 15714a65b0f1SAllen-KH Cheng mediatek,larb-id = <17>; 15724a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15734a65b0f1SAllen-KH Cheng clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 15744a65b0f1SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX>; 15754a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15764a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 15774a65b0f1SAllen-KH Cheng }; 15784a65b0f1SAllen-KH Cheng 15794a65b0f1SAllen-KH Cheng larb18: larb@1a011000 { 15804a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15814a65b0f1SAllen-KH Cheng reg = <0 0x1a011000 0 0x1000>; 15824a65b0f1SAllen-KH Cheng mediatek,larb-id = <18>; 15834a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15844a65b0f1SAllen-KH Cheng clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 15854a65b0f1SAllen-KH Cheng <&camsys_rawc CLK_CAM_RAWC_CAM>; 15864a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15874a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 15884a65b0f1SAllen-KH Cheng }; 15894a65b0f1SAllen-KH Cheng 15905d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 15915d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 15925d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 15935d2b897bSChun-Jie Chen #clock-cells = <1>; 15945d2b897bSChun-Jie Chen }; 15955d2b897bSChun-Jie Chen 15965d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 15975d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 15985d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 15995d2b897bSChun-Jie Chen #clock-cells = <1>; 16005d2b897bSChun-Jie Chen }; 16015d2b897bSChun-Jie Chen 16025d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 16035d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 16045d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 16055d2b897bSChun-Jie Chen #clock-cells = <1>; 16065d2b897bSChun-Jie Chen }; 16075d2b897bSChun-Jie Chen 16085d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 16095d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 16105d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 16115d2b897bSChun-Jie Chen #clock-cells = <1>; 16125d2b897bSChun-Jie Chen }; 16135d2b897bSChun-Jie Chen 16144a65b0f1SAllen-KH Cheng larb20: larb@1b00f000 { 16154a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16164a65b0f1SAllen-KH Cheng reg = <0 0x1b00f000 0 0x1000>; 16174a65b0f1SAllen-KH Cheng mediatek,larb-id = <20>; 16184a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16194a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 16204a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB20>; 16214a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16224a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 16234a65b0f1SAllen-KH Cheng }; 16244a65b0f1SAllen-KH Cheng 16254a65b0f1SAllen-KH Cheng larb19: larb@1b10f000 { 16264a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16274a65b0f1SAllen-KH Cheng reg = <0 0x1b10f000 0 0x1000>; 16284a65b0f1SAllen-KH Cheng mediatek,larb-id = <19>; 16294a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16304a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 16314a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB19>; 16324a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16334a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 16344a65b0f1SAllen-KH Cheng }; 16354a65b0f1SAllen-KH Cheng 16365d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 16375d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 16385d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 16395d2b897bSChun-Jie Chen #clock-cells = <1>; 16405d2b897bSChun-Jie Chen }; 16414a65b0f1SAllen-KH Cheng 16424a65b0f1SAllen-KH Cheng larb2: larb@1f002000 { 16434a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16444a65b0f1SAllen-KH Cheng reg = <0 0x1f002000 0 0x1000>; 16454a65b0f1SAllen-KH Cheng mediatek,larb-id = <2>; 16464a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16474a65b0f1SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, 16484a65b0f1SAllen-KH Cheng <&mdpsys CLK_MDP_SMI0>; 16494a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16504a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 16514a65b0f1SAllen-KH Cheng }; 165248489980SSeiya Wang }; 165348489980SSeiya Wang}; 1654