148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 114a65b0f1SAllen-KH Cheng#include <dt-bindings/memory/mt8192-larb-port.h> 1248489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 13e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h> 14994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 1548489980SSeiya Wang 1648489980SSeiya Wang/ { 1748489980SSeiya Wang compatible = "mediatek,mt8192"; 1848489980SSeiya Wang interrupt-parent = <&gic>; 1948489980SSeiya Wang #address-cells = <2>; 2048489980SSeiya Wang #size-cells = <2>; 2148489980SSeiya Wang 2248489980SSeiya Wang clk26m: oscillator0 { 2348489980SSeiya Wang compatible = "fixed-clock"; 2448489980SSeiya Wang #clock-cells = <0>; 2548489980SSeiya Wang clock-frequency = <26000000>; 2648489980SSeiya Wang clock-output-names = "clk26m"; 2748489980SSeiya Wang }; 2848489980SSeiya Wang 2948489980SSeiya Wang clk32k: oscillator1 { 3048489980SSeiya Wang compatible = "fixed-clock"; 3148489980SSeiya Wang #clock-cells = <0>; 3248489980SSeiya Wang clock-frequency = <32768>; 3348489980SSeiya Wang clock-output-names = "clk32k"; 3448489980SSeiya Wang }; 3548489980SSeiya Wang 3648489980SSeiya Wang cpus { 3748489980SSeiya Wang #address-cells = <1>; 3848489980SSeiya Wang #size-cells = <0>; 3948489980SSeiya Wang 4048489980SSeiya Wang cpu0: cpu@0 { 4148489980SSeiya Wang device_type = "cpu"; 4248489980SSeiya Wang compatible = "arm,cortex-a55"; 4348489980SSeiya Wang reg = <0x000>; 4448489980SSeiya Wang enable-method = "psci"; 4548489980SSeiya Wang clock-frequency = <1701000000>; 469260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 4748489980SSeiya Wang next-level-cache = <&l2_0>; 4848489980SSeiya Wang capacity-dmips-mhz = <530>; 4948489980SSeiya Wang }; 5048489980SSeiya Wang 5148489980SSeiya Wang cpu1: cpu@100 { 5248489980SSeiya Wang device_type = "cpu"; 5348489980SSeiya Wang compatible = "arm,cortex-a55"; 5448489980SSeiya Wang reg = <0x100>; 5548489980SSeiya Wang enable-method = "psci"; 5648489980SSeiya Wang clock-frequency = <1701000000>; 579260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 5848489980SSeiya Wang next-level-cache = <&l2_0>; 5948489980SSeiya Wang capacity-dmips-mhz = <530>; 6048489980SSeiya Wang }; 6148489980SSeiya Wang 6248489980SSeiya Wang cpu2: cpu@200 { 6348489980SSeiya Wang device_type = "cpu"; 6448489980SSeiya Wang compatible = "arm,cortex-a55"; 6548489980SSeiya Wang reg = <0x200>; 6648489980SSeiya Wang enable-method = "psci"; 6748489980SSeiya Wang clock-frequency = <1701000000>; 689260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 6948489980SSeiya Wang next-level-cache = <&l2_0>; 7048489980SSeiya Wang capacity-dmips-mhz = <530>; 7148489980SSeiya Wang }; 7248489980SSeiya Wang 7348489980SSeiya Wang cpu3: cpu@300 { 7448489980SSeiya Wang device_type = "cpu"; 7548489980SSeiya Wang compatible = "arm,cortex-a55"; 7648489980SSeiya Wang reg = <0x300>; 7748489980SSeiya Wang enable-method = "psci"; 7848489980SSeiya Wang clock-frequency = <1701000000>; 799260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 8048489980SSeiya Wang next-level-cache = <&l2_0>; 8148489980SSeiya Wang capacity-dmips-mhz = <530>; 8248489980SSeiya Wang }; 8348489980SSeiya Wang 8448489980SSeiya Wang cpu4: cpu@400 { 8548489980SSeiya Wang device_type = "cpu"; 8648489980SSeiya Wang compatible = "arm,cortex-a76"; 8748489980SSeiya Wang reg = <0x400>; 8848489980SSeiya Wang enable-method = "psci"; 8948489980SSeiya Wang clock-frequency = <2171000000>; 909260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 9148489980SSeiya Wang next-level-cache = <&l2_1>; 9248489980SSeiya Wang capacity-dmips-mhz = <1024>; 9348489980SSeiya Wang }; 9448489980SSeiya Wang 9548489980SSeiya Wang cpu5: cpu@500 { 9648489980SSeiya Wang device_type = "cpu"; 9748489980SSeiya Wang compatible = "arm,cortex-a76"; 9848489980SSeiya Wang reg = <0x500>; 9948489980SSeiya Wang enable-method = "psci"; 10048489980SSeiya Wang clock-frequency = <2171000000>; 1019260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 10248489980SSeiya Wang next-level-cache = <&l2_1>; 10348489980SSeiya Wang capacity-dmips-mhz = <1024>; 10448489980SSeiya Wang }; 10548489980SSeiya Wang 10648489980SSeiya Wang cpu6: cpu@600 { 10748489980SSeiya Wang device_type = "cpu"; 10848489980SSeiya Wang compatible = "arm,cortex-a76"; 10948489980SSeiya Wang reg = <0x600>; 11048489980SSeiya Wang enable-method = "psci"; 11148489980SSeiya Wang clock-frequency = <2171000000>; 1129260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 11348489980SSeiya Wang next-level-cache = <&l2_1>; 11448489980SSeiya Wang capacity-dmips-mhz = <1024>; 11548489980SSeiya Wang }; 11648489980SSeiya Wang 11748489980SSeiya Wang cpu7: cpu@700 { 11848489980SSeiya Wang device_type = "cpu"; 11948489980SSeiya Wang compatible = "arm,cortex-a76"; 12048489980SSeiya Wang reg = <0x700>; 12148489980SSeiya Wang enable-method = "psci"; 12248489980SSeiya Wang clock-frequency = <2171000000>; 1239260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 12448489980SSeiya Wang next-level-cache = <&l2_1>; 12548489980SSeiya Wang capacity-dmips-mhz = <1024>; 12648489980SSeiya Wang }; 12748489980SSeiya Wang 12848489980SSeiya Wang cpu-map { 12948489980SSeiya Wang cluster0 { 13048489980SSeiya Wang core0 { 13148489980SSeiya Wang cpu = <&cpu0>; 13248489980SSeiya Wang }; 13348489980SSeiya Wang core1 { 13448489980SSeiya Wang cpu = <&cpu1>; 13548489980SSeiya Wang }; 13648489980SSeiya Wang core2 { 13748489980SSeiya Wang cpu = <&cpu2>; 13848489980SSeiya Wang }; 13948489980SSeiya Wang core3 { 14048489980SSeiya Wang cpu = <&cpu3>; 14148489980SSeiya Wang }; 14248489980SSeiya Wang }; 14348489980SSeiya Wang 14448489980SSeiya Wang cluster1 { 14548489980SSeiya Wang core0 { 14648489980SSeiya Wang cpu = <&cpu4>; 14748489980SSeiya Wang }; 14848489980SSeiya Wang core1 { 14948489980SSeiya Wang cpu = <&cpu5>; 15048489980SSeiya Wang }; 15148489980SSeiya Wang core2 { 15248489980SSeiya Wang cpu = <&cpu6>; 15348489980SSeiya Wang }; 15448489980SSeiya Wang core3 { 15548489980SSeiya Wang cpu = <&cpu7>; 15648489980SSeiya Wang }; 15748489980SSeiya Wang }; 15848489980SSeiya Wang }; 15948489980SSeiya Wang 16048489980SSeiya Wang l2_0: l2-cache0 { 16148489980SSeiya Wang compatible = "cache"; 16248489980SSeiya Wang next-level-cache = <&l3_0>; 16348489980SSeiya Wang }; 16448489980SSeiya Wang 16548489980SSeiya Wang l2_1: l2-cache1 { 16648489980SSeiya Wang compatible = "cache"; 16748489980SSeiya Wang next-level-cache = <&l3_0>; 16848489980SSeiya Wang }; 16948489980SSeiya Wang 17048489980SSeiya Wang l3_0: l3-cache { 17148489980SSeiya Wang compatible = "cache"; 17248489980SSeiya Wang }; 1739260918dSJames Liao 1749260918dSJames Liao idle-states { 1759260918dSJames Liao entry-method = "arm,psci"; 1769260918dSJames Liao cpuoff_l: cpuoff_l { 1779260918dSJames Liao compatible = "arm,idle-state"; 1789260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1799260918dSJames Liao local-timer-stop; 1809260918dSJames Liao entry-latency-us = <55>; 1819260918dSJames Liao exit-latency-us = <140>; 1829260918dSJames Liao min-residency-us = <780>; 1839260918dSJames Liao }; 1849260918dSJames Liao cpuoff_b: cpuoff_b { 1859260918dSJames Liao compatible = "arm,idle-state"; 1869260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1879260918dSJames Liao local-timer-stop; 1889260918dSJames Liao entry-latency-us = <35>; 1899260918dSJames Liao exit-latency-us = <145>; 1909260918dSJames Liao min-residency-us = <720>; 1919260918dSJames Liao }; 1929260918dSJames Liao clusteroff_l: clusteroff_l { 1939260918dSJames Liao compatible = "arm,idle-state"; 1949260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 1959260918dSJames Liao local-timer-stop; 1969260918dSJames Liao entry-latency-us = <60>; 1979260918dSJames Liao exit-latency-us = <155>; 1989260918dSJames Liao min-residency-us = <860>; 1999260918dSJames Liao }; 2009260918dSJames Liao clusteroff_b: clusteroff_b { 2019260918dSJames Liao compatible = "arm,idle-state"; 2029260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2039260918dSJames Liao local-timer-stop; 2049260918dSJames Liao entry-latency-us = <40>; 2059260918dSJames Liao exit-latency-us = <155>; 2069260918dSJames Liao min-residency-us = <780>; 2079260918dSJames Liao }; 2089260918dSJames Liao }; 20948489980SSeiya Wang }; 21048489980SSeiya Wang 21148489980SSeiya Wang pmu-a55 { 21248489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 21348489980SSeiya Wang interrupt-parent = <&gic>; 21448489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 21548489980SSeiya Wang }; 21648489980SSeiya Wang 21748489980SSeiya Wang pmu-a76 { 21848489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 21948489980SSeiya Wang interrupt-parent = <&gic>; 22048489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 22148489980SSeiya Wang }; 22248489980SSeiya Wang 22348489980SSeiya Wang psci { 22448489980SSeiya Wang compatible = "arm,psci-1.0"; 22548489980SSeiya Wang method = "smc"; 22648489980SSeiya Wang }; 22748489980SSeiya Wang 22848489980SSeiya Wang timer: timer { 22948489980SSeiya Wang compatible = "arm,armv8-timer"; 23048489980SSeiya Wang interrupt-parent = <&gic>; 23148489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 23248489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 23348489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 23448489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 23548489980SSeiya Wang clock-frequency = <13000000>; 23648489980SSeiya Wang }; 23748489980SSeiya Wang 23848489980SSeiya Wang soc { 23948489980SSeiya Wang #address-cells = <2>; 24048489980SSeiya Wang #size-cells = <2>; 24148489980SSeiya Wang compatible = "simple-bus"; 24248489980SSeiya Wang ranges; 24348489980SSeiya Wang 24448489980SSeiya Wang gic: interrupt-controller@c000000 { 24548489980SSeiya Wang compatible = "arm,gic-v3"; 24648489980SSeiya Wang #interrupt-cells = <4>; 24748489980SSeiya Wang #redistributor-regions = <1>; 24848489980SSeiya Wang interrupt-parent = <&gic>; 24948489980SSeiya Wang interrupt-controller; 25048489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 25148489980SSeiya Wang <0 0x0c040000 0 0x200000>; 25248489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 25348489980SSeiya Wang 25448489980SSeiya Wang ppi-partitions { 25548489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 25648489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 25748489980SSeiya Wang }; 25848489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 25948489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 26048489980SSeiya Wang }; 26148489980SSeiya Wang }; 26248489980SSeiya Wang }; 26348489980SSeiya Wang 2645d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 2655d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 2665d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 2675d2b897bSChun-Jie Chen #clock-cells = <1>; 2685d2b897bSChun-Jie Chen }; 2695d2b897bSChun-Jie Chen 2705d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 2715d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 2725d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 2735d2b897bSChun-Jie Chen #clock-cells = <1>; 2745d2b897bSChun-Jie Chen }; 2755d2b897bSChun-Jie Chen 2765d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 2775d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 2785d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 2795d2b897bSChun-Jie Chen #clock-cells = <1>; 2805d2b897bSChun-Jie Chen }; 2815d2b897bSChun-Jie Chen 28248489980SSeiya Wang pio: pinctrl@10005000 { 28348489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 28448489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 28548489980SSeiya Wang <0 0x11c20000 0 0x1000>, 28648489980SSeiya Wang <0 0x11d10000 0 0x1000>, 28748489980SSeiya Wang <0 0x11d30000 0 0x1000>, 28848489980SSeiya Wang <0 0x11d40000 0 0x1000>, 28948489980SSeiya Wang <0 0x11e20000 0 0x1000>, 29048489980SSeiya Wang <0 0x11e70000 0 0x1000>, 29148489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 29248489980SSeiya Wang <0 0x11f20000 0 0x1000>, 29348489980SSeiya Wang <0 0x11f30000 0 0x1000>, 29448489980SSeiya Wang <0 0x1000b000 0 0x1000>; 29548489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 29648489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 29748489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 29848489980SSeiya Wang "iocfg_tl", "eint"; 29948489980SSeiya Wang gpio-controller; 30048489980SSeiya Wang #gpio-cells = <2>; 30148489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 30248489980SSeiya Wang interrupt-controller; 30348489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 30448489980SSeiya Wang #interrupt-cells = <2>; 30548489980SSeiya Wang }; 30648489980SSeiya Wang 307994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 308994a71a3SChun-Jie Chen compatible = "syscon", "simple-mfd"; 309994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 310994a71a3SChun-Jie Chen #power-domain-cells = <1>; 311994a71a3SChun-Jie Chen 312994a71a3SChun-Jie Chen /* System Power Manager */ 313994a71a3SChun-Jie Chen spm: power-controller { 314994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 315994a71a3SChun-Jie Chen #address-cells = <1>; 316994a71a3SChun-Jie Chen #size-cells = <0>; 317994a71a3SChun-Jie Chen #power-domain-cells = <1>; 318994a71a3SChun-Jie Chen 319994a71a3SChun-Jie Chen /* power domain of the SoC */ 320994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 321994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 322994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 323994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 324994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 325994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 326994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 327994a71a3SChun-Jie Chen #power-domain-cells = <0>; 328994a71a3SChun-Jie Chen }; 329994a71a3SChun-Jie Chen 330994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 331994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 332994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 333994a71a3SChun-Jie Chen clock-names = "conn"; 334994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 335994a71a3SChun-Jie Chen #power-domain-cells = <0>; 336994a71a3SChun-Jie Chen }; 337994a71a3SChun-Jie Chen 338994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG0 { 339994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 340994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 341994a71a3SChun-Jie Chen clock-names = "mfg"; 342994a71a3SChun-Jie Chen #address-cells = <1>; 343994a71a3SChun-Jie Chen #size-cells = <0>; 344994a71a3SChun-Jie Chen #power-domain-cells = <1>; 345994a71a3SChun-Jie Chen 346994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG1 { 347994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 348994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 349994a71a3SChun-Jie Chen #address-cells = <1>; 350994a71a3SChun-Jie Chen #size-cells = <0>; 351994a71a3SChun-Jie Chen #power-domain-cells = <1>; 352994a71a3SChun-Jie Chen 353994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 354994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 355994a71a3SChun-Jie Chen #power-domain-cells = <0>; 356994a71a3SChun-Jie Chen }; 357994a71a3SChun-Jie Chen 358994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 359994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 360994a71a3SChun-Jie Chen #power-domain-cells = <0>; 361994a71a3SChun-Jie Chen }; 362994a71a3SChun-Jie Chen 363994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 364994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 365994a71a3SChun-Jie Chen #power-domain-cells = <0>; 366994a71a3SChun-Jie Chen }; 367994a71a3SChun-Jie Chen 368994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 369994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 370994a71a3SChun-Jie Chen #power-domain-cells = <0>; 371994a71a3SChun-Jie Chen }; 372994a71a3SChun-Jie Chen 373994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 374994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 375994a71a3SChun-Jie Chen #power-domain-cells = <0>; 376994a71a3SChun-Jie Chen }; 377994a71a3SChun-Jie Chen }; 378994a71a3SChun-Jie Chen }; 379994a71a3SChun-Jie Chen 380994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 381994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 382994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 383994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 384994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 385994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 386994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 387994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 388994a71a3SChun-Jie Chen "disp-3"; 389994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 390994a71a3SChun-Jie Chen #address-cells = <1>; 391994a71a3SChun-Jie Chen #size-cells = <0>; 392994a71a3SChun-Jie Chen #power-domain-cells = <1>; 393994a71a3SChun-Jie Chen 394994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 395994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 396994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 397994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 398994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 399994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 400994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 401994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 402994a71a3SChun-Jie Chen "ipe-3"; 403994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 404994a71a3SChun-Jie Chen #power-domain-cells = <0>; 405994a71a3SChun-Jie Chen }; 406994a71a3SChun-Jie Chen 407994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 408994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 409994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 410994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 411994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 412994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 413994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 414994a71a3SChun-Jie Chen #power-domain-cells = <0>; 415994a71a3SChun-Jie Chen }; 416994a71a3SChun-Jie Chen 417994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 418994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 419994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 420994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 421994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 422994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 423994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 424994a71a3SChun-Jie Chen #power-domain-cells = <0>; 425994a71a3SChun-Jie Chen }; 426994a71a3SChun-Jie Chen 427994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 428994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 429994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 430994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 431994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 432994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 433994a71a3SChun-Jie Chen #power-domain-cells = <0>; 434994a71a3SChun-Jie Chen }; 435994a71a3SChun-Jie Chen 436994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 437994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 438994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 439994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 440994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 441994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 442994a71a3SChun-Jie Chen #power-domain-cells = <0>; 443994a71a3SChun-Jie Chen }; 444994a71a3SChun-Jie Chen 445994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 446994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 447994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 448994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 449994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 450994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 451994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 452994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 453994a71a3SChun-Jie Chen #address-cells = <1>; 454994a71a3SChun-Jie Chen #size-cells = <0>; 455994a71a3SChun-Jie Chen #power-domain-cells = <1>; 456994a71a3SChun-Jie Chen 457994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 458994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 459994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 460994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 461994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 462994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 463994a71a3SChun-Jie Chen "vdec2-2"; 464994a71a3SChun-Jie Chen #power-domain-cells = <0>; 465994a71a3SChun-Jie Chen }; 466994a71a3SChun-Jie Chen }; 467994a71a3SChun-Jie Chen 468994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 469994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 470994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 471994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 472994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 473994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 474994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 475994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 476994a71a3SChun-Jie Chen "cam-3"; 477994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 478994a71a3SChun-Jie Chen #address-cells = <1>; 479994a71a3SChun-Jie Chen #size-cells = <0>; 480994a71a3SChun-Jie Chen #power-domain-cells = <1>; 481994a71a3SChun-Jie Chen 482994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 483994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 484994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 485994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 486994a71a3SChun-Jie Chen #power-domain-cells = <0>; 487994a71a3SChun-Jie Chen }; 488994a71a3SChun-Jie Chen 489994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 490994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 491994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 492994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 493994a71a3SChun-Jie Chen #power-domain-cells = <0>; 494994a71a3SChun-Jie Chen }; 495994a71a3SChun-Jie Chen 496994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 497994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 498994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 499994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 500994a71a3SChun-Jie Chen #power-domain-cells = <0>; 501994a71a3SChun-Jie Chen }; 502994a71a3SChun-Jie Chen }; 503994a71a3SChun-Jie Chen }; 504994a71a3SChun-Jie Chen }; 505994a71a3SChun-Jie Chen }; 506994a71a3SChun-Jie Chen 507d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 508d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 509d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 510d1986fbdSAllen-KH Cheng #reset-cells = <1>; 511d1986fbdSAllen-KH Cheng }; 512d1986fbdSAllen-KH Cheng 5135d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 5145d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 5155d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 5165d2b897bSChun-Jie Chen #clock-cells = <1>; 5175d2b897bSChun-Jie Chen }; 5185d2b897bSChun-Jie Chen 51948489980SSeiya Wang systimer: timer@10017000 { 52048489980SSeiya Wang compatible = "mediatek,mt8192-timer", 52148489980SSeiya Wang "mediatek,mt6765-timer"; 52248489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 52348489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 524dde3c175SAllen-KH Cheng clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 52548489980SSeiya Wang clock-names = "clk13m"; 52648489980SSeiya Wang }; 52748489980SSeiya Wang 528261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 529261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 530261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 531261691b4SAllen-KH Cheng reg-names = "pwrap"; 532261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 533261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 534261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 535261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 536261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 537261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 538261691b4SAllen-KH Cheng }; 539261691b4SAllen-KH Cheng 5405d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 5415d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 5425d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 5435d2b897bSChun-Jie Chen #clock-cells = <1>; 5445d2b897bSChun-Jie Chen }; 5455d2b897bSChun-Jie Chen 54648489980SSeiya Wang uart0: serial@11002000 { 54748489980SSeiya Wang compatible = "mediatek,mt8192-uart", 54848489980SSeiya Wang "mediatek,mt6577-uart"; 54948489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 55048489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 55173ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 55248489980SSeiya Wang clock-names = "baud", "bus"; 55348489980SSeiya Wang status = "disabled"; 55448489980SSeiya Wang }; 55548489980SSeiya Wang 55648489980SSeiya Wang uart1: serial@11003000 { 55748489980SSeiya Wang compatible = "mediatek,mt8192-uart", 55848489980SSeiya Wang "mediatek,mt6577-uart"; 55948489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 56048489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 56173ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 56248489980SSeiya Wang clock-names = "baud", "bus"; 56348489980SSeiya Wang status = "disabled"; 56448489980SSeiya Wang }; 56548489980SSeiya Wang 5665d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 5675d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 5685d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 5695d2b897bSChun-Jie Chen #clock-cells = <1>; 5705d2b897bSChun-Jie Chen }; 5715d2b897bSChun-Jie Chen 57248489980SSeiya Wang spi0: spi@1100a000 { 57348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 57448489980SSeiya Wang "mediatek,mt6765-spi"; 57548489980SSeiya Wang #address-cells = <1>; 57648489980SSeiya Wang #size-cells = <0>; 57748489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 57848489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 5797f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5807f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5817f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 58248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 58348489980SSeiya Wang status = "disabled"; 58448489980SSeiya Wang }; 58548489980SSeiya Wang 58648489980SSeiya Wang spi1: spi@11010000 { 58748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 58848489980SSeiya Wang "mediatek,mt6765-spi"; 58948489980SSeiya Wang #address-cells = <1>; 59048489980SSeiya Wang #size-cells = <0>; 59148489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 59248489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 5937f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5947f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5957f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 59648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 59748489980SSeiya Wang status = "disabled"; 59848489980SSeiya Wang }; 59948489980SSeiya Wang 60048489980SSeiya Wang spi2: spi@11012000 { 60148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 60248489980SSeiya Wang "mediatek,mt6765-spi"; 60348489980SSeiya Wang #address-cells = <1>; 60448489980SSeiya Wang #size-cells = <0>; 60548489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 60648489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 6077f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6087f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6097f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 61048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 61148489980SSeiya Wang status = "disabled"; 61248489980SSeiya Wang }; 61348489980SSeiya Wang 61448489980SSeiya Wang spi3: spi@11013000 { 61548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 61648489980SSeiya Wang "mediatek,mt6765-spi"; 61748489980SSeiya Wang #address-cells = <1>; 61848489980SSeiya Wang #size-cells = <0>; 61948489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 62048489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 6217f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6227f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6237f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 62448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 62548489980SSeiya Wang status = "disabled"; 62648489980SSeiya Wang }; 62748489980SSeiya Wang 62848489980SSeiya Wang spi4: spi@11018000 { 62948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 63048489980SSeiya Wang "mediatek,mt6765-spi"; 63148489980SSeiya Wang #address-cells = <1>; 63248489980SSeiya Wang #size-cells = <0>; 63348489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 63448489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 6357f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6367f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6377f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 63848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 63948489980SSeiya Wang status = "disabled"; 64048489980SSeiya Wang }; 64148489980SSeiya Wang 64248489980SSeiya Wang spi5: spi@11019000 { 64348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 64448489980SSeiya Wang "mediatek,mt6765-spi"; 64548489980SSeiya Wang #address-cells = <1>; 64648489980SSeiya Wang #size-cells = <0>; 64748489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 64848489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 6497f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6507f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6517f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 65248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 65348489980SSeiya Wang status = "disabled"; 65448489980SSeiya Wang }; 65548489980SSeiya Wang 65648489980SSeiya Wang spi6: spi@1101d000 { 65748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 65848489980SSeiya Wang "mediatek,mt6765-spi"; 65948489980SSeiya Wang #address-cells = <1>; 66048489980SSeiya Wang #size-cells = <0>; 66148489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 66248489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 6637f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6647f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6657f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 66648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 66748489980SSeiya Wang status = "disabled"; 66848489980SSeiya Wang }; 66948489980SSeiya Wang 67048489980SSeiya Wang spi7: spi@1101e000 { 67148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 67248489980SSeiya Wang "mediatek,mt6765-spi"; 67348489980SSeiya Wang #address-cells = <1>; 67448489980SSeiya Wang #size-cells = <0>; 67548489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 67648489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 6777f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6787f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6797f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 68048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 68148489980SSeiya Wang status = "disabled"; 68248489980SSeiya Wang }; 68348489980SSeiya Wang 684c63556ecSAllen-KH Cheng scp: scp@10500000 { 685c63556ecSAllen-KH Cheng compatible = "mediatek,mt8192-scp"; 686c63556ecSAllen-KH Cheng reg = <0 0x10500000 0 0x100000>, 687c63556ecSAllen-KH Cheng <0 0x10700000 0 0x8000>, 688c63556ecSAllen-KH Cheng <0 0x10720000 0 0xe0000>; 689c63556ecSAllen-KH Cheng reg-names = "sram", "l1tcm", "cfg"; 690c63556ecSAllen-KH Cheng interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 691c63556ecSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SCPSYS>; 692c63556ecSAllen-KH Cheng clock-names = "main"; 693c63556ecSAllen-KH Cheng status = "disabled"; 694c63556ecSAllen-KH Cheng }; 695c63556ecSAllen-KH Cheng 696e5aac225SAllen-KH Cheng xhci: usb@11200000 { 697e5aac225SAllen-KH Cheng compatible = "mediatek,mt8192-xhci", 698e5aac225SAllen-KH Cheng "mediatek,mtk-xhci"; 699e5aac225SAllen-KH Cheng reg = <0 0x11200000 0 0x1000>, 700e5aac225SAllen-KH Cheng <0 0x11203e00 0 0x0100>; 701e5aac225SAllen-KH Cheng reg-names = "mac", "ippc"; 702e5aac225SAllen-KH Cheng interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 703e5aac225SAllen-KH Cheng interrupt-names = "host"; 704e5aac225SAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>, 705e5aac225SAllen-KH Cheng <&u3port0 PHY_TYPE_USB3>; 706e5aac225SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 707e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 708e5aac225SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 709e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 710e5aac225SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SSUSB>, 711e5aac225SAllen-KH Cheng <&infracfg CLK_INFRA_SSUSB_XHCI>, 712e5aac225SAllen-KH Cheng <&apmixedsys CLK_APMIXED_USBPLL>; 713e5aac225SAllen-KH Cheng clock-names = "sys_ck", "xhci_ck", "ref_ck"; 714e5aac225SAllen-KH Cheng wakeup-source; 715e5aac225SAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 102>; 716e5aac225SAllen-KH Cheng status = "disabled"; 717e5aac225SAllen-KH Cheng }; 718e5aac225SAllen-KH Cheng 719d0a197a0Sbayi cheng nor_flash: spi@11234000 { 720d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 721d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 722d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 723aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 724aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 725aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 726d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 727aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 728aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 729d0a197a0Sbayi cheng #address-cells = <1>; 730d0a197a0Sbayi cheng #size-cells = <0>; 73127f0eb16SAllen-KH Cheng status = "disabled"; 732d0a197a0Sbayi cheng }; 733d0a197a0Sbayi cheng 7345d2b897bSChun-Jie Chen audsys: clock-controller@11210000 { 7355d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-audsys", "syscon"; 7365d2b897bSChun-Jie Chen reg = <0 0x11210000 0 0x1000>; 7375d2b897bSChun-Jie Chen #clock-cells = <1>; 7385d2b897bSChun-Jie Chen }; 7395d2b897bSChun-Jie Chen 7404d50a433SAllen-KH Cheng efuse: efuse@11c10000 { 7414d50a433SAllen-KH Cheng compatible = "mediatek,efuse"; 7424d50a433SAllen-KH Cheng reg = <0 0x11c10000 0 0x1000>; 7434d50a433SAllen-KH Cheng #address-cells = <1>; 7444d50a433SAllen-KH Cheng #size-cells = <1>; 7454d50a433SAllen-KH Cheng 7464d50a433SAllen-KH Cheng lvts_e_data1: data1@1c0 { 7474d50a433SAllen-KH Cheng reg = <0x1c0 0x58>; 7484d50a433SAllen-KH Cheng }; 7494d50a433SAllen-KH Cheng 7504d50a433SAllen-KH Cheng svs_calibration: calib@580 { 7514d50a433SAllen-KH Cheng reg = <0x580 0x68>; 7524d50a433SAllen-KH Cheng }; 7534d50a433SAllen-KH Cheng }; 7544d50a433SAllen-KH Cheng 7557f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 75648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 75748489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 75848489980SSeiya Wang <0 0x10217300 0 0x80>; 75948489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 76022623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 76122623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 76248489980SSeiya Wang clock-names = "main", "dma"; 76348489980SSeiya Wang clock-div = <1>; 76448489980SSeiya Wang #address-cells = <1>; 76548489980SSeiya Wang #size-cells = <0>; 76648489980SSeiya Wang status = "disabled"; 76748489980SSeiya Wang }; 76848489980SSeiya Wang 7695d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 7705d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 7715d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 7725d2b897bSChun-Jie Chen #clock-cells = <1>; 7735d2b897bSChun-Jie Chen }; 7745d2b897bSChun-Jie Chen 7757f1a9f47SFabien Parent i2c7: i2c@11d00000 { 77648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 77748489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 77848489980SSeiya Wang <0 0x10217600 0 0x180>; 77948489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 78022623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 78122623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 78248489980SSeiya Wang clock-names = "main", "dma"; 78348489980SSeiya Wang clock-div = <1>; 78448489980SSeiya Wang #address-cells = <1>; 78548489980SSeiya Wang #size-cells = <0>; 78648489980SSeiya Wang status = "disabled"; 78748489980SSeiya Wang }; 78848489980SSeiya Wang 7897f1a9f47SFabien Parent i2c8: i2c@11d01000 { 79048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 79148489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 79248489980SSeiya Wang <0 0x10217780 0 0x180>; 79348489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 79422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 79522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 79648489980SSeiya Wang clock-names = "main", "dma"; 79748489980SSeiya Wang clock-div = <1>; 79848489980SSeiya Wang #address-cells = <1>; 79948489980SSeiya Wang #size-cells = <0>; 80048489980SSeiya Wang status = "disabled"; 80148489980SSeiya Wang }; 80248489980SSeiya Wang 8037f1a9f47SFabien Parent i2c9: i2c@11d02000 { 80448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 80548489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 80648489980SSeiya Wang <0 0x10217900 0 0x180>; 80748489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 80822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 80922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 81048489980SSeiya Wang clock-names = "main", "dma"; 81148489980SSeiya Wang clock-div = <1>; 81248489980SSeiya Wang #address-cells = <1>; 81348489980SSeiya Wang #size-cells = <0>; 81448489980SSeiya Wang status = "disabled"; 81548489980SSeiya Wang }; 81648489980SSeiya Wang 8175d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 8185d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 8195d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 8205d2b897bSChun-Jie Chen #clock-cells = <1>; 8215d2b897bSChun-Jie Chen }; 8225d2b897bSChun-Jie Chen 8237f1a9f47SFabien Parent i2c1: i2c@11d20000 { 82448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 82548489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 82648489980SSeiya Wang <0 0x10217100 0 0x80>; 82748489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 82822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 82922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 83048489980SSeiya Wang clock-names = "main", "dma"; 83148489980SSeiya Wang clock-div = <1>; 83248489980SSeiya Wang #address-cells = <1>; 83348489980SSeiya Wang #size-cells = <0>; 83448489980SSeiya Wang status = "disabled"; 83548489980SSeiya Wang }; 83648489980SSeiya Wang 8377f1a9f47SFabien Parent i2c2: i2c@11d21000 { 83848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 83948489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 84048489980SSeiya Wang <0 0x10217180 0 0x180>; 84148489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 84222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 84322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 84448489980SSeiya Wang clock-names = "main", "dma"; 84548489980SSeiya Wang clock-div = <1>; 84648489980SSeiya Wang #address-cells = <1>; 84748489980SSeiya Wang #size-cells = <0>; 84848489980SSeiya Wang status = "disabled"; 84948489980SSeiya Wang }; 85048489980SSeiya Wang 8517f1a9f47SFabien Parent i2c4: i2c@11d22000 { 85248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 85348489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 85448489980SSeiya Wang <0 0x10217380 0 0x180>; 85548489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 85622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 85722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 85848489980SSeiya Wang clock-names = "main", "dma"; 85948489980SSeiya Wang clock-div = <1>; 86048489980SSeiya Wang #address-cells = <1>; 86148489980SSeiya Wang #size-cells = <0>; 86248489980SSeiya Wang status = "disabled"; 86348489980SSeiya Wang }; 86448489980SSeiya Wang 8655d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 8665d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 8675d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 8685d2b897bSChun-Jie Chen #clock-cells = <1>; 8695d2b897bSChun-Jie Chen }; 8705d2b897bSChun-Jie Chen 8717f1a9f47SFabien Parent i2c5: i2c@11e00000 { 87248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 87348489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 87448489980SSeiya Wang <0 0x10217500 0 0x80>; 87548489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 87622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 87722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 87848489980SSeiya Wang clock-names = "main", "dma"; 87948489980SSeiya Wang clock-div = <1>; 88048489980SSeiya Wang #address-cells = <1>; 88148489980SSeiya Wang #size-cells = <0>; 88248489980SSeiya Wang status = "disabled"; 88348489980SSeiya Wang }; 88448489980SSeiya Wang 8855d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 8865d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 8875d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 8885d2b897bSChun-Jie Chen #clock-cells = <1>; 8895d2b897bSChun-Jie Chen }; 8905d2b897bSChun-Jie Chen 89140de66b8SAllen-KH Cheng u3phy0: t-phy@11e40000 { 89240de66b8SAllen-KH Cheng compatible = "mediatek,mt8192-tphy", 89340de66b8SAllen-KH Cheng "mediatek,generic-tphy-v2"; 89440de66b8SAllen-KH Cheng #address-cells = <1>; 89540de66b8SAllen-KH Cheng #size-cells = <1>; 89640de66b8SAllen-KH Cheng ranges = <0x0 0x0 0x11e40000 0x1000>; 89740de66b8SAllen-KH Cheng 89840de66b8SAllen-KH Cheng u2port0: usb-phy@0 { 89940de66b8SAllen-KH Cheng reg = <0x0 0x700>; 90040de66b8SAllen-KH Cheng clocks = <&clk26m>; 90140de66b8SAllen-KH Cheng clock-names = "ref"; 90240de66b8SAllen-KH Cheng #phy-cells = <1>; 90340de66b8SAllen-KH Cheng }; 90440de66b8SAllen-KH Cheng 90540de66b8SAllen-KH Cheng u3port0: usb-phy@700 { 90640de66b8SAllen-KH Cheng reg = <0x700 0x900>; 90740de66b8SAllen-KH Cheng clocks = <&clk26m>; 90840de66b8SAllen-KH Cheng clock-names = "ref"; 90940de66b8SAllen-KH Cheng #phy-cells = <1>; 91040de66b8SAllen-KH Cheng }; 91140de66b8SAllen-KH Cheng }; 91240de66b8SAllen-KH Cheng 9137f1a9f47SFabien Parent i2c0: i2c@11f00000 { 91448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 91548489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 91648489980SSeiya Wang <0 0x10217080 0 0x80>; 91748489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 91822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 91922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 92048489980SSeiya Wang clock-names = "main", "dma"; 92148489980SSeiya Wang clock-div = <1>; 92248489980SSeiya Wang #address-cells = <1>; 92348489980SSeiya Wang #size-cells = <0>; 92448489980SSeiya Wang status = "disabled"; 92548489980SSeiya Wang }; 92648489980SSeiya Wang 9277f1a9f47SFabien Parent i2c6: i2c@11f01000 { 92848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 92948489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 93048489980SSeiya Wang <0 0x10217580 0 0x80>; 93148489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 93222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 93322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 93448489980SSeiya Wang clock-names = "main", "dma"; 93548489980SSeiya Wang clock-div = <1>; 93648489980SSeiya Wang #address-cells = <1>; 93748489980SSeiya Wang #size-cells = <0>; 93848489980SSeiya Wang status = "disabled"; 93948489980SSeiya Wang }; 9405d2b897bSChun-Jie Chen 9415d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 9425d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 9435d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 9445d2b897bSChun-Jie Chen #clock-cells = <1>; 9455d2b897bSChun-Jie Chen }; 9465d2b897bSChun-Jie Chen 9475d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 9485d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 9495d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 9505d2b897bSChun-Jie Chen #clock-cells = <1>; 9515d2b897bSChun-Jie Chen }; 9525d2b897bSChun-Jie Chen 9535d2b897bSChun-Jie Chen msdc: clock-controller@11f60000 { 9545d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc"; 9555d2b897bSChun-Jie Chen reg = <0 0x11f60000 0 0x1000>; 9565d2b897bSChun-Jie Chen #clock-cells = <1>; 9575d2b897bSChun-Jie Chen }; 9585d2b897bSChun-Jie Chen 9595d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 9605d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 9615d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 9625d2b897bSChun-Jie Chen #clock-cells = <1>; 9635d2b897bSChun-Jie Chen }; 9645d2b897bSChun-Jie Chen 9655d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 9665d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 9675d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 9685d2b897bSChun-Jie Chen #clock-cells = <1>; 9695d2b897bSChun-Jie Chen }; 9705d2b897bSChun-Jie Chen 9714a65b0f1SAllen-KH Cheng smi_common: smi@14002000 { 9724a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-common"; 9734a65b0f1SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 9744a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 9754a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 9764a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 9774a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>; 9784a65b0f1SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 9794a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 9804a65b0f1SAllen-KH Cheng }; 9814a65b0f1SAllen-KH Cheng 9824a65b0f1SAllen-KH Cheng larb0: larb@14003000 { 9834a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 9844a65b0f1SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 9854a65b0f1SAllen-KH Cheng mediatek,larb-id = <0>; 9864a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 9874a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 9884a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 9894a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 9904a65b0f1SAllen-KH Cheng }; 9914a65b0f1SAllen-KH Cheng 9924a65b0f1SAllen-KH Cheng larb1: larb@14004000 { 9934a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 9944a65b0f1SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 9954a65b0f1SAllen-KH Cheng mediatek,larb-id = <1>; 9964a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 9974a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 9984a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 9994a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 10004a65b0f1SAllen-KH Cheng }; 10014a65b0f1SAllen-KH Cheng 1002*b2edd519SAllen-KH Cheng dpi0: dpi@14016000 { 1003*b2edd519SAllen-KH Cheng compatible = "mediatek,mt8192-dpi"; 1004*b2edd519SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1005*b2edd519SAllen-KH Cheng interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1006*b2edd519SAllen-KH Cheng clocks = <&mmsys CLK_MM_DPI_DPI0>, 1007*b2edd519SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI0>, 1008*b2edd519SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 1009*b2edd519SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 1010*b2edd519SAllen-KH Cheng status = "disabled"; 1011*b2edd519SAllen-KH Cheng }; 1012*b2edd519SAllen-KH Cheng 10134a65b0f1SAllen-KH Cheng iommu0: m4u@1401d000 { 10144a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-m4u"; 10154a65b0f1SAllen-KH Cheng reg = <0 0x1401d000 0 0x1000>; 10164a65b0f1SAllen-KH Cheng mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 10174a65b0f1SAllen-KH Cheng <&larb4>, <&larb5>, <&larb7>, 10184a65b0f1SAllen-KH Cheng <&larb9>, <&larb11>, <&larb13>, 10194a65b0f1SAllen-KH Cheng <&larb14>, <&larb16>, <&larb17>, 10204a65b0f1SAllen-KH Cheng <&larb18>, <&larb19>, <&larb20>; 10214a65b0f1SAllen-KH Cheng interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 10224a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 10234a65b0f1SAllen-KH Cheng clock-names = "bclk"; 10244a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 10254a65b0f1SAllen-KH Cheng #iommu-cells = <1>; 10264a65b0f1SAllen-KH Cheng }; 10274a65b0f1SAllen-KH Cheng 10285d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 10295d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 10305d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 10315d2b897bSChun-Jie Chen #clock-cells = <1>; 10325d2b897bSChun-Jie Chen }; 10335d2b897bSChun-Jie Chen 10344a65b0f1SAllen-KH Cheng larb9: larb@1502e000 { 10354a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 10364a65b0f1SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 10374a65b0f1SAllen-KH Cheng mediatek,larb-id = <9>; 10384a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 10394a65b0f1SAllen-KH Cheng clocks = <&imgsys CLK_IMG_LARB9>, 10404a65b0f1SAllen-KH Cheng <&imgsys CLK_IMG_LARB9>; 10414a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 10424a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 10434a65b0f1SAllen-KH Cheng }; 10444a65b0f1SAllen-KH Cheng 10455d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 10465d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 10475d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 10485d2b897bSChun-Jie Chen #clock-cells = <1>; 10495d2b897bSChun-Jie Chen }; 10505d2b897bSChun-Jie Chen 10514a65b0f1SAllen-KH Cheng larb11: larb@1582e000 { 10524a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 10534a65b0f1SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 10544a65b0f1SAllen-KH Cheng mediatek,larb-id = <11>; 10554a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 10564a65b0f1SAllen-KH Cheng clocks = <&imgsys2 CLK_IMG2_LARB11>, 10574a65b0f1SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB11>; 10584a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 10594a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 10604a65b0f1SAllen-KH Cheng }; 10614a65b0f1SAllen-KH Cheng 10624a65b0f1SAllen-KH Cheng larb5: larb@1600d000 { 10634a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 10644a65b0f1SAllen-KH Cheng reg = <0 0x1600d000 0 0x1000>; 10654a65b0f1SAllen-KH Cheng mediatek,larb-id = <5>; 10664a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 10674a65b0f1SAllen-KH Cheng clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 10684a65b0f1SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 10694a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 10704a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 10714a65b0f1SAllen-KH Cheng }; 10724a65b0f1SAllen-KH Cheng 10735d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 10745d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 10755d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 10765d2b897bSChun-Jie Chen #clock-cells = <1>; 10775d2b897bSChun-Jie Chen }; 10785d2b897bSChun-Jie Chen 10794a65b0f1SAllen-KH Cheng larb4: larb@1602e000 { 10804a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 10814a65b0f1SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 10824a65b0f1SAllen-KH Cheng mediatek,larb-id = <4>; 10834a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 10844a65b0f1SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 10854a65b0f1SAllen-KH Cheng <&vdecsys CLK_VDEC_SOC_LARB1>; 10864a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 10874a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 10884a65b0f1SAllen-KH Cheng }; 10894a65b0f1SAllen-KH Cheng 10905d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 10915d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 10925d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 10935d2b897bSChun-Jie Chen #clock-cells = <1>; 10945d2b897bSChun-Jie Chen }; 10955d2b897bSChun-Jie Chen 10965d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 10975d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 10985d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 10995d2b897bSChun-Jie Chen #clock-cells = <1>; 11005d2b897bSChun-Jie Chen }; 11015d2b897bSChun-Jie Chen 11024a65b0f1SAllen-KH Cheng larb7: larb@17010000 { 11034a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 11044a65b0f1SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 11054a65b0f1SAllen-KH Cheng mediatek,larb-id = <7>; 11064a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 11074a65b0f1SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET0_LARB>, 11084a65b0f1SAllen-KH Cheng <&vencsys CLK_VENC_SET1_VENC>; 11094a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 11104a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 11114a65b0f1SAllen-KH Cheng }; 11124a65b0f1SAllen-KH Cheng 11135d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 11145d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 11155d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 11165d2b897bSChun-Jie Chen #clock-cells = <1>; 11175d2b897bSChun-Jie Chen }; 11185d2b897bSChun-Jie Chen 11194a65b0f1SAllen-KH Cheng larb13: larb@1a001000 { 11204a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 11214a65b0f1SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 11224a65b0f1SAllen-KH Cheng mediatek,larb-id = <13>; 11234a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 11244a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 11254a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB13>; 11264a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 11274a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 11284a65b0f1SAllen-KH Cheng }; 11294a65b0f1SAllen-KH Cheng 11304a65b0f1SAllen-KH Cheng larb14: larb@1a002000 { 11314a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 11324a65b0f1SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 11334a65b0f1SAllen-KH Cheng mediatek,larb-id = <14>; 11344a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 11354a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 11364a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB14>; 11374a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 11384a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 11394a65b0f1SAllen-KH Cheng }; 11404a65b0f1SAllen-KH Cheng 11414a65b0f1SAllen-KH Cheng larb16: larb@1a00f000 { 11424a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 11434a65b0f1SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 11444a65b0f1SAllen-KH Cheng mediatek,larb-id = <16>; 11454a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 11464a65b0f1SAllen-KH Cheng clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 11474a65b0f1SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX>; 11484a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 11494a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 11504a65b0f1SAllen-KH Cheng }; 11514a65b0f1SAllen-KH Cheng 11524a65b0f1SAllen-KH Cheng larb17: larb@1a010000 { 11534a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 11544a65b0f1SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 11554a65b0f1SAllen-KH Cheng mediatek,larb-id = <17>; 11564a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 11574a65b0f1SAllen-KH Cheng clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 11584a65b0f1SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX>; 11594a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 11604a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 11614a65b0f1SAllen-KH Cheng }; 11624a65b0f1SAllen-KH Cheng 11634a65b0f1SAllen-KH Cheng larb18: larb@1a011000 { 11644a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 11654a65b0f1SAllen-KH Cheng reg = <0 0x1a011000 0 0x1000>; 11664a65b0f1SAllen-KH Cheng mediatek,larb-id = <18>; 11674a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 11684a65b0f1SAllen-KH Cheng clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 11694a65b0f1SAllen-KH Cheng <&camsys_rawc CLK_CAM_RAWC_CAM>; 11704a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 11714a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 11724a65b0f1SAllen-KH Cheng }; 11734a65b0f1SAllen-KH Cheng 11745d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 11755d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 11765d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 11775d2b897bSChun-Jie Chen #clock-cells = <1>; 11785d2b897bSChun-Jie Chen }; 11795d2b897bSChun-Jie Chen 11805d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 11815d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 11825d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 11835d2b897bSChun-Jie Chen #clock-cells = <1>; 11845d2b897bSChun-Jie Chen }; 11855d2b897bSChun-Jie Chen 11865d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 11875d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 11885d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 11895d2b897bSChun-Jie Chen #clock-cells = <1>; 11905d2b897bSChun-Jie Chen }; 11915d2b897bSChun-Jie Chen 11925d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 11935d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 11945d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 11955d2b897bSChun-Jie Chen #clock-cells = <1>; 11965d2b897bSChun-Jie Chen }; 11975d2b897bSChun-Jie Chen 11984a65b0f1SAllen-KH Cheng larb20: larb@1b00f000 { 11994a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12004a65b0f1SAllen-KH Cheng reg = <0 0x1b00f000 0 0x1000>; 12014a65b0f1SAllen-KH Cheng mediatek,larb-id = <20>; 12024a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12034a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 12044a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB20>; 12054a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12064a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 12074a65b0f1SAllen-KH Cheng }; 12084a65b0f1SAllen-KH Cheng 12094a65b0f1SAllen-KH Cheng larb19: larb@1b10f000 { 12104a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12114a65b0f1SAllen-KH Cheng reg = <0 0x1b10f000 0 0x1000>; 12124a65b0f1SAllen-KH Cheng mediatek,larb-id = <19>; 12134a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12144a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 12154a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB19>; 12164a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12174a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 12184a65b0f1SAllen-KH Cheng }; 12194a65b0f1SAllen-KH Cheng 12205d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 12215d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 12225d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 12235d2b897bSChun-Jie Chen #clock-cells = <1>; 12245d2b897bSChun-Jie Chen }; 12254a65b0f1SAllen-KH Cheng 12264a65b0f1SAllen-KH Cheng larb2: larb@1f002000 { 12274a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12284a65b0f1SAllen-KH Cheng reg = <0 0x1f002000 0 0x1000>; 12294a65b0f1SAllen-KH Cheng mediatek,larb-id = <2>; 12304a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12314a65b0f1SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, 12324a65b0f1SAllen-KH Cheng <&mdpsys CLK_MDP_SMI0>; 12334a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12344a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 12354a65b0f1SAllen-KH Cheng }; 123648489980SSeiya Wang }; 123748489980SSeiya Wang}; 1238