xref: /openbmc/linux/scripts/dtc/include-prefixes/arm64/mediatek/mt8192.dtsi (revision aa247c07)

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2020 MediaTek Inc.
 * Author: Seiya Wang <seiya.wang@mediatek.com>
 */

/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>

/ {
	compatible = "mediatek,mt8192";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	clk26m: oscillator0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "clk32k";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x000>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
			next-level-cache = <&l2_0>;
			capacity-dmips-mhz = <530>;
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
			next-level-cache = <&l2_0>;
			capacity-dmips-mhz = <530>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x200>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
			next-level-cache = <&l2_0>;
			capacity-dmips-mhz = <530>;
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x300>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
			next-level-cache = <&l2_0>;
			capacity-dmips-mhz = <530>;
		};

		cpu4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x400>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
			next-level-cache = <&l2_1>;
			capacity-dmips-mhz = <1024>;
		};

		cpu5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x500>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
			next-level-cache = <&l2_1>;
			capacity-dmips-mhz = <1024>;
		};

		cpu6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x600>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
			next-level-cache = <&l2_1>;
			capacity-dmips-mhz = <1024>;
		};

		cpu7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x700>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
			next-level-cache = <&l2_1>;
			capacity-dmips-mhz = <1024>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		l2_0: l2-cache0 {
			compatible = "cache";
			next-level-cache = <&l3_0>;
		};

		l2_1: l2-cache1 {
			compatible = "cache";
			next-level-cache = <&l3_0>;
		};

		l3_0: l3-cache {
			compatible = "cache";
		};

		idle-states {
			entry-method = "arm,psci";
			cpuoff_l: cpuoff_l {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x00010001>;
				local-timer-stop;
				entry-latency-us = <55>;
				exit-latency-us = <140>;
				min-residency-us = <780>;
			};
			cpuoff_b: cpuoff_b {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x00010001>;
				local-timer-stop;
				entry-latency-us = <35>;
				exit-latency-us = <145>;
				min-residency-us = <720>;
			};
			clusteroff_l: clusteroff_l {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010002>;
				local-timer-stop;
				entry-latency-us = <60>;
				exit-latency-us = <155>;
				min-residency-us = <860>;
			};
			clusteroff_b: clusteroff_b {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010002>;
				local-timer-stop;
				entry-latency-us = <40>;
				exit-latency-us = <155>;
				min-residency-us = <780>;
			};
		};
	};

	pmu-a55 {
		compatible = "arm,cortex-a55-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
	};

	pmu-a76 {
		compatible = "arm,cortex-a76-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer: timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
		clock-frequency = <13000000>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		gic: interrupt-controller@c000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <4>;
			#redistributor-regions = <1>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x0c000000 0 0x40000>,
			      <0 0x0c040000 0 0x200000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;

			ppi-partitions {
				ppi_cluster0: interrupt-partition-0 {
					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
				};
				ppi_cluster1: interrupt-partition-1 {
					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
				};
			};
		};

		topckgen: syscon@10000000 {
			compatible = "mediatek,mt8192-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: syscon@10001000 {
			compatible = "mediatek,mt8192-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
		};

		pericfg: syscon@10003000 {
			compatible = "mediatek,mt8192-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@10005000 {
			compatible = "mediatek,mt8192-pinctrl";
			reg = <0 0x10005000 0 0x1000>,
			      <0 0x11c20000 0 0x1000>,
			      <0 0x11d10000 0 0x1000>,
			      <0 0x11d30000 0 0x1000>,
			      <0 0x11d40000 0 0x1000>,
			      <0 0x11e20000 0 0x1000>,
			      <0 0x11e70000 0 0x1000>,
			      <0 0x11ea0000 0 0x1000>,
			      <0 0x11f20000 0 0x1000>,
			      <0 0x11f30000 0 0x1000>,
			      <0 0x1000b000 0 0x1000>;
			reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
				    "iocfg_bl", "iocfg_br", "iocfg_lm",
				    "iocfg_lb", "iocfg_rt", "iocfg_lt",
				    "iocfg_tl", "eint";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 220>;
			interrupt-controller;
			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
			#interrupt-cells = <2>;
		};

		apmixedsys: syscon@1000c000 {
			compatible = "mediatek,mt8192-apmixedsys", "syscon";
			reg = <0 0x1000c000 0 0x1000>;
			#clock-cells = <1>;
		};

		systimer: timer@10017000 {
			compatible = "mediatek,mt8192-timer",
				     "mediatek,mt6765-timer";
			reg = <0 0x10017000 0 0x1000>;
			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>;
			clock-names = "clk13m";
		};

		scp_adsp: clock-controller@10720000 {
			compatible = "mediatek,mt8192-scp_adsp";
			reg = <0 0x10720000 0 0x1000>;
			#clock-cells = <1>;
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt8192-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt8192-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		imp_iic_wrap_c: clock-controller@11007000 {
			compatible = "mediatek,mt8192-imp_iic_wrap_c";
			reg = <0 0x11007000 0 0x1000>;
			#clock-cells = <1>;
		};

		spi0: spi@1100a000 {
			compatible = "mediatek,mt8192-spi",
				     "mediatek,mt6765-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x1100a000 0 0x1000>;
			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_SPI0>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi1: spi@11010000 {
			compatible = "mediatek,mt8192-spi",
				     "mediatek,mt6765-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11010000 0 0x1000>;
			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_SPI1>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi2: spi@11012000 {
			compatible = "mediatek,mt8192-spi",
				     "mediatek,mt6765-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11012000 0 0x1000>;
			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_SPI2>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi3: spi@11013000 {
			compatible = "mediatek,mt8192-spi",
				     "mediatek,mt6765-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11013000 0 0x1000>;
			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_SPI3>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi4: spi@11018000 {
			compatible = "mediatek,mt8192-spi",
				     "mediatek,mt6765-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11018000 0 0x1000>;
			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_SPI4>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi5: spi@11019000 {
			compatible = "mediatek,mt8192-spi",
				     "mediatek,mt6765-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11019000 0 0x1000>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_SPI5>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi6: spi@1101d000 {
			compatible = "mediatek,mt8192-spi",
				     "mediatek,mt6765-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x1101d000 0 0x1000>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_SPI6>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi7: spi@1101e000 {
			compatible = "mediatek,mt8192-spi",
				     "mediatek,mt6765-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x1101e000 0 0x1000>;
			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_SPI7>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		nor_flash: spi@11234000 {
			compatible = "mediatek,mt8192-nor";
			reg = <0 0x11234000 0 0xe0>;
			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
				 <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
				 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
			clock-names = "spi", "sf", "axi";
			assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
			assigned-clock-parents = <&clk26m>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disable";
		};

		audsys: clock-controller@11210000 {
			compatible = "mediatek,mt8192-audsys", "syscon";
			reg = <0 0x11210000 0 0x1000>;
			#clock-cells = <1>;
		};

		i2c3: i2c@11cb0000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11cb0000 0 0x1000>,
			      <0 0x10217300 0 0x80>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		imp_iic_wrap_e: clock-controller@11cb1000 {
			compatible = "mediatek,mt8192-imp_iic_wrap_e";
			reg = <0 0x11cb1000 0 0x1000>;
			#clock-cells = <1>;
		};

		i2c7: i2c@11d00000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11d00000 0 0x1000>,
			      <0 0x10217600 0 0x180>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c8: i2c@11d01000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11d01000 0 0x1000>,
			      <0 0x10217780 0 0x180>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c9: i2c@11d02000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11d02000 0 0x1000>,
			      <0 0x10217900 0 0x180>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		imp_iic_wrap_s: clock-controller@11d03000 {
			compatible = "mediatek,mt8192-imp_iic_wrap_s";
			reg = <0 0x11d03000 0 0x1000>;
			#clock-cells = <1>;
		};

		i2c1: i2c@11d20000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11d20000 0 0x1000>,
			      <0 0x10217100 0 0x80>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@11d21000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11d21000 0 0x1000>,
			      <0 0x10217180 0 0x180>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@11d22000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11d22000 0 0x1000>,
			      <0 0x10217380 0 0x180>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		imp_iic_wrap_ws: clock-controller@11d23000 {
			compatible = "mediatek,mt8192-imp_iic_wrap_ws";
			reg = <0 0x11d23000 0 0x1000>;
			#clock-cells = <1>;
		};

		i2c5: i2c@11e00000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11e00000 0 0x1000>,
			      <0 0x10217500 0 0x80>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		imp_iic_wrap_w: clock-controller@11e01000 {
			compatible = "mediatek,mt8192-imp_iic_wrap_w";
			reg = <0 0x11e01000 0 0x1000>;
			#clock-cells = <1>;
		};

		i2c0: i2c@11f00000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11f00000 0 0x1000>,
			      <0 0x10217080 0 0x80>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c6: i2c@11f01000 {
			compatible = "mediatek,mt8192-i2c";
			reg = <0 0x11f01000 0 0x1000>,
			      <0 0x10217580 0 0x80>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		imp_iic_wrap_n: clock-controller@11f02000 {
			compatible = "mediatek,mt8192-imp_iic_wrap_n";
			reg = <0 0x11f02000 0 0x1000>;
			#clock-cells = <1>;
		};

		msdc_top: clock-controller@11f10000 {
			compatible = "mediatek,mt8192-msdc_top";
			reg = <0 0x11f10000 0 0x1000>;
			#clock-cells = <1>;
		};

		msdc: clock-controller@11f60000 {
			compatible = "mediatek,mt8192-msdc";
			reg = <0 0x11f60000 0 0x1000>;
			#clock-cells = <1>;
		};

		mfgcfg: clock-controller@13fbf000 {
			compatible = "mediatek,mt8192-mfgcfg";
			reg = <0 0x13fbf000 0 0x1000>;
			#clock-cells = <1>;
		};

		mmsys: syscon@14000000 {
			compatible = "mediatek,mt8192-mmsys", "syscon";
			reg = <0 0x14000000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys: clock-controller@15020000 {
			compatible = "mediatek,mt8192-imgsys";
			reg = <0 0x15020000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys2: clock-controller@15820000 {
			compatible = "mediatek,mt8192-imgsys2";
			reg = <0 0x15820000 0 0x1000>;
			#clock-cells = <1>;
		};

		vdecsys_soc: clock-controller@1600f000 {
			compatible = "mediatek,mt8192-vdecsys_soc";
			reg = <0 0x1600f000 0 0x1000>;
			#clock-cells = <1>;
		};

		vdecsys: clock-controller@1602f000 {
			compatible = "mediatek,mt8192-vdecsys";
			reg = <0 0x1602f000 0 0x1000>;
			#clock-cells = <1>;
		};

		vencsys: clock-controller@17000000 {
			compatible = "mediatek,mt8192-vencsys";
			reg = <0 0x17000000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys: clock-controller@1a000000 {
			compatible = "mediatek,mt8192-camsys";
			reg = <0 0x1a000000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys_rawa: clock-controller@1a04f000 {
			compatible = "mediatek,mt8192-camsys_rawa";
			reg = <0 0x1a04f000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys_rawb: clock-controller@1a06f000 {
			compatible = "mediatek,mt8192-camsys_rawb";
			reg = <0 0x1a06f000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys_rawc: clock-controller@1a08f000 {
			compatible = "mediatek,mt8192-camsys_rawc";
			reg = <0 0x1a08f000 0 0x1000>;
			#clock-cells = <1>;
		};

		ipesys: clock-controller@1b000000 {
			compatible = "mediatek,mt8192-ipesys";
			reg = <0 0x1b000000 0 0x1000>;
			#clock-cells = <1>;
		};

		mdpsys: clock-controller@1f000000 {
			compatible = "mediatek,mt8192-mdpsys";
			reg = <0 0x1f000000 0 0x1000>;
			#clock-cells = <1>;
		};
	};
};