148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT)
248489980SSeiya Wang/*
348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc.
448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com>
548489980SSeiya Wang */
648489980SSeiya Wang
748489980SSeiya Wang/dts-v1/;
85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h>
948489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h>
1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h>
114a65b0f1SAllen-KH Cheng#include <dt-bindings/memory/mt8192-larb-port.h>
1248489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
13e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h>
14994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h>
1548489980SSeiya Wang
1648489980SSeiya Wang/ {
1748489980SSeiya Wang	compatible = "mediatek,mt8192";
1848489980SSeiya Wang	interrupt-parent = <&gic>;
1948489980SSeiya Wang	#address-cells = <2>;
2048489980SSeiya Wang	#size-cells = <2>;
2148489980SSeiya Wang
2248489980SSeiya Wang	clk26m: oscillator0 {
2348489980SSeiya Wang		compatible = "fixed-clock";
2448489980SSeiya Wang		#clock-cells = <0>;
2548489980SSeiya Wang		clock-frequency = <26000000>;
2648489980SSeiya Wang		clock-output-names = "clk26m";
2748489980SSeiya Wang	};
2848489980SSeiya Wang
2948489980SSeiya Wang	clk32k: oscillator1 {
3048489980SSeiya Wang		compatible = "fixed-clock";
3148489980SSeiya Wang		#clock-cells = <0>;
3248489980SSeiya Wang		clock-frequency = <32768>;
3348489980SSeiya Wang		clock-output-names = "clk32k";
3448489980SSeiya Wang	};
3548489980SSeiya Wang
3648489980SSeiya Wang	cpus {
3748489980SSeiya Wang		#address-cells = <1>;
3848489980SSeiya Wang		#size-cells = <0>;
3948489980SSeiya Wang
4048489980SSeiya Wang		cpu0: cpu@0 {
4148489980SSeiya Wang			device_type = "cpu";
4248489980SSeiya Wang			compatible = "arm,cortex-a55";
4348489980SSeiya Wang			reg = <0x000>;
4448489980SSeiya Wang			enable-method = "psci";
4548489980SSeiya Wang			clock-frequency = <1701000000>;
469260918dSJames Liao			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
4748489980SSeiya Wang			next-level-cache = <&l2_0>;
4848489980SSeiya Wang			capacity-dmips-mhz = <530>;
4948489980SSeiya Wang		};
5048489980SSeiya Wang
5148489980SSeiya Wang		cpu1: cpu@100 {
5248489980SSeiya Wang			device_type = "cpu";
5348489980SSeiya Wang			compatible = "arm,cortex-a55";
5448489980SSeiya Wang			reg = <0x100>;
5548489980SSeiya Wang			enable-method = "psci";
5648489980SSeiya Wang			clock-frequency = <1701000000>;
579260918dSJames Liao			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
5848489980SSeiya Wang			next-level-cache = <&l2_0>;
5948489980SSeiya Wang			capacity-dmips-mhz = <530>;
6048489980SSeiya Wang		};
6148489980SSeiya Wang
6248489980SSeiya Wang		cpu2: cpu@200 {
6348489980SSeiya Wang			device_type = "cpu";
6448489980SSeiya Wang			compatible = "arm,cortex-a55";
6548489980SSeiya Wang			reg = <0x200>;
6648489980SSeiya Wang			enable-method = "psci";
6748489980SSeiya Wang			clock-frequency = <1701000000>;
689260918dSJames Liao			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
6948489980SSeiya Wang			next-level-cache = <&l2_0>;
7048489980SSeiya Wang			capacity-dmips-mhz = <530>;
7148489980SSeiya Wang		};
7248489980SSeiya Wang
7348489980SSeiya Wang		cpu3: cpu@300 {
7448489980SSeiya Wang			device_type = "cpu";
7548489980SSeiya Wang			compatible = "arm,cortex-a55";
7648489980SSeiya Wang			reg = <0x300>;
7748489980SSeiya Wang			enable-method = "psci";
7848489980SSeiya Wang			clock-frequency = <1701000000>;
799260918dSJames Liao			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
8048489980SSeiya Wang			next-level-cache = <&l2_0>;
8148489980SSeiya Wang			capacity-dmips-mhz = <530>;
8248489980SSeiya Wang		};
8348489980SSeiya Wang
8448489980SSeiya Wang		cpu4: cpu@400 {
8548489980SSeiya Wang			device_type = "cpu";
8648489980SSeiya Wang			compatible = "arm,cortex-a76";
8748489980SSeiya Wang			reg = <0x400>;
8848489980SSeiya Wang			enable-method = "psci";
8948489980SSeiya Wang			clock-frequency = <2171000000>;
909260918dSJames Liao			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
9148489980SSeiya Wang			next-level-cache = <&l2_1>;
9248489980SSeiya Wang			capacity-dmips-mhz = <1024>;
9348489980SSeiya Wang		};
9448489980SSeiya Wang
9548489980SSeiya Wang		cpu5: cpu@500 {
9648489980SSeiya Wang			device_type = "cpu";
9748489980SSeiya Wang			compatible = "arm,cortex-a76";
9848489980SSeiya Wang			reg = <0x500>;
9948489980SSeiya Wang			enable-method = "psci";
10048489980SSeiya Wang			clock-frequency = <2171000000>;
1019260918dSJames Liao			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
10248489980SSeiya Wang			next-level-cache = <&l2_1>;
10348489980SSeiya Wang			capacity-dmips-mhz = <1024>;
10448489980SSeiya Wang		};
10548489980SSeiya Wang
10648489980SSeiya Wang		cpu6: cpu@600 {
10748489980SSeiya Wang			device_type = "cpu";
10848489980SSeiya Wang			compatible = "arm,cortex-a76";
10948489980SSeiya Wang			reg = <0x600>;
11048489980SSeiya Wang			enable-method = "psci";
11148489980SSeiya Wang			clock-frequency = <2171000000>;
1129260918dSJames Liao			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
11348489980SSeiya Wang			next-level-cache = <&l2_1>;
11448489980SSeiya Wang			capacity-dmips-mhz = <1024>;
11548489980SSeiya Wang		};
11648489980SSeiya Wang
11748489980SSeiya Wang		cpu7: cpu@700 {
11848489980SSeiya Wang			device_type = "cpu";
11948489980SSeiya Wang			compatible = "arm,cortex-a76";
12048489980SSeiya Wang			reg = <0x700>;
12148489980SSeiya Wang			enable-method = "psci";
12248489980SSeiya Wang			clock-frequency = <2171000000>;
1239260918dSJames Liao			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
12448489980SSeiya Wang			next-level-cache = <&l2_1>;
12548489980SSeiya Wang			capacity-dmips-mhz = <1024>;
12648489980SSeiya Wang		};
12748489980SSeiya Wang
12848489980SSeiya Wang		cpu-map {
12948489980SSeiya Wang			cluster0 {
13048489980SSeiya Wang				core0 {
13148489980SSeiya Wang					cpu = <&cpu0>;
13248489980SSeiya Wang				};
13348489980SSeiya Wang				core1 {
13448489980SSeiya Wang					cpu = <&cpu1>;
13548489980SSeiya Wang				};
13648489980SSeiya Wang				core2 {
13748489980SSeiya Wang					cpu = <&cpu2>;
13848489980SSeiya Wang				};
13948489980SSeiya Wang				core3 {
14048489980SSeiya Wang					cpu = <&cpu3>;
14148489980SSeiya Wang				};
14248489980SSeiya Wang			};
14348489980SSeiya Wang
14448489980SSeiya Wang			cluster1 {
14548489980SSeiya Wang				core0 {
14648489980SSeiya Wang					cpu = <&cpu4>;
14748489980SSeiya Wang				};
14848489980SSeiya Wang				core1 {
14948489980SSeiya Wang					cpu = <&cpu5>;
15048489980SSeiya Wang				};
15148489980SSeiya Wang				core2 {
15248489980SSeiya Wang					cpu = <&cpu6>;
15348489980SSeiya Wang				};
15448489980SSeiya Wang				core3 {
15548489980SSeiya Wang					cpu = <&cpu7>;
15648489980SSeiya Wang				};
15748489980SSeiya Wang			};
15848489980SSeiya Wang		};
15948489980SSeiya Wang
16048489980SSeiya Wang		l2_0: l2-cache0 {
16148489980SSeiya Wang			compatible = "cache";
16248489980SSeiya Wang			next-level-cache = <&l3_0>;
16348489980SSeiya Wang		};
16448489980SSeiya Wang
16548489980SSeiya Wang		l2_1: l2-cache1 {
16648489980SSeiya Wang			compatible = "cache";
16748489980SSeiya Wang			next-level-cache = <&l3_0>;
16848489980SSeiya Wang		};
16948489980SSeiya Wang
17048489980SSeiya Wang		l3_0: l3-cache {
17148489980SSeiya Wang			compatible = "cache";
17248489980SSeiya Wang		};
1739260918dSJames Liao
1749260918dSJames Liao		idle-states {
1759260918dSJames Liao			entry-method = "arm,psci";
1769260918dSJames Liao			cpuoff_l: cpuoff_l {
1779260918dSJames Liao				compatible = "arm,idle-state";
1789260918dSJames Liao				arm,psci-suspend-param = <0x00010001>;
1799260918dSJames Liao				local-timer-stop;
1809260918dSJames Liao				entry-latency-us = <55>;
1819260918dSJames Liao				exit-latency-us = <140>;
1829260918dSJames Liao				min-residency-us = <780>;
1839260918dSJames Liao			};
1849260918dSJames Liao			cpuoff_b: cpuoff_b {
1859260918dSJames Liao				compatible = "arm,idle-state";
1869260918dSJames Liao				arm,psci-suspend-param = <0x00010001>;
1879260918dSJames Liao				local-timer-stop;
1889260918dSJames Liao				entry-latency-us = <35>;
1899260918dSJames Liao				exit-latency-us = <145>;
1909260918dSJames Liao				min-residency-us = <720>;
1919260918dSJames Liao			};
1929260918dSJames Liao			clusteroff_l: clusteroff_l {
1939260918dSJames Liao				compatible = "arm,idle-state";
1949260918dSJames Liao				arm,psci-suspend-param = <0x01010002>;
1959260918dSJames Liao				local-timer-stop;
1969260918dSJames Liao				entry-latency-us = <60>;
1979260918dSJames Liao				exit-latency-us = <155>;
1989260918dSJames Liao				min-residency-us = <860>;
1999260918dSJames Liao			};
2009260918dSJames Liao			clusteroff_b: clusteroff_b {
2019260918dSJames Liao				compatible = "arm,idle-state";
2029260918dSJames Liao				arm,psci-suspend-param = <0x01010002>;
2039260918dSJames Liao				local-timer-stop;
2049260918dSJames Liao				entry-latency-us = <40>;
2059260918dSJames Liao				exit-latency-us = <155>;
2069260918dSJames Liao				min-residency-us = <780>;
2079260918dSJames Liao			};
2089260918dSJames Liao		};
20948489980SSeiya Wang	};
21048489980SSeiya Wang
21148489980SSeiya Wang	pmu-a55 {
21248489980SSeiya Wang		compatible = "arm,cortex-a55-pmu";
21348489980SSeiya Wang		interrupt-parent = <&gic>;
21448489980SSeiya Wang		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
21548489980SSeiya Wang	};
21648489980SSeiya Wang
21748489980SSeiya Wang	pmu-a76 {
21848489980SSeiya Wang		compatible = "arm,cortex-a76-pmu";
21948489980SSeiya Wang		interrupt-parent = <&gic>;
22048489980SSeiya Wang		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
22148489980SSeiya Wang	};
22248489980SSeiya Wang
22348489980SSeiya Wang	psci {
22448489980SSeiya Wang		compatible = "arm,psci-1.0";
22548489980SSeiya Wang		method = "smc";
22648489980SSeiya Wang	};
22748489980SSeiya Wang
22848489980SSeiya Wang	timer: timer {
22948489980SSeiya Wang		compatible = "arm,armv8-timer";
23048489980SSeiya Wang		interrupt-parent = <&gic>;
23148489980SSeiya Wang		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
23248489980SSeiya Wang			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
23348489980SSeiya Wang			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
23448489980SSeiya Wang			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
23548489980SSeiya Wang		clock-frequency = <13000000>;
23648489980SSeiya Wang	};
23748489980SSeiya Wang
23848489980SSeiya Wang	soc {
23948489980SSeiya Wang		#address-cells = <2>;
24048489980SSeiya Wang		#size-cells = <2>;
24148489980SSeiya Wang		compatible = "simple-bus";
24248489980SSeiya Wang		ranges;
24348489980SSeiya Wang
24448489980SSeiya Wang		gic: interrupt-controller@c000000 {
24548489980SSeiya Wang			compatible = "arm,gic-v3";
24648489980SSeiya Wang			#interrupt-cells = <4>;
24748489980SSeiya Wang			#redistributor-regions = <1>;
24848489980SSeiya Wang			interrupt-parent = <&gic>;
24948489980SSeiya Wang			interrupt-controller;
25048489980SSeiya Wang			reg = <0 0x0c000000 0 0x40000>,
25148489980SSeiya Wang			      <0 0x0c040000 0 0x200000>;
25248489980SSeiya Wang			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
25348489980SSeiya Wang
25448489980SSeiya Wang			ppi-partitions {
25548489980SSeiya Wang				ppi_cluster0: interrupt-partition-0 {
25648489980SSeiya Wang					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
25748489980SSeiya Wang				};
25848489980SSeiya Wang				ppi_cluster1: interrupt-partition-1 {
25948489980SSeiya Wang					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
26048489980SSeiya Wang				};
26148489980SSeiya Wang			};
26248489980SSeiya Wang		};
26348489980SSeiya Wang
2645d2b897bSChun-Jie Chen		topckgen: syscon@10000000 {
2655d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-topckgen", "syscon";
2665d2b897bSChun-Jie Chen			reg = <0 0x10000000 0 0x1000>;
2675d2b897bSChun-Jie Chen			#clock-cells = <1>;
2685d2b897bSChun-Jie Chen		};
2695d2b897bSChun-Jie Chen
2705d2b897bSChun-Jie Chen		infracfg: syscon@10001000 {
2715d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-infracfg", "syscon";
2725d2b897bSChun-Jie Chen			reg = <0 0x10001000 0 0x1000>;
2735d2b897bSChun-Jie Chen			#clock-cells = <1>;
2745d2b897bSChun-Jie Chen		};
2755d2b897bSChun-Jie Chen
2765d2b897bSChun-Jie Chen		pericfg: syscon@10003000 {
2775d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-pericfg", "syscon";
2785d2b897bSChun-Jie Chen			reg = <0 0x10003000 0 0x1000>;
2795d2b897bSChun-Jie Chen			#clock-cells = <1>;
2805d2b897bSChun-Jie Chen		};
2815d2b897bSChun-Jie Chen
28248489980SSeiya Wang		pio: pinctrl@10005000 {
28348489980SSeiya Wang			compatible = "mediatek,mt8192-pinctrl";
28448489980SSeiya Wang			reg = <0 0x10005000 0 0x1000>,
28548489980SSeiya Wang			      <0 0x11c20000 0 0x1000>,
28648489980SSeiya Wang			      <0 0x11d10000 0 0x1000>,
28748489980SSeiya Wang			      <0 0x11d30000 0 0x1000>,
28848489980SSeiya Wang			      <0 0x11d40000 0 0x1000>,
28948489980SSeiya Wang			      <0 0x11e20000 0 0x1000>,
29048489980SSeiya Wang			      <0 0x11e70000 0 0x1000>,
29148489980SSeiya Wang			      <0 0x11ea0000 0 0x1000>,
29248489980SSeiya Wang			      <0 0x11f20000 0 0x1000>,
29348489980SSeiya Wang			      <0 0x11f30000 0 0x1000>,
29448489980SSeiya Wang			      <0 0x1000b000 0 0x1000>;
29548489980SSeiya Wang			reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
29648489980SSeiya Wang				    "iocfg_bl", "iocfg_br", "iocfg_lm",
29748489980SSeiya Wang				    "iocfg_lb", "iocfg_rt", "iocfg_lt",
29848489980SSeiya Wang				    "iocfg_tl", "eint";
29948489980SSeiya Wang			gpio-controller;
30048489980SSeiya Wang			#gpio-cells = <2>;
30148489980SSeiya Wang			gpio-ranges = <&pio 0 0 220>;
30248489980SSeiya Wang			interrupt-controller;
30348489980SSeiya Wang			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
30448489980SSeiya Wang			#interrupt-cells = <2>;
30548489980SSeiya Wang		};
30648489980SSeiya Wang
307994a71a3SChun-Jie Chen		scpsys: syscon@10006000 {
308994a71a3SChun-Jie Chen			compatible = "syscon", "simple-mfd";
309994a71a3SChun-Jie Chen			reg = <0 0x10006000 0 0x1000>;
310994a71a3SChun-Jie Chen			#power-domain-cells = <1>;
311994a71a3SChun-Jie Chen
312994a71a3SChun-Jie Chen			/* System Power Manager */
313994a71a3SChun-Jie Chen			spm: power-controller {
314994a71a3SChun-Jie Chen				compatible = "mediatek,mt8192-power-controller";
315994a71a3SChun-Jie Chen				#address-cells = <1>;
316994a71a3SChun-Jie Chen				#size-cells = <0>;
317994a71a3SChun-Jie Chen				#power-domain-cells = <1>;
318994a71a3SChun-Jie Chen
319994a71a3SChun-Jie Chen				/* power domain of the SoC */
320994a71a3SChun-Jie Chen				power-domain@MT8192_POWER_DOMAIN_AUDIO {
321994a71a3SChun-Jie Chen					reg = <MT8192_POWER_DOMAIN_AUDIO>;
322994a71a3SChun-Jie Chen					clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
323994a71a3SChun-Jie Chen						 <&infracfg CLK_INFRA_AUDIO_26M_B>,
324994a71a3SChun-Jie Chen						 <&infracfg CLK_INFRA_AUDIO>;
325994a71a3SChun-Jie Chen					clock-names = "audio", "audio1", "audio2";
326994a71a3SChun-Jie Chen					mediatek,infracfg = <&infracfg>;
327994a71a3SChun-Jie Chen					#power-domain-cells = <0>;
328994a71a3SChun-Jie Chen				};
329994a71a3SChun-Jie Chen
330994a71a3SChun-Jie Chen				power-domain@MT8192_POWER_DOMAIN_CONN {
331994a71a3SChun-Jie Chen					reg = <MT8192_POWER_DOMAIN_CONN>;
332994a71a3SChun-Jie Chen					clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
333994a71a3SChun-Jie Chen					clock-names = "conn";
334994a71a3SChun-Jie Chen					mediatek,infracfg = <&infracfg>;
335994a71a3SChun-Jie Chen					#power-domain-cells = <0>;
336994a71a3SChun-Jie Chen				};
337994a71a3SChun-Jie Chen
338994a71a3SChun-Jie Chen				power-domain@MT8192_POWER_DOMAIN_MFG0 {
339994a71a3SChun-Jie Chen					reg = <MT8192_POWER_DOMAIN_MFG0>;
340994a71a3SChun-Jie Chen					clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
341994a71a3SChun-Jie Chen					clock-names = "mfg";
342994a71a3SChun-Jie Chen					#address-cells = <1>;
343994a71a3SChun-Jie Chen					#size-cells = <0>;
344994a71a3SChun-Jie Chen					#power-domain-cells = <1>;
345994a71a3SChun-Jie Chen
346994a71a3SChun-Jie Chen					power-domain@MT8192_POWER_DOMAIN_MFG1 {
347994a71a3SChun-Jie Chen						reg = <MT8192_POWER_DOMAIN_MFG1>;
348994a71a3SChun-Jie Chen						mediatek,infracfg = <&infracfg>;
349994a71a3SChun-Jie Chen						#address-cells = <1>;
350994a71a3SChun-Jie Chen						#size-cells = <0>;
351994a71a3SChun-Jie Chen						#power-domain-cells = <1>;
352994a71a3SChun-Jie Chen
353994a71a3SChun-Jie Chen						power-domain@MT8192_POWER_DOMAIN_MFG2 {
354994a71a3SChun-Jie Chen							reg = <MT8192_POWER_DOMAIN_MFG2>;
355994a71a3SChun-Jie Chen							#power-domain-cells = <0>;
356994a71a3SChun-Jie Chen						};
357994a71a3SChun-Jie Chen
358994a71a3SChun-Jie Chen						power-domain@MT8192_POWER_DOMAIN_MFG3 {
359994a71a3SChun-Jie Chen							reg = <MT8192_POWER_DOMAIN_MFG3>;
360994a71a3SChun-Jie Chen							#power-domain-cells = <0>;
361994a71a3SChun-Jie Chen						};
362994a71a3SChun-Jie Chen
363994a71a3SChun-Jie Chen						power-domain@MT8192_POWER_DOMAIN_MFG4 {
364994a71a3SChun-Jie Chen							reg = <MT8192_POWER_DOMAIN_MFG4>;
365994a71a3SChun-Jie Chen							#power-domain-cells = <0>;
366994a71a3SChun-Jie Chen						};
367994a71a3SChun-Jie Chen
368994a71a3SChun-Jie Chen						power-domain@MT8192_POWER_DOMAIN_MFG5 {
369994a71a3SChun-Jie Chen							reg = <MT8192_POWER_DOMAIN_MFG5>;
370994a71a3SChun-Jie Chen							#power-domain-cells = <0>;
371994a71a3SChun-Jie Chen						};
372994a71a3SChun-Jie Chen
373994a71a3SChun-Jie Chen						power-domain@MT8192_POWER_DOMAIN_MFG6 {
374994a71a3SChun-Jie Chen							reg = <MT8192_POWER_DOMAIN_MFG6>;
375994a71a3SChun-Jie Chen							#power-domain-cells = <0>;
376994a71a3SChun-Jie Chen						};
377994a71a3SChun-Jie Chen					};
378994a71a3SChun-Jie Chen				};
379994a71a3SChun-Jie Chen
380994a71a3SChun-Jie Chen				power-domain@MT8192_POWER_DOMAIN_DISP {
381994a71a3SChun-Jie Chen					reg = <MT8192_POWER_DOMAIN_DISP>;
382994a71a3SChun-Jie Chen					clocks = <&topckgen CLK_TOP_DISP_SEL>,
383994a71a3SChun-Jie Chen						 <&mmsys CLK_MM_SMI_INFRA>,
384994a71a3SChun-Jie Chen						 <&mmsys CLK_MM_SMI_COMMON>,
385994a71a3SChun-Jie Chen						 <&mmsys CLK_MM_SMI_GALS>,
386994a71a3SChun-Jie Chen						 <&mmsys CLK_MM_SMI_IOMMU>;
387994a71a3SChun-Jie Chen					clock-names = "disp", "disp-0", "disp-1", "disp-2",
388994a71a3SChun-Jie Chen						      "disp-3";
389994a71a3SChun-Jie Chen					mediatek,infracfg = <&infracfg>;
390994a71a3SChun-Jie Chen					#address-cells = <1>;
391994a71a3SChun-Jie Chen					#size-cells = <0>;
392994a71a3SChun-Jie Chen					#power-domain-cells = <1>;
393994a71a3SChun-Jie Chen
394994a71a3SChun-Jie Chen					power-domain@MT8192_POWER_DOMAIN_IPE {
395994a71a3SChun-Jie Chen						reg = <MT8192_POWER_DOMAIN_IPE>;
396994a71a3SChun-Jie Chen						clocks = <&topckgen CLK_TOP_IPE_SEL>,
397994a71a3SChun-Jie Chen							 <&ipesys CLK_IPE_LARB19>,
398994a71a3SChun-Jie Chen							 <&ipesys CLK_IPE_LARB20>,
399994a71a3SChun-Jie Chen							 <&ipesys CLK_IPE_SMI_SUBCOM>,
400994a71a3SChun-Jie Chen							 <&ipesys CLK_IPE_GALS>;
401994a71a3SChun-Jie Chen						clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
402994a71a3SChun-Jie Chen							      "ipe-3";
403994a71a3SChun-Jie Chen						mediatek,infracfg = <&infracfg>;
404994a71a3SChun-Jie Chen						#power-domain-cells = <0>;
405994a71a3SChun-Jie Chen					};
406994a71a3SChun-Jie Chen
407994a71a3SChun-Jie Chen					power-domain@MT8192_POWER_DOMAIN_ISP {
408994a71a3SChun-Jie Chen						reg = <MT8192_POWER_DOMAIN_ISP>;
409994a71a3SChun-Jie Chen						clocks = <&topckgen CLK_TOP_IMG1_SEL>,
410994a71a3SChun-Jie Chen							 <&imgsys CLK_IMG_LARB9>,
411994a71a3SChun-Jie Chen							 <&imgsys CLK_IMG_GALS>;
412994a71a3SChun-Jie Chen						clock-names = "isp", "isp-0", "isp-1";
413994a71a3SChun-Jie Chen						mediatek,infracfg = <&infracfg>;
414994a71a3SChun-Jie Chen						#power-domain-cells = <0>;
415994a71a3SChun-Jie Chen					};
416994a71a3SChun-Jie Chen
417994a71a3SChun-Jie Chen					power-domain@MT8192_POWER_DOMAIN_ISP2 {
418994a71a3SChun-Jie Chen						reg = <MT8192_POWER_DOMAIN_ISP2>;
419994a71a3SChun-Jie Chen						clocks = <&topckgen CLK_TOP_IMG2_SEL>,
420994a71a3SChun-Jie Chen							 <&imgsys2 CLK_IMG2_LARB11>,
421994a71a3SChun-Jie Chen							 <&imgsys2 CLK_IMG2_GALS>;
422994a71a3SChun-Jie Chen						clock-names = "isp2", "isp2-0", "isp2-1";
423994a71a3SChun-Jie Chen						mediatek,infracfg = <&infracfg>;
424994a71a3SChun-Jie Chen						#power-domain-cells = <0>;
425994a71a3SChun-Jie Chen					};
426994a71a3SChun-Jie Chen
427994a71a3SChun-Jie Chen					power-domain@MT8192_POWER_DOMAIN_MDP {
428994a71a3SChun-Jie Chen						reg = <MT8192_POWER_DOMAIN_MDP>;
429994a71a3SChun-Jie Chen						clocks = <&topckgen CLK_TOP_MDP_SEL>,
430994a71a3SChun-Jie Chen							 <&mdpsys CLK_MDP_SMI0>;
431994a71a3SChun-Jie Chen						clock-names = "mdp", "mdp-0";
432994a71a3SChun-Jie Chen						mediatek,infracfg = <&infracfg>;
433994a71a3SChun-Jie Chen						#power-domain-cells = <0>;
434994a71a3SChun-Jie Chen					};
435994a71a3SChun-Jie Chen
436994a71a3SChun-Jie Chen					power-domain@MT8192_POWER_DOMAIN_VENC {
437994a71a3SChun-Jie Chen						reg = <MT8192_POWER_DOMAIN_VENC>;
438994a71a3SChun-Jie Chen						clocks = <&topckgen CLK_TOP_VENC_SEL>,
439994a71a3SChun-Jie Chen							 <&vencsys CLK_VENC_SET1_VENC>;
440994a71a3SChun-Jie Chen						clock-names = "venc", "venc-0";
441994a71a3SChun-Jie Chen						mediatek,infracfg = <&infracfg>;
442994a71a3SChun-Jie Chen						#power-domain-cells = <0>;
443994a71a3SChun-Jie Chen					};
444994a71a3SChun-Jie Chen
445994a71a3SChun-Jie Chen					power-domain@MT8192_POWER_DOMAIN_VDEC {
446994a71a3SChun-Jie Chen						reg = <MT8192_POWER_DOMAIN_VDEC>;
447994a71a3SChun-Jie Chen						clocks = <&topckgen CLK_TOP_VDEC_SEL>,
448994a71a3SChun-Jie Chen							 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
449994a71a3SChun-Jie Chen							 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
450994a71a3SChun-Jie Chen							 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
451994a71a3SChun-Jie Chen						clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
452994a71a3SChun-Jie Chen						mediatek,infracfg = <&infracfg>;
453994a71a3SChun-Jie Chen						#address-cells = <1>;
454994a71a3SChun-Jie Chen						#size-cells = <0>;
455994a71a3SChun-Jie Chen						#power-domain-cells = <1>;
456994a71a3SChun-Jie Chen
457994a71a3SChun-Jie Chen						power-domain@MT8192_POWER_DOMAIN_VDEC2 {
458994a71a3SChun-Jie Chen							reg = <MT8192_POWER_DOMAIN_VDEC2>;
459994a71a3SChun-Jie Chen							clocks = <&vdecsys CLK_VDEC_VDEC>,
460994a71a3SChun-Jie Chen								 <&vdecsys CLK_VDEC_LAT>,
461994a71a3SChun-Jie Chen								 <&vdecsys CLK_VDEC_LARB1>;
462994a71a3SChun-Jie Chen							clock-names = "vdec2-0", "vdec2-1",
463994a71a3SChun-Jie Chen								      "vdec2-2";
464994a71a3SChun-Jie Chen							#power-domain-cells = <0>;
465994a71a3SChun-Jie Chen						};
466994a71a3SChun-Jie Chen					};
467994a71a3SChun-Jie Chen
468994a71a3SChun-Jie Chen					power-domain@MT8192_POWER_DOMAIN_CAM {
469994a71a3SChun-Jie Chen						reg = <MT8192_POWER_DOMAIN_CAM>;
470994a71a3SChun-Jie Chen						clocks = <&topckgen CLK_TOP_CAM_SEL>,
471994a71a3SChun-Jie Chen							 <&camsys CLK_CAM_LARB13>,
472994a71a3SChun-Jie Chen							 <&camsys CLK_CAM_LARB14>,
473994a71a3SChun-Jie Chen							 <&camsys CLK_CAM_CCU_GALS>,
474994a71a3SChun-Jie Chen							 <&camsys CLK_CAM_CAM2MM_GALS>;
475994a71a3SChun-Jie Chen						clock-names = "cam", "cam-0", "cam-1", "cam-2",
476994a71a3SChun-Jie Chen							      "cam-3";
477994a71a3SChun-Jie Chen						mediatek,infracfg = <&infracfg>;
478994a71a3SChun-Jie Chen						#address-cells = <1>;
479994a71a3SChun-Jie Chen						#size-cells = <0>;
480994a71a3SChun-Jie Chen						#power-domain-cells = <1>;
481994a71a3SChun-Jie Chen
482994a71a3SChun-Jie Chen						power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
483994a71a3SChun-Jie Chen							reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
484994a71a3SChun-Jie Chen							clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
485994a71a3SChun-Jie Chen							clock-names = "cam_rawa-0";
486994a71a3SChun-Jie Chen							#power-domain-cells = <0>;
487994a71a3SChun-Jie Chen						};
488994a71a3SChun-Jie Chen
489994a71a3SChun-Jie Chen						power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
490994a71a3SChun-Jie Chen							reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
491994a71a3SChun-Jie Chen							clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
492994a71a3SChun-Jie Chen							clock-names = "cam_rawb-0";
493994a71a3SChun-Jie Chen							#power-domain-cells = <0>;
494994a71a3SChun-Jie Chen						};
495994a71a3SChun-Jie Chen
496994a71a3SChun-Jie Chen						power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
497994a71a3SChun-Jie Chen							reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
498994a71a3SChun-Jie Chen							clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
499994a71a3SChun-Jie Chen							clock-names = "cam_rawc-0";
500994a71a3SChun-Jie Chen							#power-domain-cells = <0>;
501994a71a3SChun-Jie Chen						};
502994a71a3SChun-Jie Chen					};
503994a71a3SChun-Jie Chen				};
504994a71a3SChun-Jie Chen			};
505994a71a3SChun-Jie Chen		};
506994a71a3SChun-Jie Chen
507d1986fbdSAllen-KH Cheng		watchdog: watchdog@10007000 {
508d1986fbdSAllen-KH Cheng			compatible = "mediatek,mt8192-wdt";
509d1986fbdSAllen-KH Cheng			reg = <0 0x10007000 0 0x100>;
510d1986fbdSAllen-KH Cheng			#reset-cells = <1>;
511d1986fbdSAllen-KH Cheng		};
512d1986fbdSAllen-KH Cheng
5135d2b897bSChun-Jie Chen		apmixedsys: syscon@1000c000 {
5145d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-apmixedsys", "syscon";
5155d2b897bSChun-Jie Chen			reg = <0 0x1000c000 0 0x1000>;
5165d2b897bSChun-Jie Chen			#clock-cells = <1>;
5175d2b897bSChun-Jie Chen		};
5185d2b897bSChun-Jie Chen
51948489980SSeiya Wang		systimer: timer@10017000 {
52048489980SSeiya Wang			compatible = "mediatek,mt8192-timer",
52148489980SSeiya Wang				     "mediatek,mt6765-timer";
52248489980SSeiya Wang			reg = <0 0x10017000 0 0x1000>;
52348489980SSeiya Wang			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
524dde3c175SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
52548489980SSeiya Wang			clock-names = "clk13m";
52648489980SSeiya Wang		};
52748489980SSeiya Wang
528261691b4SAllen-KH Cheng		pwrap: pwrap@10026000 {
529261691b4SAllen-KH Cheng			compatible = "mediatek,mt6873-pwrap";
530261691b4SAllen-KH Cheng			reg = <0 0x10026000 0 0x1000>;
531261691b4SAllen-KH Cheng			reg-names = "pwrap";
532261691b4SAllen-KH Cheng			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
533261691b4SAllen-KH Cheng			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
534261691b4SAllen-KH Cheng				 <&infracfg CLK_INFRA_PMIC_TMR>;
535261691b4SAllen-KH Cheng			clock-names = "spi", "wrap";
536261691b4SAllen-KH Cheng			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
537261691b4SAllen-KH Cheng			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
538261691b4SAllen-KH Cheng		};
539261691b4SAllen-KH Cheng
540*a8bbcf70SAllen-KH Cheng		spmi: spmi@10027000 {
541*a8bbcf70SAllen-KH Cheng			compatible = "mediatek,mt6873-spmi";
542*a8bbcf70SAllen-KH Cheng			reg = <0 0x10027000 0 0x000e00>,
543*a8bbcf70SAllen-KH Cheng			      <0 0x10029000 0 0x000100>;
544*a8bbcf70SAllen-KH Cheng			reg-names = "pmif", "spmimst";
545*a8bbcf70SAllen-KH Cheng			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
546*a8bbcf70SAllen-KH Cheng				 <&infracfg CLK_INFRA_PMIC_TMR>,
547*a8bbcf70SAllen-KH Cheng				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
548*a8bbcf70SAllen-KH Cheng			clock-names = "pmif_sys_ck",
549*a8bbcf70SAllen-KH Cheng				      "pmif_tmr_ck",
550*a8bbcf70SAllen-KH Cheng				      "spmimst_clk_mux";
551*a8bbcf70SAllen-KH Cheng			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
552*a8bbcf70SAllen-KH Cheng			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
553*a8bbcf70SAllen-KH Cheng		};
554*a8bbcf70SAllen-KH Cheng
5555d2b897bSChun-Jie Chen		scp_adsp: clock-controller@10720000 {
5565d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-scp_adsp";
5575d2b897bSChun-Jie Chen			reg = <0 0x10720000 0 0x1000>;
5585d2b897bSChun-Jie Chen			#clock-cells = <1>;
5595d2b897bSChun-Jie Chen		};
5605d2b897bSChun-Jie Chen
56148489980SSeiya Wang		uart0: serial@11002000 {
56248489980SSeiya Wang			compatible = "mediatek,mt8192-uart",
56348489980SSeiya Wang				     "mediatek,mt6577-uart";
56448489980SSeiya Wang			reg = <0 0x11002000 0 0x1000>;
56548489980SSeiya Wang			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
56673ba8502SAllen-KH Cheng			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
56748489980SSeiya Wang			clock-names = "baud", "bus";
56848489980SSeiya Wang			status = "disabled";
56948489980SSeiya Wang		};
57048489980SSeiya Wang
57148489980SSeiya Wang		uart1: serial@11003000 {
57248489980SSeiya Wang			compatible = "mediatek,mt8192-uart",
57348489980SSeiya Wang				     "mediatek,mt6577-uart";
57448489980SSeiya Wang			reg = <0 0x11003000 0 0x1000>;
57548489980SSeiya Wang			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
57673ba8502SAllen-KH Cheng			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
57748489980SSeiya Wang			clock-names = "baud", "bus";
57848489980SSeiya Wang			status = "disabled";
57948489980SSeiya Wang		};
58048489980SSeiya Wang
5815d2b897bSChun-Jie Chen		imp_iic_wrap_c: clock-controller@11007000 {
5825d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-imp_iic_wrap_c";
5835d2b897bSChun-Jie Chen			reg = <0 0x11007000 0 0x1000>;
5845d2b897bSChun-Jie Chen			#clock-cells = <1>;
5855d2b897bSChun-Jie Chen		};
5865d2b897bSChun-Jie Chen
58748489980SSeiya Wang		spi0: spi@1100a000 {
58848489980SSeiya Wang			compatible = "mediatek,mt8192-spi",
58948489980SSeiya Wang				     "mediatek,mt6765-spi";
59048489980SSeiya Wang			#address-cells = <1>;
59148489980SSeiya Wang			#size-cells = <0>;
59248489980SSeiya Wang			reg = <0 0x1100a000 0 0x1000>;
59348489980SSeiya Wang			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
5947f0c5b39SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
5957f0c5b39SAllen-KH Cheng				 <&topckgen CLK_TOP_SPI_SEL>,
5967f0c5b39SAllen-KH Cheng				 <&infracfg CLK_INFRA_SPI0>;
59748489980SSeiya Wang			clock-names = "parent-clk", "sel-clk", "spi-clk";
59848489980SSeiya Wang			status = "disabled";
59948489980SSeiya Wang		};
60048489980SSeiya Wang
60148489980SSeiya Wang		spi1: spi@11010000 {
60248489980SSeiya Wang			compatible = "mediatek,mt8192-spi",
60348489980SSeiya Wang				     "mediatek,mt6765-spi";
60448489980SSeiya Wang			#address-cells = <1>;
60548489980SSeiya Wang			#size-cells = <0>;
60648489980SSeiya Wang			reg = <0 0x11010000 0 0x1000>;
60748489980SSeiya Wang			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
6087f0c5b39SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
6097f0c5b39SAllen-KH Cheng				 <&topckgen CLK_TOP_SPI_SEL>,
6107f0c5b39SAllen-KH Cheng				 <&infracfg CLK_INFRA_SPI1>;
61148489980SSeiya Wang			clock-names = "parent-clk", "sel-clk", "spi-clk";
61248489980SSeiya Wang			status = "disabled";
61348489980SSeiya Wang		};
61448489980SSeiya Wang
61548489980SSeiya Wang		spi2: spi@11012000 {
61648489980SSeiya Wang			compatible = "mediatek,mt8192-spi",
61748489980SSeiya Wang				     "mediatek,mt6765-spi";
61848489980SSeiya Wang			#address-cells = <1>;
61948489980SSeiya Wang			#size-cells = <0>;
62048489980SSeiya Wang			reg = <0 0x11012000 0 0x1000>;
62148489980SSeiya Wang			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
6227f0c5b39SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
6237f0c5b39SAllen-KH Cheng				 <&topckgen CLK_TOP_SPI_SEL>,
6247f0c5b39SAllen-KH Cheng				 <&infracfg CLK_INFRA_SPI2>;
62548489980SSeiya Wang			clock-names = "parent-clk", "sel-clk", "spi-clk";
62648489980SSeiya Wang			status = "disabled";
62748489980SSeiya Wang		};
62848489980SSeiya Wang
62948489980SSeiya Wang		spi3: spi@11013000 {
63048489980SSeiya Wang			compatible = "mediatek,mt8192-spi",
63148489980SSeiya Wang				     "mediatek,mt6765-spi";
63248489980SSeiya Wang			#address-cells = <1>;
63348489980SSeiya Wang			#size-cells = <0>;
63448489980SSeiya Wang			reg = <0 0x11013000 0 0x1000>;
63548489980SSeiya Wang			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
6367f0c5b39SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
6377f0c5b39SAllen-KH Cheng				 <&topckgen CLK_TOP_SPI_SEL>,
6387f0c5b39SAllen-KH Cheng				 <&infracfg CLK_INFRA_SPI3>;
63948489980SSeiya Wang			clock-names = "parent-clk", "sel-clk", "spi-clk";
64048489980SSeiya Wang			status = "disabled";
64148489980SSeiya Wang		};
64248489980SSeiya Wang
64348489980SSeiya Wang		spi4: spi@11018000 {
64448489980SSeiya Wang			compatible = "mediatek,mt8192-spi",
64548489980SSeiya Wang				     "mediatek,mt6765-spi";
64648489980SSeiya Wang			#address-cells = <1>;
64748489980SSeiya Wang			#size-cells = <0>;
64848489980SSeiya Wang			reg = <0 0x11018000 0 0x1000>;
64948489980SSeiya Wang			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
6507f0c5b39SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
6517f0c5b39SAllen-KH Cheng				 <&topckgen CLK_TOP_SPI_SEL>,
6527f0c5b39SAllen-KH Cheng				 <&infracfg CLK_INFRA_SPI4>;
65348489980SSeiya Wang			clock-names = "parent-clk", "sel-clk", "spi-clk";
65448489980SSeiya Wang			status = "disabled";
65548489980SSeiya Wang		};
65648489980SSeiya Wang
65748489980SSeiya Wang		spi5: spi@11019000 {
65848489980SSeiya Wang			compatible = "mediatek,mt8192-spi",
65948489980SSeiya Wang				     "mediatek,mt6765-spi";
66048489980SSeiya Wang			#address-cells = <1>;
66148489980SSeiya Wang			#size-cells = <0>;
66248489980SSeiya Wang			reg = <0 0x11019000 0 0x1000>;
66348489980SSeiya Wang			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
6647f0c5b39SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
6657f0c5b39SAllen-KH Cheng				 <&topckgen CLK_TOP_SPI_SEL>,
6667f0c5b39SAllen-KH Cheng				 <&infracfg CLK_INFRA_SPI5>;
66748489980SSeiya Wang			clock-names = "parent-clk", "sel-clk", "spi-clk";
66848489980SSeiya Wang			status = "disabled";
66948489980SSeiya Wang		};
67048489980SSeiya Wang
67148489980SSeiya Wang		spi6: spi@1101d000 {
67248489980SSeiya Wang			compatible = "mediatek,mt8192-spi",
67348489980SSeiya Wang				     "mediatek,mt6765-spi";
67448489980SSeiya Wang			#address-cells = <1>;
67548489980SSeiya Wang			#size-cells = <0>;
67648489980SSeiya Wang			reg = <0 0x1101d000 0 0x1000>;
67748489980SSeiya Wang			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
6787f0c5b39SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
6797f0c5b39SAllen-KH Cheng				 <&topckgen CLK_TOP_SPI_SEL>,
6807f0c5b39SAllen-KH Cheng				 <&infracfg CLK_INFRA_SPI6>;
68148489980SSeiya Wang			clock-names = "parent-clk", "sel-clk", "spi-clk";
68248489980SSeiya Wang			status = "disabled";
68348489980SSeiya Wang		};
68448489980SSeiya Wang
68548489980SSeiya Wang		spi7: spi@1101e000 {
68648489980SSeiya Wang			compatible = "mediatek,mt8192-spi",
68748489980SSeiya Wang				     "mediatek,mt6765-spi";
68848489980SSeiya Wang			#address-cells = <1>;
68948489980SSeiya Wang			#size-cells = <0>;
69048489980SSeiya Wang			reg = <0 0x1101e000 0 0x1000>;
69148489980SSeiya Wang			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
6927f0c5b39SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
6937f0c5b39SAllen-KH Cheng				 <&topckgen CLK_TOP_SPI_SEL>,
6947f0c5b39SAllen-KH Cheng				 <&infracfg CLK_INFRA_SPI7>;
69548489980SSeiya Wang			clock-names = "parent-clk", "sel-clk", "spi-clk";
69648489980SSeiya Wang			status = "disabled";
69748489980SSeiya Wang		};
69848489980SSeiya Wang
699c63556ecSAllen-KH Cheng		scp: scp@10500000 {
700c63556ecSAllen-KH Cheng			compatible = "mediatek,mt8192-scp";
701c63556ecSAllen-KH Cheng			reg = <0 0x10500000 0 0x100000>,
702c63556ecSAllen-KH Cheng			      <0 0x10700000 0 0x8000>,
703c63556ecSAllen-KH Cheng			      <0 0x10720000 0 0xe0000>;
704c63556ecSAllen-KH Cheng			reg-names = "sram", "l1tcm", "cfg";
705c63556ecSAllen-KH Cheng			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
706c63556ecSAllen-KH Cheng			clocks = <&infracfg CLK_INFRA_SCPSYS>;
707c63556ecSAllen-KH Cheng			clock-names = "main";
708c63556ecSAllen-KH Cheng			status = "disabled";
709c63556ecSAllen-KH Cheng		};
710c63556ecSAllen-KH Cheng
711e5aac225SAllen-KH Cheng		xhci: usb@11200000 {
712e5aac225SAllen-KH Cheng			compatible = "mediatek,mt8192-xhci",
713e5aac225SAllen-KH Cheng				     "mediatek,mtk-xhci";
714e5aac225SAllen-KH Cheng			reg = <0 0x11200000 0 0x1000>,
715e5aac225SAllen-KH Cheng			      <0 0x11203e00 0 0x0100>;
716e5aac225SAllen-KH Cheng			reg-names = "mac", "ippc";
717e5aac225SAllen-KH Cheng			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
718e5aac225SAllen-KH Cheng			interrupt-names = "host";
719e5aac225SAllen-KH Cheng			phys = <&u2port0 PHY_TYPE_USB2>,
720e5aac225SAllen-KH Cheng			       <&u3port0 PHY_TYPE_USB3>;
721e5aac225SAllen-KH Cheng			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
722e5aac225SAllen-KH Cheng					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
723e5aac225SAllen-KH Cheng			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
724e5aac225SAllen-KH Cheng						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
725e5aac225SAllen-KH Cheng			clocks = <&infracfg CLK_INFRA_SSUSB>,
726e5aac225SAllen-KH Cheng				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
727e5aac225SAllen-KH Cheng				 <&apmixedsys CLK_APMIXED_USBPLL>;
728e5aac225SAllen-KH Cheng			clock-names = "sys_ck", "xhci_ck", "ref_ck";
729e5aac225SAllen-KH Cheng			wakeup-source;
730e5aac225SAllen-KH Cheng			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
731e5aac225SAllen-KH Cheng			status = "disabled";
732e5aac225SAllen-KH Cheng		};
733e5aac225SAllen-KH Cheng
734e530d080SAllen-KH Cheng		pcie: pcie@11230000 {
735e530d080SAllen-KH Cheng			compatible = "mediatek,mt8192-pcie";
736e530d080SAllen-KH Cheng			device_type = "pci";
737e530d080SAllen-KH Cheng			reg = <0 0x11230000 0 0x2000>;
738e530d080SAllen-KH Cheng			reg-names = "pcie-mac";
739e530d080SAllen-KH Cheng			#address-cells = <3>;
740e530d080SAllen-KH Cheng			#size-cells = <2>;
741e530d080SAllen-KH Cheng			clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
742e530d080SAllen-KH Cheng				 <&infracfg CLK_INFRA_PCIE_TL_26M>,
743e530d080SAllen-KH Cheng				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
744e530d080SAllen-KH Cheng				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
745e530d080SAllen-KH Cheng				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
746e530d080SAllen-KH Cheng				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
747e530d080SAllen-KH Cheng			clock-names = "pl_250m", "tl_26m", "tl_96m",
748e530d080SAllen-KH Cheng				      "tl_32k", "peri_26m", "top_133m";
749e530d080SAllen-KH Cheng			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
750e530d080SAllen-KH Cheng			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
751e530d080SAllen-KH Cheng			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
752e530d080SAllen-KH Cheng			bus-range = <0x00 0xff>;
753e530d080SAllen-KH Cheng			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
754e530d080SAllen-KH Cheng				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
755e530d080SAllen-KH Cheng			#interrupt-cells = <1>;
756e530d080SAllen-KH Cheng			interrupt-map-mask = <0 0 0 7>;
757e530d080SAllen-KH Cheng			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
758e530d080SAllen-KH Cheng					<0 0 0 2 &pcie_intc0 1>,
759e530d080SAllen-KH Cheng					<0 0 0 3 &pcie_intc0 2>,
760e530d080SAllen-KH Cheng					<0 0 0 4 &pcie_intc0 3>;
761e530d080SAllen-KH Cheng
762e530d080SAllen-KH Cheng			pcie_intc0: interrupt-controller {
763e530d080SAllen-KH Cheng				interrupt-controller;
764e530d080SAllen-KH Cheng				#address-cells = <0>;
765e530d080SAllen-KH Cheng				#interrupt-cells = <1>;
766e530d080SAllen-KH Cheng			};
767e530d080SAllen-KH Cheng		};
768e530d080SAllen-KH Cheng
769d0a197a0Sbayi cheng		nor_flash: spi@11234000 {
770d0a197a0Sbayi cheng			compatible = "mediatek,mt8192-nor";
771d0a197a0Sbayi cheng			reg = <0 0x11234000 0 0xe0>;
772d0a197a0Sbayi cheng			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
773aa247c07SAllen-KH Cheng			clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
774aa247c07SAllen-KH Cheng				 <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
775aa247c07SAllen-KH Cheng				 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
776d0a197a0Sbayi cheng			clock-names = "spi", "sf", "axi";
777aa247c07SAllen-KH Cheng			assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
778aa247c07SAllen-KH Cheng			assigned-clock-parents = <&clk26m>;
779d0a197a0Sbayi cheng			#address-cells = <1>;
780d0a197a0Sbayi cheng			#size-cells = <0>;
78127f0eb16SAllen-KH Cheng			status = "disabled";
782d0a197a0Sbayi cheng		};
783d0a197a0Sbayi cheng
7845d2b897bSChun-Jie Chen		audsys: clock-controller@11210000 {
7855d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-audsys", "syscon";
7865d2b897bSChun-Jie Chen			reg = <0 0x11210000 0 0x1000>;
7875d2b897bSChun-Jie Chen			#clock-cells = <1>;
7885d2b897bSChun-Jie Chen		};
7895d2b897bSChun-Jie Chen
7904d50a433SAllen-KH Cheng		efuse: efuse@11c10000 {
7914d50a433SAllen-KH Cheng			compatible = "mediatek,efuse";
7924d50a433SAllen-KH Cheng			reg = <0 0x11c10000 0 0x1000>;
7934d50a433SAllen-KH Cheng			#address-cells = <1>;
7944d50a433SAllen-KH Cheng			#size-cells = <1>;
7954d50a433SAllen-KH Cheng
7964d50a433SAllen-KH Cheng			lvts_e_data1: data1@1c0 {
7974d50a433SAllen-KH Cheng				reg = <0x1c0 0x58>;
7984d50a433SAllen-KH Cheng			};
7994d50a433SAllen-KH Cheng
8004d50a433SAllen-KH Cheng			svs_calibration: calib@580 {
8014d50a433SAllen-KH Cheng				reg = <0x580 0x68>;
8024d50a433SAllen-KH Cheng			};
8034d50a433SAllen-KH Cheng		};
8044d50a433SAllen-KH Cheng
8057f1a9f47SFabien Parent		i2c3: i2c@11cb0000 {
80648489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
80748489980SSeiya Wang			reg = <0 0x11cb0000 0 0x1000>,
80848489980SSeiya Wang			      <0 0x10217300 0 0x80>;
80948489980SSeiya Wang			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
81022623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
81122623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
81248489980SSeiya Wang			clock-names = "main", "dma";
81348489980SSeiya Wang			clock-div = <1>;
81448489980SSeiya Wang			#address-cells = <1>;
81548489980SSeiya Wang			#size-cells = <0>;
81648489980SSeiya Wang			status = "disabled";
81748489980SSeiya Wang		};
81848489980SSeiya Wang
8195d2b897bSChun-Jie Chen		imp_iic_wrap_e: clock-controller@11cb1000 {
8205d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-imp_iic_wrap_e";
8215d2b897bSChun-Jie Chen			reg = <0 0x11cb1000 0 0x1000>;
8225d2b897bSChun-Jie Chen			#clock-cells = <1>;
8235d2b897bSChun-Jie Chen		};
8245d2b897bSChun-Jie Chen
8257f1a9f47SFabien Parent		i2c7: i2c@11d00000 {
82648489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
82748489980SSeiya Wang			reg = <0 0x11d00000 0 0x1000>,
82848489980SSeiya Wang			      <0 0x10217600 0 0x180>;
82948489980SSeiya Wang			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
83022623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
83122623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
83248489980SSeiya Wang			clock-names = "main", "dma";
83348489980SSeiya Wang			clock-div = <1>;
83448489980SSeiya Wang			#address-cells = <1>;
83548489980SSeiya Wang			#size-cells = <0>;
83648489980SSeiya Wang			status = "disabled";
83748489980SSeiya Wang		};
83848489980SSeiya Wang
8397f1a9f47SFabien Parent		i2c8: i2c@11d01000 {
84048489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
84148489980SSeiya Wang			reg = <0 0x11d01000 0 0x1000>,
84248489980SSeiya Wang			      <0 0x10217780 0 0x180>;
84348489980SSeiya Wang			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
84422623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
84522623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
84648489980SSeiya Wang			clock-names = "main", "dma";
84748489980SSeiya Wang			clock-div = <1>;
84848489980SSeiya Wang			#address-cells = <1>;
84948489980SSeiya Wang			#size-cells = <0>;
85048489980SSeiya Wang			status = "disabled";
85148489980SSeiya Wang		};
85248489980SSeiya Wang
8537f1a9f47SFabien Parent		i2c9: i2c@11d02000 {
85448489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
85548489980SSeiya Wang			reg = <0 0x11d02000 0 0x1000>,
85648489980SSeiya Wang			      <0 0x10217900 0 0x180>;
85748489980SSeiya Wang			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
85822623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
85922623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
86048489980SSeiya Wang			clock-names = "main", "dma";
86148489980SSeiya Wang			clock-div = <1>;
86248489980SSeiya Wang			#address-cells = <1>;
86348489980SSeiya Wang			#size-cells = <0>;
86448489980SSeiya Wang			status = "disabled";
86548489980SSeiya Wang		};
86648489980SSeiya Wang
8675d2b897bSChun-Jie Chen		imp_iic_wrap_s: clock-controller@11d03000 {
8685d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-imp_iic_wrap_s";
8695d2b897bSChun-Jie Chen			reg = <0 0x11d03000 0 0x1000>;
8705d2b897bSChun-Jie Chen			#clock-cells = <1>;
8715d2b897bSChun-Jie Chen		};
8725d2b897bSChun-Jie Chen
8737f1a9f47SFabien Parent		i2c1: i2c@11d20000 {
87448489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
87548489980SSeiya Wang			reg = <0 0x11d20000 0 0x1000>,
87648489980SSeiya Wang			      <0 0x10217100 0 0x80>;
87748489980SSeiya Wang			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
87822623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
87922623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
88048489980SSeiya Wang			clock-names = "main", "dma";
88148489980SSeiya Wang			clock-div = <1>;
88248489980SSeiya Wang			#address-cells = <1>;
88348489980SSeiya Wang			#size-cells = <0>;
88448489980SSeiya Wang			status = "disabled";
88548489980SSeiya Wang		};
88648489980SSeiya Wang
8877f1a9f47SFabien Parent		i2c2: i2c@11d21000 {
88848489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
88948489980SSeiya Wang			reg = <0 0x11d21000 0 0x1000>,
89048489980SSeiya Wang			      <0 0x10217180 0 0x180>;
89148489980SSeiya Wang			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
89222623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
89322623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
89448489980SSeiya Wang			clock-names = "main", "dma";
89548489980SSeiya Wang			clock-div = <1>;
89648489980SSeiya Wang			#address-cells = <1>;
89748489980SSeiya Wang			#size-cells = <0>;
89848489980SSeiya Wang			status = "disabled";
89948489980SSeiya Wang		};
90048489980SSeiya Wang
9017f1a9f47SFabien Parent		i2c4: i2c@11d22000 {
90248489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
90348489980SSeiya Wang			reg = <0 0x11d22000 0 0x1000>,
90448489980SSeiya Wang			      <0 0x10217380 0 0x180>;
90548489980SSeiya Wang			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
90622623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
90722623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
90848489980SSeiya Wang			clock-names = "main", "dma";
90948489980SSeiya Wang			clock-div = <1>;
91048489980SSeiya Wang			#address-cells = <1>;
91148489980SSeiya Wang			#size-cells = <0>;
91248489980SSeiya Wang			status = "disabled";
91348489980SSeiya Wang		};
91448489980SSeiya Wang
9155d2b897bSChun-Jie Chen		imp_iic_wrap_ws: clock-controller@11d23000 {
9165d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-imp_iic_wrap_ws";
9175d2b897bSChun-Jie Chen			reg = <0 0x11d23000 0 0x1000>;
9185d2b897bSChun-Jie Chen			#clock-cells = <1>;
9195d2b897bSChun-Jie Chen		};
9205d2b897bSChun-Jie Chen
9217f1a9f47SFabien Parent		i2c5: i2c@11e00000 {
92248489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
92348489980SSeiya Wang			reg = <0 0x11e00000 0 0x1000>,
92448489980SSeiya Wang			      <0 0x10217500 0 0x80>;
92548489980SSeiya Wang			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
92622623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
92722623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
92848489980SSeiya Wang			clock-names = "main", "dma";
92948489980SSeiya Wang			clock-div = <1>;
93048489980SSeiya Wang			#address-cells = <1>;
93148489980SSeiya Wang			#size-cells = <0>;
93248489980SSeiya Wang			status = "disabled";
93348489980SSeiya Wang		};
93448489980SSeiya Wang
9355d2b897bSChun-Jie Chen		imp_iic_wrap_w: clock-controller@11e01000 {
9365d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-imp_iic_wrap_w";
9375d2b897bSChun-Jie Chen			reg = <0 0x11e01000 0 0x1000>;
9385d2b897bSChun-Jie Chen			#clock-cells = <1>;
9395d2b897bSChun-Jie Chen		};
9405d2b897bSChun-Jie Chen
94140de66b8SAllen-KH Cheng		u3phy0: t-phy@11e40000 {
94240de66b8SAllen-KH Cheng			compatible = "mediatek,mt8192-tphy",
94340de66b8SAllen-KH Cheng				     "mediatek,generic-tphy-v2";
94440de66b8SAllen-KH Cheng			#address-cells = <1>;
94540de66b8SAllen-KH Cheng			#size-cells = <1>;
94640de66b8SAllen-KH Cheng			ranges = <0x0 0x0 0x11e40000 0x1000>;
94740de66b8SAllen-KH Cheng
94840de66b8SAllen-KH Cheng			u2port0: usb-phy@0 {
94940de66b8SAllen-KH Cheng				reg = <0x0 0x700>;
95040de66b8SAllen-KH Cheng				clocks = <&clk26m>;
95140de66b8SAllen-KH Cheng				clock-names = "ref";
95240de66b8SAllen-KH Cheng				#phy-cells = <1>;
95340de66b8SAllen-KH Cheng			};
95440de66b8SAllen-KH Cheng
95540de66b8SAllen-KH Cheng			u3port0: usb-phy@700 {
95640de66b8SAllen-KH Cheng				reg = <0x700 0x900>;
95740de66b8SAllen-KH Cheng				clocks = <&clk26m>;
95840de66b8SAllen-KH Cheng				clock-names = "ref";
95940de66b8SAllen-KH Cheng				#phy-cells = <1>;
96040de66b8SAllen-KH Cheng			};
96140de66b8SAllen-KH Cheng		};
96240de66b8SAllen-KH Cheng
9637f1a9f47SFabien Parent		i2c0: i2c@11f00000 {
96448489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
96548489980SSeiya Wang			reg = <0 0x11f00000 0 0x1000>,
96648489980SSeiya Wang			      <0 0x10217080 0 0x80>;
96748489980SSeiya Wang			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
96822623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
96922623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
97048489980SSeiya Wang			clock-names = "main", "dma";
97148489980SSeiya Wang			clock-div = <1>;
97248489980SSeiya Wang			#address-cells = <1>;
97348489980SSeiya Wang			#size-cells = <0>;
97448489980SSeiya Wang			status = "disabled";
97548489980SSeiya Wang		};
97648489980SSeiya Wang
9777f1a9f47SFabien Parent		i2c6: i2c@11f01000 {
97848489980SSeiya Wang			compatible = "mediatek,mt8192-i2c";
97948489980SSeiya Wang			reg = <0 0x11f01000 0 0x1000>,
98048489980SSeiya Wang			      <0 0x10217580 0 0x80>;
98148489980SSeiya Wang			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
98222623154SAllen-KH Cheng			clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
98322623154SAllen-KH Cheng				 <&infracfg CLK_INFRA_AP_DMA>;
98448489980SSeiya Wang			clock-names = "main", "dma";
98548489980SSeiya Wang			clock-div = <1>;
98648489980SSeiya Wang			#address-cells = <1>;
98748489980SSeiya Wang			#size-cells = <0>;
98848489980SSeiya Wang			status = "disabled";
98948489980SSeiya Wang		};
9905d2b897bSChun-Jie Chen
9915d2b897bSChun-Jie Chen		imp_iic_wrap_n: clock-controller@11f02000 {
9925d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-imp_iic_wrap_n";
9935d2b897bSChun-Jie Chen			reg = <0 0x11f02000 0 0x1000>;
9945d2b897bSChun-Jie Chen			#clock-cells = <1>;
9955d2b897bSChun-Jie Chen		};
9965d2b897bSChun-Jie Chen
9975d2b897bSChun-Jie Chen		msdc_top: clock-controller@11f10000 {
9985d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-msdc_top";
9995d2b897bSChun-Jie Chen			reg = <0 0x11f10000 0 0x1000>;
10005d2b897bSChun-Jie Chen			#clock-cells = <1>;
10015d2b897bSChun-Jie Chen		};
10025d2b897bSChun-Jie Chen
10035d2b897bSChun-Jie Chen		msdc: clock-controller@11f60000 {
10045d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-msdc";
10055d2b897bSChun-Jie Chen			reg = <0 0x11f60000 0 0x1000>;
10065d2b897bSChun-Jie Chen			#clock-cells = <1>;
10075d2b897bSChun-Jie Chen		};
10085d2b897bSChun-Jie Chen
10095d2b897bSChun-Jie Chen		mfgcfg: clock-controller@13fbf000 {
10105d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-mfgcfg";
10115d2b897bSChun-Jie Chen			reg = <0 0x13fbf000 0 0x1000>;
10125d2b897bSChun-Jie Chen			#clock-cells = <1>;
10135d2b897bSChun-Jie Chen		};
10145d2b897bSChun-Jie Chen
10155d2b897bSChun-Jie Chen		mmsys: syscon@14000000 {
10165d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-mmsys", "syscon";
10175d2b897bSChun-Jie Chen			reg = <0 0x14000000 0 0x1000>;
10185d2b897bSChun-Jie Chen			#clock-cells = <1>;
10195d2b897bSChun-Jie Chen		};
10205d2b897bSChun-Jie Chen
10214a65b0f1SAllen-KH Cheng		smi_common: smi@14002000 {
10224a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-common";
10234a65b0f1SAllen-KH Cheng			reg = <0 0x14002000 0 0x1000>;
10244a65b0f1SAllen-KH Cheng			clocks = <&mmsys CLK_MM_SMI_COMMON>,
10254a65b0f1SAllen-KH Cheng				 <&mmsys CLK_MM_SMI_INFRA>,
10264a65b0f1SAllen-KH Cheng				 <&mmsys CLK_MM_SMI_GALS>,
10274a65b0f1SAllen-KH Cheng				 <&mmsys CLK_MM_SMI_GALS>;
10284a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi", "gals0", "gals1";
10294a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
10304a65b0f1SAllen-KH Cheng		};
10314a65b0f1SAllen-KH Cheng
10324a65b0f1SAllen-KH Cheng		larb0: larb@14003000 {
10334a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
10344a65b0f1SAllen-KH Cheng			reg = <0 0x14003000 0 0x1000>;
10354a65b0f1SAllen-KH Cheng			mediatek,larb-id = <0>;
10364a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
10374a65b0f1SAllen-KH Cheng			clocks = <&clk26m>, <&clk26m>;
10384a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
10394a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
10404a65b0f1SAllen-KH Cheng		};
10414a65b0f1SAllen-KH Cheng
10424a65b0f1SAllen-KH Cheng		larb1: larb@14004000 {
10434a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
10444a65b0f1SAllen-KH Cheng			reg = <0 0x14004000 0 0x1000>;
10454a65b0f1SAllen-KH Cheng			mediatek,larb-id = <1>;
10464a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
10474a65b0f1SAllen-KH Cheng			clocks = <&clk26m>, <&clk26m>;
10484a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
10494a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
10504a65b0f1SAllen-KH Cheng		};
10514a65b0f1SAllen-KH Cheng
1052b2edd519SAllen-KH Cheng		dpi0: dpi@14016000 {
1053b2edd519SAllen-KH Cheng			compatible = "mediatek,mt8192-dpi";
1054b2edd519SAllen-KH Cheng			reg = <0 0x14016000 0 0x1000>;
1055b2edd519SAllen-KH Cheng			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
1056b2edd519SAllen-KH Cheng			clocks = <&mmsys CLK_MM_DPI_DPI0>,
1057b2edd519SAllen-KH Cheng				 <&mmsys CLK_MM_DISP_DPI0>,
1058b2edd519SAllen-KH Cheng				 <&apmixedsys CLK_APMIXED_TVDPLL>;
1059b2edd519SAllen-KH Cheng			clock-names = "pixel", "engine", "pll";
1060b2edd519SAllen-KH Cheng			status = "disabled";
1061b2edd519SAllen-KH Cheng		};
1062b2edd519SAllen-KH Cheng
10634a65b0f1SAllen-KH Cheng		iommu0: m4u@1401d000 {
10644a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-m4u";
10654a65b0f1SAllen-KH Cheng			reg = <0 0x1401d000 0 0x1000>;
10664a65b0f1SAllen-KH Cheng			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
10674a65b0f1SAllen-KH Cheng					 <&larb4>, <&larb5>, <&larb7>,
10684a65b0f1SAllen-KH Cheng					 <&larb9>, <&larb11>, <&larb13>,
10694a65b0f1SAllen-KH Cheng					 <&larb14>, <&larb16>, <&larb17>,
10704a65b0f1SAllen-KH Cheng					 <&larb18>, <&larb19>, <&larb20>;
10714a65b0f1SAllen-KH Cheng			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
10724a65b0f1SAllen-KH Cheng			clocks = <&mmsys CLK_MM_SMI_IOMMU>;
10734a65b0f1SAllen-KH Cheng			clock-names = "bclk";
10744a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
10754a65b0f1SAllen-KH Cheng			#iommu-cells = <1>;
10764a65b0f1SAllen-KH Cheng		};
10774a65b0f1SAllen-KH Cheng
10785d2b897bSChun-Jie Chen		imgsys: clock-controller@15020000 {
10795d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-imgsys";
10805d2b897bSChun-Jie Chen			reg = <0 0x15020000 0 0x1000>;
10815d2b897bSChun-Jie Chen			#clock-cells = <1>;
10825d2b897bSChun-Jie Chen		};
10835d2b897bSChun-Jie Chen
10844a65b0f1SAllen-KH Cheng		larb9: larb@1502e000 {
10854a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
10864a65b0f1SAllen-KH Cheng			reg = <0 0x1502e000 0 0x1000>;
10874a65b0f1SAllen-KH Cheng			mediatek,larb-id = <9>;
10884a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
10894a65b0f1SAllen-KH Cheng			clocks = <&imgsys CLK_IMG_LARB9>,
10904a65b0f1SAllen-KH Cheng				 <&imgsys CLK_IMG_LARB9>;
10914a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
10924a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
10934a65b0f1SAllen-KH Cheng		};
10944a65b0f1SAllen-KH Cheng
10955d2b897bSChun-Jie Chen		imgsys2: clock-controller@15820000 {
10965d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-imgsys2";
10975d2b897bSChun-Jie Chen			reg = <0 0x15820000 0 0x1000>;
10985d2b897bSChun-Jie Chen			#clock-cells = <1>;
10995d2b897bSChun-Jie Chen		};
11005d2b897bSChun-Jie Chen
11014a65b0f1SAllen-KH Cheng		larb11: larb@1582e000 {
11024a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
11034a65b0f1SAllen-KH Cheng			reg = <0 0x1582e000 0 0x1000>;
11044a65b0f1SAllen-KH Cheng			mediatek,larb-id = <11>;
11054a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
11064a65b0f1SAllen-KH Cheng			clocks = <&imgsys2 CLK_IMG2_LARB11>,
11074a65b0f1SAllen-KH Cheng				 <&imgsys2 CLK_IMG2_LARB11>;
11084a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
11094a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
11104a65b0f1SAllen-KH Cheng		};
11114a65b0f1SAllen-KH Cheng
11124a65b0f1SAllen-KH Cheng		larb5: larb@1600d000 {
11134a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
11144a65b0f1SAllen-KH Cheng			reg = <0 0x1600d000 0 0x1000>;
11154a65b0f1SAllen-KH Cheng			mediatek,larb-id = <5>;
11164a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
11174a65b0f1SAllen-KH Cheng			clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
11184a65b0f1SAllen-KH Cheng				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
11194a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
11204a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
11214a65b0f1SAllen-KH Cheng		};
11224a65b0f1SAllen-KH Cheng
11235d2b897bSChun-Jie Chen		vdecsys_soc: clock-controller@1600f000 {
11245d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-vdecsys_soc";
11255d2b897bSChun-Jie Chen			reg = <0 0x1600f000 0 0x1000>;
11265d2b897bSChun-Jie Chen			#clock-cells = <1>;
11275d2b897bSChun-Jie Chen		};
11285d2b897bSChun-Jie Chen
11294a65b0f1SAllen-KH Cheng		larb4: larb@1602e000 {
11304a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
11314a65b0f1SAllen-KH Cheng			reg = <0 0x1602e000 0 0x1000>;
11324a65b0f1SAllen-KH Cheng			mediatek,larb-id = <4>;
11334a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
11344a65b0f1SAllen-KH Cheng			clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
11354a65b0f1SAllen-KH Cheng				 <&vdecsys CLK_VDEC_SOC_LARB1>;
11364a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
11374a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
11384a65b0f1SAllen-KH Cheng		};
11394a65b0f1SAllen-KH Cheng
11405d2b897bSChun-Jie Chen		vdecsys: clock-controller@1602f000 {
11415d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-vdecsys";
11425d2b897bSChun-Jie Chen			reg = <0 0x1602f000 0 0x1000>;
11435d2b897bSChun-Jie Chen			#clock-cells = <1>;
11445d2b897bSChun-Jie Chen		};
11455d2b897bSChun-Jie Chen
11465d2b897bSChun-Jie Chen		vencsys: clock-controller@17000000 {
11475d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-vencsys";
11485d2b897bSChun-Jie Chen			reg = <0 0x17000000 0 0x1000>;
11495d2b897bSChun-Jie Chen			#clock-cells = <1>;
11505d2b897bSChun-Jie Chen		};
11515d2b897bSChun-Jie Chen
11524a65b0f1SAllen-KH Cheng		larb7: larb@17010000 {
11534a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
11544a65b0f1SAllen-KH Cheng			reg = <0 0x17010000 0 0x1000>;
11554a65b0f1SAllen-KH Cheng			mediatek,larb-id = <7>;
11564a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
11574a65b0f1SAllen-KH Cheng			clocks = <&vencsys CLK_VENC_SET0_LARB>,
11584a65b0f1SAllen-KH Cheng				 <&vencsys CLK_VENC_SET1_VENC>;
11594a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
11604a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
11614a65b0f1SAllen-KH Cheng		};
11624a65b0f1SAllen-KH Cheng
1163aa8f3711SAllen-KH Cheng		vcodec_enc: vcodec@17020000 {
1164aa8f3711SAllen-KH Cheng			compatible = "mediatek,mt8192-vcodec-enc";
1165aa8f3711SAllen-KH Cheng			reg = <0 0x17020000 0 0x2000>;
1166aa8f3711SAllen-KH Cheng			iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
1167aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_REC>,
1168aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
1169aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
1170aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
1171aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
1172aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
1173aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
1174aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
1175aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
1176aa8f3711SAllen-KH Cheng				 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
1177aa8f3711SAllen-KH Cheng			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
1178aa8f3711SAllen-KH Cheng			mediatek,scp = <&scp>;
1179aa8f3711SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1180aa8f3711SAllen-KH Cheng			clocks = <&vencsys CLK_VENC_SET1_VENC>;
1181aa8f3711SAllen-KH Cheng			clock-names = "venc-set1";
1182aa8f3711SAllen-KH Cheng			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1183aa8f3711SAllen-KH Cheng			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1184aa8f3711SAllen-KH Cheng		};
1185aa8f3711SAllen-KH Cheng
11865d2b897bSChun-Jie Chen		camsys: clock-controller@1a000000 {
11875d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-camsys";
11885d2b897bSChun-Jie Chen			reg = <0 0x1a000000 0 0x1000>;
11895d2b897bSChun-Jie Chen			#clock-cells = <1>;
11905d2b897bSChun-Jie Chen		};
11915d2b897bSChun-Jie Chen
11924a65b0f1SAllen-KH Cheng		larb13: larb@1a001000 {
11934a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
11944a65b0f1SAllen-KH Cheng			reg = <0 0x1a001000 0 0x1000>;
11954a65b0f1SAllen-KH Cheng			mediatek,larb-id = <13>;
11964a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
11974a65b0f1SAllen-KH Cheng			clocks = <&camsys CLK_CAM_CAM>,
11984a65b0f1SAllen-KH Cheng				 <&camsys CLK_CAM_LARB13>;
11994a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
12004a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
12014a65b0f1SAllen-KH Cheng		};
12024a65b0f1SAllen-KH Cheng
12034a65b0f1SAllen-KH Cheng		larb14: larb@1a002000 {
12044a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
12054a65b0f1SAllen-KH Cheng			reg = <0 0x1a002000 0 0x1000>;
12064a65b0f1SAllen-KH Cheng			mediatek,larb-id = <14>;
12074a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
12084a65b0f1SAllen-KH Cheng			clocks = <&camsys CLK_CAM_CAM>,
12094a65b0f1SAllen-KH Cheng				 <&camsys CLK_CAM_LARB14>;
12104a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
12114a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
12124a65b0f1SAllen-KH Cheng		};
12134a65b0f1SAllen-KH Cheng
12144a65b0f1SAllen-KH Cheng		larb16: larb@1a00f000 {
12154a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
12164a65b0f1SAllen-KH Cheng			reg = <0 0x1a00f000 0 0x1000>;
12174a65b0f1SAllen-KH Cheng			mediatek,larb-id = <16>;
12184a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
12194a65b0f1SAllen-KH Cheng			clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
12204a65b0f1SAllen-KH Cheng				 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
12214a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
12224a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
12234a65b0f1SAllen-KH Cheng		};
12244a65b0f1SAllen-KH Cheng
12254a65b0f1SAllen-KH Cheng		larb17: larb@1a010000 {
12264a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
12274a65b0f1SAllen-KH Cheng			reg = <0 0x1a010000 0 0x1000>;
12284a65b0f1SAllen-KH Cheng			mediatek,larb-id = <17>;
12294a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
12304a65b0f1SAllen-KH Cheng			clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
12314a65b0f1SAllen-KH Cheng				 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
12324a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
12334a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
12344a65b0f1SAllen-KH Cheng		};
12354a65b0f1SAllen-KH Cheng
12364a65b0f1SAllen-KH Cheng		larb18: larb@1a011000 {
12374a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
12384a65b0f1SAllen-KH Cheng			reg = <0 0x1a011000 0 0x1000>;
12394a65b0f1SAllen-KH Cheng			mediatek,larb-id = <18>;
12404a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
12414a65b0f1SAllen-KH Cheng			clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
12424a65b0f1SAllen-KH Cheng				 <&camsys_rawc CLK_CAM_RAWC_CAM>;
12434a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
12444a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
12454a65b0f1SAllen-KH Cheng		};
12464a65b0f1SAllen-KH Cheng
12475d2b897bSChun-Jie Chen		camsys_rawa: clock-controller@1a04f000 {
12485d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-camsys_rawa";
12495d2b897bSChun-Jie Chen			reg = <0 0x1a04f000 0 0x1000>;
12505d2b897bSChun-Jie Chen			#clock-cells = <1>;
12515d2b897bSChun-Jie Chen		};
12525d2b897bSChun-Jie Chen
12535d2b897bSChun-Jie Chen		camsys_rawb: clock-controller@1a06f000 {
12545d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-camsys_rawb";
12555d2b897bSChun-Jie Chen			reg = <0 0x1a06f000 0 0x1000>;
12565d2b897bSChun-Jie Chen			#clock-cells = <1>;
12575d2b897bSChun-Jie Chen		};
12585d2b897bSChun-Jie Chen
12595d2b897bSChun-Jie Chen		camsys_rawc: clock-controller@1a08f000 {
12605d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-camsys_rawc";
12615d2b897bSChun-Jie Chen			reg = <0 0x1a08f000 0 0x1000>;
12625d2b897bSChun-Jie Chen			#clock-cells = <1>;
12635d2b897bSChun-Jie Chen		};
12645d2b897bSChun-Jie Chen
12655d2b897bSChun-Jie Chen		ipesys: clock-controller@1b000000 {
12665d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-ipesys";
12675d2b897bSChun-Jie Chen			reg = <0 0x1b000000 0 0x1000>;
12685d2b897bSChun-Jie Chen			#clock-cells = <1>;
12695d2b897bSChun-Jie Chen		};
12705d2b897bSChun-Jie Chen
12714a65b0f1SAllen-KH Cheng		larb20: larb@1b00f000 {
12724a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
12734a65b0f1SAllen-KH Cheng			reg = <0 0x1b00f000 0 0x1000>;
12744a65b0f1SAllen-KH Cheng			mediatek,larb-id = <20>;
12754a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
12764a65b0f1SAllen-KH Cheng			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
12774a65b0f1SAllen-KH Cheng				 <&ipesys CLK_IPE_LARB20>;
12784a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
12794a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
12804a65b0f1SAllen-KH Cheng		};
12814a65b0f1SAllen-KH Cheng
12824a65b0f1SAllen-KH Cheng		larb19: larb@1b10f000 {
12834a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
12844a65b0f1SAllen-KH Cheng			reg = <0 0x1b10f000 0 0x1000>;
12854a65b0f1SAllen-KH Cheng			mediatek,larb-id = <19>;
12864a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
12874a65b0f1SAllen-KH Cheng			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
12884a65b0f1SAllen-KH Cheng				 <&ipesys CLK_IPE_LARB19>;
12894a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
12904a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
12914a65b0f1SAllen-KH Cheng		};
12924a65b0f1SAllen-KH Cheng
12935d2b897bSChun-Jie Chen		mdpsys: clock-controller@1f000000 {
12945d2b897bSChun-Jie Chen			compatible = "mediatek,mt8192-mdpsys";
12955d2b897bSChun-Jie Chen			reg = <0 0x1f000000 0 0x1000>;
12965d2b897bSChun-Jie Chen			#clock-cells = <1>;
12975d2b897bSChun-Jie Chen		};
12984a65b0f1SAllen-KH Cheng
12994a65b0f1SAllen-KH Cheng		larb2: larb@1f002000 {
13004a65b0f1SAllen-KH Cheng			compatible = "mediatek,mt8192-smi-larb";
13014a65b0f1SAllen-KH Cheng			reg = <0 0x1f002000 0 0x1000>;
13024a65b0f1SAllen-KH Cheng			mediatek,larb-id = <2>;
13034a65b0f1SAllen-KH Cheng			mediatek,smi = <&smi_common>;
13044a65b0f1SAllen-KH Cheng			clocks = <&mdpsys CLK_MDP_SMI0>,
13054a65b0f1SAllen-KH Cheng				 <&mdpsys CLK_MDP_SMI0>;
13064a65b0f1SAllen-KH Cheng			clock-names = "apb", "smi";
13074a65b0f1SAllen-KH Cheng			power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
13084a65b0f1SAllen-KH Cheng		};
130948489980SSeiya Wang	};
131048489980SSeiya Wang};
1311