148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 1148489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 12*994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 1348489980SSeiya Wang 1448489980SSeiya Wang/ { 1548489980SSeiya Wang compatible = "mediatek,mt8192"; 1648489980SSeiya Wang interrupt-parent = <&gic>; 1748489980SSeiya Wang #address-cells = <2>; 1848489980SSeiya Wang #size-cells = <2>; 1948489980SSeiya Wang 2048489980SSeiya Wang clk26m: oscillator0 { 2148489980SSeiya Wang compatible = "fixed-clock"; 2248489980SSeiya Wang #clock-cells = <0>; 2348489980SSeiya Wang clock-frequency = <26000000>; 2448489980SSeiya Wang clock-output-names = "clk26m"; 2548489980SSeiya Wang }; 2648489980SSeiya Wang 2748489980SSeiya Wang clk32k: oscillator1 { 2848489980SSeiya Wang compatible = "fixed-clock"; 2948489980SSeiya Wang #clock-cells = <0>; 3048489980SSeiya Wang clock-frequency = <32768>; 3148489980SSeiya Wang clock-output-names = "clk32k"; 3248489980SSeiya Wang }; 3348489980SSeiya Wang 3448489980SSeiya Wang cpus { 3548489980SSeiya Wang #address-cells = <1>; 3648489980SSeiya Wang #size-cells = <0>; 3748489980SSeiya Wang 3848489980SSeiya Wang cpu0: cpu@0 { 3948489980SSeiya Wang device_type = "cpu"; 4048489980SSeiya Wang compatible = "arm,cortex-a55"; 4148489980SSeiya Wang reg = <0x000>; 4248489980SSeiya Wang enable-method = "psci"; 4348489980SSeiya Wang clock-frequency = <1701000000>; 449260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 4548489980SSeiya Wang next-level-cache = <&l2_0>; 4648489980SSeiya Wang capacity-dmips-mhz = <530>; 4748489980SSeiya Wang }; 4848489980SSeiya Wang 4948489980SSeiya Wang cpu1: cpu@100 { 5048489980SSeiya Wang device_type = "cpu"; 5148489980SSeiya Wang compatible = "arm,cortex-a55"; 5248489980SSeiya Wang reg = <0x100>; 5348489980SSeiya Wang enable-method = "psci"; 5448489980SSeiya Wang clock-frequency = <1701000000>; 559260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 5648489980SSeiya Wang next-level-cache = <&l2_0>; 5748489980SSeiya Wang capacity-dmips-mhz = <530>; 5848489980SSeiya Wang }; 5948489980SSeiya Wang 6048489980SSeiya Wang cpu2: cpu@200 { 6148489980SSeiya Wang device_type = "cpu"; 6248489980SSeiya Wang compatible = "arm,cortex-a55"; 6348489980SSeiya Wang reg = <0x200>; 6448489980SSeiya Wang enable-method = "psci"; 6548489980SSeiya Wang clock-frequency = <1701000000>; 669260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 6748489980SSeiya Wang next-level-cache = <&l2_0>; 6848489980SSeiya Wang capacity-dmips-mhz = <530>; 6948489980SSeiya Wang }; 7048489980SSeiya Wang 7148489980SSeiya Wang cpu3: cpu@300 { 7248489980SSeiya Wang device_type = "cpu"; 7348489980SSeiya Wang compatible = "arm,cortex-a55"; 7448489980SSeiya Wang reg = <0x300>; 7548489980SSeiya Wang enable-method = "psci"; 7648489980SSeiya Wang clock-frequency = <1701000000>; 779260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 7848489980SSeiya Wang next-level-cache = <&l2_0>; 7948489980SSeiya Wang capacity-dmips-mhz = <530>; 8048489980SSeiya Wang }; 8148489980SSeiya Wang 8248489980SSeiya Wang cpu4: cpu@400 { 8348489980SSeiya Wang device_type = "cpu"; 8448489980SSeiya Wang compatible = "arm,cortex-a76"; 8548489980SSeiya Wang reg = <0x400>; 8648489980SSeiya Wang enable-method = "psci"; 8748489980SSeiya Wang clock-frequency = <2171000000>; 889260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 8948489980SSeiya Wang next-level-cache = <&l2_1>; 9048489980SSeiya Wang capacity-dmips-mhz = <1024>; 9148489980SSeiya Wang }; 9248489980SSeiya Wang 9348489980SSeiya Wang cpu5: cpu@500 { 9448489980SSeiya Wang device_type = "cpu"; 9548489980SSeiya Wang compatible = "arm,cortex-a76"; 9648489980SSeiya Wang reg = <0x500>; 9748489980SSeiya Wang enable-method = "psci"; 9848489980SSeiya Wang clock-frequency = <2171000000>; 999260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 10048489980SSeiya Wang next-level-cache = <&l2_1>; 10148489980SSeiya Wang capacity-dmips-mhz = <1024>; 10248489980SSeiya Wang }; 10348489980SSeiya Wang 10448489980SSeiya Wang cpu6: cpu@600 { 10548489980SSeiya Wang device_type = "cpu"; 10648489980SSeiya Wang compatible = "arm,cortex-a76"; 10748489980SSeiya Wang reg = <0x600>; 10848489980SSeiya Wang enable-method = "psci"; 10948489980SSeiya Wang clock-frequency = <2171000000>; 1109260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 11148489980SSeiya Wang next-level-cache = <&l2_1>; 11248489980SSeiya Wang capacity-dmips-mhz = <1024>; 11348489980SSeiya Wang }; 11448489980SSeiya Wang 11548489980SSeiya Wang cpu7: cpu@700 { 11648489980SSeiya Wang device_type = "cpu"; 11748489980SSeiya Wang compatible = "arm,cortex-a76"; 11848489980SSeiya Wang reg = <0x700>; 11948489980SSeiya Wang enable-method = "psci"; 12048489980SSeiya Wang clock-frequency = <2171000000>; 1219260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 12248489980SSeiya Wang next-level-cache = <&l2_1>; 12348489980SSeiya Wang capacity-dmips-mhz = <1024>; 12448489980SSeiya Wang }; 12548489980SSeiya Wang 12648489980SSeiya Wang cpu-map { 12748489980SSeiya Wang cluster0 { 12848489980SSeiya Wang core0 { 12948489980SSeiya Wang cpu = <&cpu0>; 13048489980SSeiya Wang }; 13148489980SSeiya Wang core1 { 13248489980SSeiya Wang cpu = <&cpu1>; 13348489980SSeiya Wang }; 13448489980SSeiya Wang core2 { 13548489980SSeiya Wang cpu = <&cpu2>; 13648489980SSeiya Wang }; 13748489980SSeiya Wang core3 { 13848489980SSeiya Wang cpu = <&cpu3>; 13948489980SSeiya Wang }; 14048489980SSeiya Wang }; 14148489980SSeiya Wang 14248489980SSeiya Wang cluster1 { 14348489980SSeiya Wang core0 { 14448489980SSeiya Wang cpu = <&cpu4>; 14548489980SSeiya Wang }; 14648489980SSeiya Wang core1 { 14748489980SSeiya Wang cpu = <&cpu5>; 14848489980SSeiya Wang }; 14948489980SSeiya Wang core2 { 15048489980SSeiya Wang cpu = <&cpu6>; 15148489980SSeiya Wang }; 15248489980SSeiya Wang core3 { 15348489980SSeiya Wang cpu = <&cpu7>; 15448489980SSeiya Wang }; 15548489980SSeiya Wang }; 15648489980SSeiya Wang }; 15748489980SSeiya Wang 15848489980SSeiya Wang l2_0: l2-cache0 { 15948489980SSeiya Wang compatible = "cache"; 16048489980SSeiya Wang next-level-cache = <&l3_0>; 16148489980SSeiya Wang }; 16248489980SSeiya Wang 16348489980SSeiya Wang l2_1: l2-cache1 { 16448489980SSeiya Wang compatible = "cache"; 16548489980SSeiya Wang next-level-cache = <&l3_0>; 16648489980SSeiya Wang }; 16748489980SSeiya Wang 16848489980SSeiya Wang l3_0: l3-cache { 16948489980SSeiya Wang compatible = "cache"; 17048489980SSeiya Wang }; 1719260918dSJames Liao 1729260918dSJames Liao idle-states { 1739260918dSJames Liao entry-method = "arm,psci"; 1749260918dSJames Liao cpuoff_l: cpuoff_l { 1759260918dSJames Liao compatible = "arm,idle-state"; 1769260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1779260918dSJames Liao local-timer-stop; 1789260918dSJames Liao entry-latency-us = <55>; 1799260918dSJames Liao exit-latency-us = <140>; 1809260918dSJames Liao min-residency-us = <780>; 1819260918dSJames Liao }; 1829260918dSJames Liao cpuoff_b: cpuoff_b { 1839260918dSJames Liao compatible = "arm,idle-state"; 1849260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1859260918dSJames Liao local-timer-stop; 1869260918dSJames Liao entry-latency-us = <35>; 1879260918dSJames Liao exit-latency-us = <145>; 1889260918dSJames Liao min-residency-us = <720>; 1899260918dSJames Liao }; 1909260918dSJames Liao clusteroff_l: clusteroff_l { 1919260918dSJames Liao compatible = "arm,idle-state"; 1929260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 1939260918dSJames Liao local-timer-stop; 1949260918dSJames Liao entry-latency-us = <60>; 1959260918dSJames Liao exit-latency-us = <155>; 1969260918dSJames Liao min-residency-us = <860>; 1979260918dSJames Liao }; 1989260918dSJames Liao clusteroff_b: clusteroff_b { 1999260918dSJames Liao compatible = "arm,idle-state"; 2009260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2019260918dSJames Liao local-timer-stop; 2029260918dSJames Liao entry-latency-us = <40>; 2039260918dSJames Liao exit-latency-us = <155>; 2049260918dSJames Liao min-residency-us = <780>; 2059260918dSJames Liao }; 2069260918dSJames Liao }; 20748489980SSeiya Wang }; 20848489980SSeiya Wang 20948489980SSeiya Wang pmu-a55 { 21048489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 21148489980SSeiya Wang interrupt-parent = <&gic>; 21248489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 21348489980SSeiya Wang }; 21448489980SSeiya Wang 21548489980SSeiya Wang pmu-a76 { 21648489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 21748489980SSeiya Wang interrupt-parent = <&gic>; 21848489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 21948489980SSeiya Wang }; 22048489980SSeiya Wang 22148489980SSeiya Wang psci { 22248489980SSeiya Wang compatible = "arm,psci-1.0"; 22348489980SSeiya Wang method = "smc"; 22448489980SSeiya Wang }; 22548489980SSeiya Wang 22648489980SSeiya Wang timer: timer { 22748489980SSeiya Wang compatible = "arm,armv8-timer"; 22848489980SSeiya Wang interrupt-parent = <&gic>; 22948489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 23048489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 23148489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 23248489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 23348489980SSeiya Wang clock-frequency = <13000000>; 23448489980SSeiya Wang }; 23548489980SSeiya Wang 23648489980SSeiya Wang soc { 23748489980SSeiya Wang #address-cells = <2>; 23848489980SSeiya Wang #size-cells = <2>; 23948489980SSeiya Wang compatible = "simple-bus"; 24048489980SSeiya Wang ranges; 24148489980SSeiya Wang 24248489980SSeiya Wang gic: interrupt-controller@c000000 { 24348489980SSeiya Wang compatible = "arm,gic-v3"; 24448489980SSeiya Wang #interrupt-cells = <4>; 24548489980SSeiya Wang #redistributor-regions = <1>; 24648489980SSeiya Wang interrupt-parent = <&gic>; 24748489980SSeiya Wang interrupt-controller; 24848489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 24948489980SSeiya Wang <0 0x0c040000 0 0x200000>; 25048489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 25148489980SSeiya Wang 25248489980SSeiya Wang ppi-partitions { 25348489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 25448489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 25548489980SSeiya Wang }; 25648489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 25748489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 25848489980SSeiya Wang }; 25948489980SSeiya Wang }; 26048489980SSeiya Wang }; 26148489980SSeiya Wang 2625d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 2635d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 2645d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 2655d2b897bSChun-Jie Chen #clock-cells = <1>; 2665d2b897bSChun-Jie Chen }; 2675d2b897bSChun-Jie Chen 2685d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 2695d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 2705d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 2715d2b897bSChun-Jie Chen #clock-cells = <1>; 2725d2b897bSChun-Jie Chen }; 2735d2b897bSChun-Jie Chen 2745d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 2755d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 2765d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 2775d2b897bSChun-Jie Chen #clock-cells = <1>; 2785d2b897bSChun-Jie Chen }; 2795d2b897bSChun-Jie Chen 28048489980SSeiya Wang pio: pinctrl@10005000 { 28148489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 28248489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 28348489980SSeiya Wang <0 0x11c20000 0 0x1000>, 28448489980SSeiya Wang <0 0x11d10000 0 0x1000>, 28548489980SSeiya Wang <0 0x11d30000 0 0x1000>, 28648489980SSeiya Wang <0 0x11d40000 0 0x1000>, 28748489980SSeiya Wang <0 0x11e20000 0 0x1000>, 28848489980SSeiya Wang <0 0x11e70000 0 0x1000>, 28948489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 29048489980SSeiya Wang <0 0x11f20000 0 0x1000>, 29148489980SSeiya Wang <0 0x11f30000 0 0x1000>, 29248489980SSeiya Wang <0 0x1000b000 0 0x1000>; 29348489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 29448489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 29548489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 29648489980SSeiya Wang "iocfg_tl", "eint"; 29748489980SSeiya Wang gpio-controller; 29848489980SSeiya Wang #gpio-cells = <2>; 29948489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 30048489980SSeiya Wang interrupt-controller; 30148489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 30248489980SSeiya Wang #interrupt-cells = <2>; 30348489980SSeiya Wang }; 30448489980SSeiya Wang 305*994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 306*994a71a3SChun-Jie Chen compatible = "syscon", "simple-mfd"; 307*994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 308*994a71a3SChun-Jie Chen #power-domain-cells = <1>; 309*994a71a3SChun-Jie Chen 310*994a71a3SChun-Jie Chen /* System Power Manager */ 311*994a71a3SChun-Jie Chen spm: power-controller { 312*994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 313*994a71a3SChun-Jie Chen #address-cells = <1>; 314*994a71a3SChun-Jie Chen #size-cells = <0>; 315*994a71a3SChun-Jie Chen #power-domain-cells = <1>; 316*994a71a3SChun-Jie Chen 317*994a71a3SChun-Jie Chen /* power domain of the SoC */ 318*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 319*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 320*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 321*994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 322*994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 323*994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 324*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 325*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 326*994a71a3SChun-Jie Chen }; 327*994a71a3SChun-Jie Chen 328*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 329*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 330*994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 331*994a71a3SChun-Jie Chen clock-names = "conn"; 332*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 333*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 334*994a71a3SChun-Jie Chen }; 335*994a71a3SChun-Jie Chen 336*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG0 { 337*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 338*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 339*994a71a3SChun-Jie Chen clock-names = "mfg"; 340*994a71a3SChun-Jie Chen #address-cells = <1>; 341*994a71a3SChun-Jie Chen #size-cells = <0>; 342*994a71a3SChun-Jie Chen #power-domain-cells = <1>; 343*994a71a3SChun-Jie Chen 344*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG1 { 345*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 346*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 347*994a71a3SChun-Jie Chen #address-cells = <1>; 348*994a71a3SChun-Jie Chen #size-cells = <0>; 349*994a71a3SChun-Jie Chen #power-domain-cells = <1>; 350*994a71a3SChun-Jie Chen 351*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 352*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 353*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 354*994a71a3SChun-Jie Chen }; 355*994a71a3SChun-Jie Chen 356*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 357*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 358*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 359*994a71a3SChun-Jie Chen }; 360*994a71a3SChun-Jie Chen 361*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 362*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 363*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 364*994a71a3SChun-Jie Chen }; 365*994a71a3SChun-Jie Chen 366*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 367*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 368*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 369*994a71a3SChun-Jie Chen }; 370*994a71a3SChun-Jie Chen 371*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 372*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 373*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 374*994a71a3SChun-Jie Chen }; 375*994a71a3SChun-Jie Chen }; 376*994a71a3SChun-Jie Chen }; 377*994a71a3SChun-Jie Chen 378*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 379*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 380*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 381*994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 382*994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 383*994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 384*994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 385*994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 386*994a71a3SChun-Jie Chen "disp-3"; 387*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 388*994a71a3SChun-Jie Chen #address-cells = <1>; 389*994a71a3SChun-Jie Chen #size-cells = <0>; 390*994a71a3SChun-Jie Chen #power-domain-cells = <1>; 391*994a71a3SChun-Jie Chen 392*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 393*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 394*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 395*994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 396*994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 397*994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 398*994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 399*994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 400*994a71a3SChun-Jie Chen "ipe-3"; 401*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 402*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 403*994a71a3SChun-Jie Chen }; 404*994a71a3SChun-Jie Chen 405*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 406*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 407*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 408*994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 409*994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 410*994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 411*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 412*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 413*994a71a3SChun-Jie Chen }; 414*994a71a3SChun-Jie Chen 415*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 416*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 417*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 418*994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 419*994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 420*994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 421*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 422*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 423*994a71a3SChun-Jie Chen }; 424*994a71a3SChun-Jie Chen 425*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 426*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 427*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 428*994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 429*994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 430*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 431*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 432*994a71a3SChun-Jie Chen }; 433*994a71a3SChun-Jie Chen 434*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 435*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 436*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 437*994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 438*994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 439*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 440*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 441*994a71a3SChun-Jie Chen }; 442*994a71a3SChun-Jie Chen 443*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 444*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 445*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 446*994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 447*994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 448*994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 449*994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 450*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 451*994a71a3SChun-Jie Chen #address-cells = <1>; 452*994a71a3SChun-Jie Chen #size-cells = <0>; 453*994a71a3SChun-Jie Chen #power-domain-cells = <1>; 454*994a71a3SChun-Jie Chen 455*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 456*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 457*994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 458*994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 459*994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 460*994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 461*994a71a3SChun-Jie Chen "vdec2-2"; 462*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 463*994a71a3SChun-Jie Chen }; 464*994a71a3SChun-Jie Chen }; 465*994a71a3SChun-Jie Chen 466*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 467*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 468*994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 469*994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 470*994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 471*994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 472*994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 473*994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 474*994a71a3SChun-Jie Chen "cam-3"; 475*994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 476*994a71a3SChun-Jie Chen #address-cells = <1>; 477*994a71a3SChun-Jie Chen #size-cells = <0>; 478*994a71a3SChun-Jie Chen #power-domain-cells = <1>; 479*994a71a3SChun-Jie Chen 480*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 481*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 482*994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 483*994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 484*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 485*994a71a3SChun-Jie Chen }; 486*994a71a3SChun-Jie Chen 487*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 488*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 489*994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 490*994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 491*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 492*994a71a3SChun-Jie Chen }; 493*994a71a3SChun-Jie Chen 494*994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 495*994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 496*994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 497*994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 498*994a71a3SChun-Jie Chen #power-domain-cells = <0>; 499*994a71a3SChun-Jie Chen }; 500*994a71a3SChun-Jie Chen }; 501*994a71a3SChun-Jie Chen }; 502*994a71a3SChun-Jie Chen }; 503*994a71a3SChun-Jie Chen }; 504*994a71a3SChun-Jie Chen 505d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 506d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 507d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 508d1986fbdSAllen-KH Cheng #reset-cells = <1>; 509d1986fbdSAllen-KH Cheng }; 510d1986fbdSAllen-KH Cheng 5115d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 5125d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 5135d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 5145d2b897bSChun-Jie Chen #clock-cells = <1>; 5155d2b897bSChun-Jie Chen }; 5165d2b897bSChun-Jie Chen 51748489980SSeiya Wang systimer: timer@10017000 { 51848489980SSeiya Wang compatible = "mediatek,mt8192-timer", 51948489980SSeiya Wang "mediatek,mt6765-timer"; 52048489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 52148489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 522dde3c175SAllen-KH Cheng clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 52348489980SSeiya Wang clock-names = "clk13m"; 52448489980SSeiya Wang }; 52548489980SSeiya Wang 5265d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 5275d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 5285d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 5295d2b897bSChun-Jie Chen #clock-cells = <1>; 5305d2b897bSChun-Jie Chen }; 5315d2b897bSChun-Jie Chen 53248489980SSeiya Wang uart0: serial@11002000 { 53348489980SSeiya Wang compatible = "mediatek,mt8192-uart", 53448489980SSeiya Wang "mediatek,mt6577-uart"; 53548489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 53648489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 53773ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 53848489980SSeiya Wang clock-names = "baud", "bus"; 53948489980SSeiya Wang status = "disabled"; 54048489980SSeiya Wang }; 54148489980SSeiya Wang 54248489980SSeiya Wang uart1: serial@11003000 { 54348489980SSeiya Wang compatible = "mediatek,mt8192-uart", 54448489980SSeiya Wang "mediatek,mt6577-uart"; 54548489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 54648489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 54773ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 54848489980SSeiya Wang clock-names = "baud", "bus"; 54948489980SSeiya Wang status = "disabled"; 55048489980SSeiya Wang }; 55148489980SSeiya Wang 5525d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 5535d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 5545d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 5555d2b897bSChun-Jie Chen #clock-cells = <1>; 5565d2b897bSChun-Jie Chen }; 5575d2b897bSChun-Jie Chen 55848489980SSeiya Wang spi0: spi@1100a000 { 55948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 56048489980SSeiya Wang "mediatek,mt6765-spi"; 56148489980SSeiya Wang #address-cells = <1>; 56248489980SSeiya Wang #size-cells = <0>; 56348489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 56448489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 5657f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5667f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5677f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 56848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 56948489980SSeiya Wang status = "disabled"; 57048489980SSeiya Wang }; 57148489980SSeiya Wang 57248489980SSeiya Wang spi1: spi@11010000 { 57348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 57448489980SSeiya Wang "mediatek,mt6765-spi"; 57548489980SSeiya Wang #address-cells = <1>; 57648489980SSeiya Wang #size-cells = <0>; 57748489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 57848489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 5797f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5807f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5817f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 58248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 58348489980SSeiya Wang status = "disabled"; 58448489980SSeiya Wang }; 58548489980SSeiya Wang 58648489980SSeiya Wang spi2: spi@11012000 { 58748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 58848489980SSeiya Wang "mediatek,mt6765-spi"; 58948489980SSeiya Wang #address-cells = <1>; 59048489980SSeiya Wang #size-cells = <0>; 59148489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 59248489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 5937f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5947f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5957f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 59648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 59748489980SSeiya Wang status = "disabled"; 59848489980SSeiya Wang }; 59948489980SSeiya Wang 60048489980SSeiya Wang spi3: spi@11013000 { 60148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 60248489980SSeiya Wang "mediatek,mt6765-spi"; 60348489980SSeiya Wang #address-cells = <1>; 60448489980SSeiya Wang #size-cells = <0>; 60548489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 60648489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 6077f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6087f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6097f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 61048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 61148489980SSeiya Wang status = "disabled"; 61248489980SSeiya Wang }; 61348489980SSeiya Wang 61448489980SSeiya Wang spi4: spi@11018000 { 61548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 61648489980SSeiya Wang "mediatek,mt6765-spi"; 61748489980SSeiya Wang #address-cells = <1>; 61848489980SSeiya Wang #size-cells = <0>; 61948489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 62048489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 6217f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6227f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6237f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 62448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 62548489980SSeiya Wang status = "disabled"; 62648489980SSeiya Wang }; 62748489980SSeiya Wang 62848489980SSeiya Wang spi5: spi@11019000 { 62948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 63048489980SSeiya Wang "mediatek,mt6765-spi"; 63148489980SSeiya Wang #address-cells = <1>; 63248489980SSeiya Wang #size-cells = <0>; 63348489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 63448489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 6357f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6367f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6377f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 63848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 63948489980SSeiya Wang status = "disabled"; 64048489980SSeiya Wang }; 64148489980SSeiya Wang 64248489980SSeiya Wang spi6: spi@1101d000 { 64348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 64448489980SSeiya Wang "mediatek,mt6765-spi"; 64548489980SSeiya Wang #address-cells = <1>; 64648489980SSeiya Wang #size-cells = <0>; 64748489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 64848489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 6497f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6507f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6517f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 65248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 65348489980SSeiya Wang status = "disabled"; 65448489980SSeiya Wang }; 65548489980SSeiya Wang 65648489980SSeiya Wang spi7: spi@1101e000 { 65748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 65848489980SSeiya Wang "mediatek,mt6765-spi"; 65948489980SSeiya Wang #address-cells = <1>; 66048489980SSeiya Wang #size-cells = <0>; 66148489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 66248489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 6637f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6647f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6657f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 66648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 66748489980SSeiya Wang status = "disabled"; 66848489980SSeiya Wang }; 66948489980SSeiya Wang 670d0a197a0Sbayi cheng nor_flash: spi@11234000 { 671d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 672d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 673d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 674aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 675aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 676aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 677d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 678aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 679aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 680d0a197a0Sbayi cheng #address-cells = <1>; 681d0a197a0Sbayi cheng #size-cells = <0>; 682d0a197a0Sbayi cheng status = "disable"; 683d0a197a0Sbayi cheng }; 684d0a197a0Sbayi cheng 6855d2b897bSChun-Jie Chen audsys: clock-controller@11210000 { 6865d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-audsys", "syscon"; 6875d2b897bSChun-Jie Chen reg = <0 0x11210000 0 0x1000>; 6885d2b897bSChun-Jie Chen #clock-cells = <1>; 6895d2b897bSChun-Jie Chen }; 6905d2b897bSChun-Jie Chen 6917f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 69248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 69348489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 69448489980SSeiya Wang <0 0x10217300 0 0x80>; 69548489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 69622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 69722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 69848489980SSeiya Wang clock-names = "main", "dma"; 69948489980SSeiya Wang clock-div = <1>; 70048489980SSeiya Wang #address-cells = <1>; 70148489980SSeiya Wang #size-cells = <0>; 70248489980SSeiya Wang status = "disabled"; 70348489980SSeiya Wang }; 70448489980SSeiya Wang 7055d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 7065d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 7075d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 7085d2b897bSChun-Jie Chen #clock-cells = <1>; 7095d2b897bSChun-Jie Chen }; 7105d2b897bSChun-Jie Chen 7117f1a9f47SFabien Parent i2c7: i2c@11d00000 { 71248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 71348489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 71448489980SSeiya Wang <0 0x10217600 0 0x180>; 71548489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 71622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 71722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 71848489980SSeiya Wang clock-names = "main", "dma"; 71948489980SSeiya Wang clock-div = <1>; 72048489980SSeiya Wang #address-cells = <1>; 72148489980SSeiya Wang #size-cells = <0>; 72248489980SSeiya Wang status = "disabled"; 72348489980SSeiya Wang }; 72448489980SSeiya Wang 7257f1a9f47SFabien Parent i2c8: i2c@11d01000 { 72648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 72748489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 72848489980SSeiya Wang <0 0x10217780 0 0x180>; 72948489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 73022623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 73122623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 73248489980SSeiya Wang clock-names = "main", "dma"; 73348489980SSeiya Wang clock-div = <1>; 73448489980SSeiya Wang #address-cells = <1>; 73548489980SSeiya Wang #size-cells = <0>; 73648489980SSeiya Wang status = "disabled"; 73748489980SSeiya Wang }; 73848489980SSeiya Wang 7397f1a9f47SFabien Parent i2c9: i2c@11d02000 { 74048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 74148489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 74248489980SSeiya Wang <0 0x10217900 0 0x180>; 74348489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 74422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 74522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 74648489980SSeiya Wang clock-names = "main", "dma"; 74748489980SSeiya Wang clock-div = <1>; 74848489980SSeiya Wang #address-cells = <1>; 74948489980SSeiya Wang #size-cells = <0>; 75048489980SSeiya Wang status = "disabled"; 75148489980SSeiya Wang }; 75248489980SSeiya Wang 7535d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 7545d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 7555d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 7565d2b897bSChun-Jie Chen #clock-cells = <1>; 7575d2b897bSChun-Jie Chen }; 7585d2b897bSChun-Jie Chen 7597f1a9f47SFabien Parent i2c1: i2c@11d20000 { 76048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 76148489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 76248489980SSeiya Wang <0 0x10217100 0 0x80>; 76348489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 76422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 76522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 76648489980SSeiya Wang clock-names = "main", "dma"; 76748489980SSeiya Wang clock-div = <1>; 76848489980SSeiya Wang #address-cells = <1>; 76948489980SSeiya Wang #size-cells = <0>; 77048489980SSeiya Wang status = "disabled"; 77148489980SSeiya Wang }; 77248489980SSeiya Wang 7737f1a9f47SFabien Parent i2c2: i2c@11d21000 { 77448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 77548489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 77648489980SSeiya Wang <0 0x10217180 0 0x180>; 77748489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 77822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 77922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 78048489980SSeiya Wang clock-names = "main", "dma"; 78148489980SSeiya Wang clock-div = <1>; 78248489980SSeiya Wang #address-cells = <1>; 78348489980SSeiya Wang #size-cells = <0>; 78448489980SSeiya Wang status = "disabled"; 78548489980SSeiya Wang }; 78648489980SSeiya Wang 7877f1a9f47SFabien Parent i2c4: i2c@11d22000 { 78848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 78948489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 79048489980SSeiya Wang <0 0x10217380 0 0x180>; 79148489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 79222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 79322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 79448489980SSeiya Wang clock-names = "main", "dma"; 79548489980SSeiya Wang clock-div = <1>; 79648489980SSeiya Wang #address-cells = <1>; 79748489980SSeiya Wang #size-cells = <0>; 79848489980SSeiya Wang status = "disabled"; 79948489980SSeiya Wang }; 80048489980SSeiya Wang 8015d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 8025d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 8035d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 8045d2b897bSChun-Jie Chen #clock-cells = <1>; 8055d2b897bSChun-Jie Chen }; 8065d2b897bSChun-Jie Chen 8077f1a9f47SFabien Parent i2c5: i2c@11e00000 { 80848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 80948489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 81048489980SSeiya Wang <0 0x10217500 0 0x80>; 81148489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 81222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 81322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 81448489980SSeiya Wang clock-names = "main", "dma"; 81548489980SSeiya Wang clock-div = <1>; 81648489980SSeiya Wang #address-cells = <1>; 81748489980SSeiya Wang #size-cells = <0>; 81848489980SSeiya Wang status = "disabled"; 81948489980SSeiya Wang }; 82048489980SSeiya Wang 8215d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 8225d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 8235d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 8245d2b897bSChun-Jie Chen #clock-cells = <1>; 8255d2b897bSChun-Jie Chen }; 8265d2b897bSChun-Jie Chen 8277f1a9f47SFabien Parent i2c0: i2c@11f00000 { 82848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 82948489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 83048489980SSeiya Wang <0 0x10217080 0 0x80>; 83148489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 83222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 83322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 83448489980SSeiya Wang clock-names = "main", "dma"; 83548489980SSeiya Wang clock-div = <1>; 83648489980SSeiya Wang #address-cells = <1>; 83748489980SSeiya Wang #size-cells = <0>; 83848489980SSeiya Wang status = "disabled"; 83948489980SSeiya Wang }; 84048489980SSeiya Wang 8417f1a9f47SFabien Parent i2c6: i2c@11f01000 { 84248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 84348489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 84448489980SSeiya Wang <0 0x10217580 0 0x80>; 84548489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 84622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 84722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 84848489980SSeiya Wang clock-names = "main", "dma"; 84948489980SSeiya Wang clock-div = <1>; 85048489980SSeiya Wang #address-cells = <1>; 85148489980SSeiya Wang #size-cells = <0>; 85248489980SSeiya Wang status = "disabled"; 85348489980SSeiya Wang }; 8545d2b897bSChun-Jie Chen 8555d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 8565d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 8575d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 8585d2b897bSChun-Jie Chen #clock-cells = <1>; 8595d2b897bSChun-Jie Chen }; 8605d2b897bSChun-Jie Chen 8615d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 8625d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 8635d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 8645d2b897bSChun-Jie Chen #clock-cells = <1>; 8655d2b897bSChun-Jie Chen }; 8665d2b897bSChun-Jie Chen 8675d2b897bSChun-Jie Chen msdc: clock-controller@11f60000 { 8685d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc"; 8695d2b897bSChun-Jie Chen reg = <0 0x11f60000 0 0x1000>; 8705d2b897bSChun-Jie Chen #clock-cells = <1>; 8715d2b897bSChun-Jie Chen }; 8725d2b897bSChun-Jie Chen 8735d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 8745d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 8755d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 8765d2b897bSChun-Jie Chen #clock-cells = <1>; 8775d2b897bSChun-Jie Chen }; 8785d2b897bSChun-Jie Chen 8795d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 8805d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 8815d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 8825d2b897bSChun-Jie Chen #clock-cells = <1>; 8835d2b897bSChun-Jie Chen }; 8845d2b897bSChun-Jie Chen 8855d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 8865d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 8875d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 8885d2b897bSChun-Jie Chen #clock-cells = <1>; 8895d2b897bSChun-Jie Chen }; 8905d2b897bSChun-Jie Chen 8915d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 8925d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 8935d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 8945d2b897bSChun-Jie Chen #clock-cells = <1>; 8955d2b897bSChun-Jie Chen }; 8965d2b897bSChun-Jie Chen 8975d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 8985d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 8995d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 9005d2b897bSChun-Jie Chen #clock-cells = <1>; 9015d2b897bSChun-Jie Chen }; 9025d2b897bSChun-Jie Chen 9035d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 9045d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 9055d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 9065d2b897bSChun-Jie Chen #clock-cells = <1>; 9075d2b897bSChun-Jie Chen }; 9085d2b897bSChun-Jie Chen 9095d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 9105d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 9115d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 9125d2b897bSChun-Jie Chen #clock-cells = <1>; 9135d2b897bSChun-Jie Chen }; 9145d2b897bSChun-Jie Chen 9155d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 9165d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 9175d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 9185d2b897bSChun-Jie Chen #clock-cells = <1>; 9195d2b897bSChun-Jie Chen }; 9205d2b897bSChun-Jie Chen 9215d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 9225d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 9235d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 9245d2b897bSChun-Jie Chen #clock-cells = <1>; 9255d2b897bSChun-Jie Chen }; 9265d2b897bSChun-Jie Chen 9275d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 9285d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 9295d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 9305d2b897bSChun-Jie Chen #clock-cells = <1>; 9315d2b897bSChun-Jie Chen }; 9325d2b897bSChun-Jie Chen 9335d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 9345d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 9355d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 9365d2b897bSChun-Jie Chen #clock-cells = <1>; 9375d2b897bSChun-Jie Chen }; 9385d2b897bSChun-Jie Chen 9395d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 9405d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 9415d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 9425d2b897bSChun-Jie Chen #clock-cells = <1>; 9435d2b897bSChun-Jie Chen }; 9445d2b897bSChun-Jie Chen 9455d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 9465d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 9475d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 9485d2b897bSChun-Jie Chen #clock-cells = <1>; 9495d2b897bSChun-Jie Chen }; 95048489980SSeiya Wang }; 95148489980SSeiya Wang}; 952