148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 848489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 1048489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 1148489980SSeiya Wang 1248489980SSeiya Wang/ { 1348489980SSeiya Wang compatible = "mediatek,mt8192"; 1448489980SSeiya Wang interrupt-parent = <&gic>; 1548489980SSeiya Wang #address-cells = <2>; 1648489980SSeiya Wang #size-cells = <2>; 1748489980SSeiya Wang 1848489980SSeiya Wang clk26m: oscillator0 { 1948489980SSeiya Wang compatible = "fixed-clock"; 2048489980SSeiya Wang #clock-cells = <0>; 2148489980SSeiya Wang clock-frequency = <26000000>; 2248489980SSeiya Wang clock-output-names = "clk26m"; 2348489980SSeiya Wang }; 2448489980SSeiya Wang 2548489980SSeiya Wang clk32k: oscillator1 { 2648489980SSeiya Wang compatible = "fixed-clock"; 2748489980SSeiya Wang #clock-cells = <0>; 2848489980SSeiya Wang clock-frequency = <32768>; 2948489980SSeiya Wang clock-output-names = "clk32k"; 3048489980SSeiya Wang }; 3148489980SSeiya Wang 3248489980SSeiya Wang cpus { 3348489980SSeiya Wang #address-cells = <1>; 3448489980SSeiya Wang #size-cells = <0>; 3548489980SSeiya Wang 3648489980SSeiya Wang cpu0: cpu@0 { 3748489980SSeiya Wang device_type = "cpu"; 3848489980SSeiya Wang compatible = "arm,cortex-a55"; 3948489980SSeiya Wang reg = <0x000>; 4048489980SSeiya Wang enable-method = "psci"; 4148489980SSeiya Wang clock-frequency = <1701000000>; 42*9260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 4348489980SSeiya Wang next-level-cache = <&l2_0>; 4448489980SSeiya Wang capacity-dmips-mhz = <530>; 4548489980SSeiya Wang }; 4648489980SSeiya Wang 4748489980SSeiya Wang cpu1: cpu@100 { 4848489980SSeiya Wang device_type = "cpu"; 4948489980SSeiya Wang compatible = "arm,cortex-a55"; 5048489980SSeiya Wang reg = <0x100>; 5148489980SSeiya Wang enable-method = "psci"; 5248489980SSeiya Wang clock-frequency = <1701000000>; 53*9260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 5448489980SSeiya Wang next-level-cache = <&l2_0>; 5548489980SSeiya Wang capacity-dmips-mhz = <530>; 5648489980SSeiya Wang }; 5748489980SSeiya Wang 5848489980SSeiya Wang cpu2: cpu@200 { 5948489980SSeiya Wang device_type = "cpu"; 6048489980SSeiya Wang compatible = "arm,cortex-a55"; 6148489980SSeiya Wang reg = <0x200>; 6248489980SSeiya Wang enable-method = "psci"; 6348489980SSeiya Wang clock-frequency = <1701000000>; 64*9260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 6548489980SSeiya Wang next-level-cache = <&l2_0>; 6648489980SSeiya Wang capacity-dmips-mhz = <530>; 6748489980SSeiya Wang }; 6848489980SSeiya Wang 6948489980SSeiya Wang cpu3: cpu@300 { 7048489980SSeiya Wang device_type = "cpu"; 7148489980SSeiya Wang compatible = "arm,cortex-a55"; 7248489980SSeiya Wang reg = <0x300>; 7348489980SSeiya Wang enable-method = "psci"; 7448489980SSeiya Wang clock-frequency = <1701000000>; 75*9260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 7648489980SSeiya Wang next-level-cache = <&l2_0>; 7748489980SSeiya Wang capacity-dmips-mhz = <530>; 7848489980SSeiya Wang }; 7948489980SSeiya Wang 8048489980SSeiya Wang cpu4: cpu@400 { 8148489980SSeiya Wang device_type = "cpu"; 8248489980SSeiya Wang compatible = "arm,cortex-a76"; 8348489980SSeiya Wang reg = <0x400>; 8448489980SSeiya Wang enable-method = "psci"; 8548489980SSeiya Wang clock-frequency = <2171000000>; 86*9260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 8748489980SSeiya Wang next-level-cache = <&l2_1>; 8848489980SSeiya Wang capacity-dmips-mhz = <1024>; 8948489980SSeiya Wang }; 9048489980SSeiya Wang 9148489980SSeiya Wang cpu5: cpu@500 { 9248489980SSeiya Wang device_type = "cpu"; 9348489980SSeiya Wang compatible = "arm,cortex-a76"; 9448489980SSeiya Wang reg = <0x500>; 9548489980SSeiya Wang enable-method = "psci"; 9648489980SSeiya Wang clock-frequency = <2171000000>; 97*9260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 9848489980SSeiya Wang next-level-cache = <&l2_1>; 9948489980SSeiya Wang capacity-dmips-mhz = <1024>; 10048489980SSeiya Wang }; 10148489980SSeiya Wang 10248489980SSeiya Wang cpu6: cpu@600 { 10348489980SSeiya Wang device_type = "cpu"; 10448489980SSeiya Wang compatible = "arm,cortex-a76"; 10548489980SSeiya Wang reg = <0x600>; 10648489980SSeiya Wang enable-method = "psci"; 10748489980SSeiya Wang clock-frequency = <2171000000>; 108*9260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 10948489980SSeiya Wang next-level-cache = <&l2_1>; 11048489980SSeiya Wang capacity-dmips-mhz = <1024>; 11148489980SSeiya Wang }; 11248489980SSeiya Wang 11348489980SSeiya Wang cpu7: cpu@700 { 11448489980SSeiya Wang device_type = "cpu"; 11548489980SSeiya Wang compatible = "arm,cortex-a76"; 11648489980SSeiya Wang reg = <0x700>; 11748489980SSeiya Wang enable-method = "psci"; 11848489980SSeiya Wang clock-frequency = <2171000000>; 119*9260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 12048489980SSeiya Wang next-level-cache = <&l2_1>; 12148489980SSeiya Wang capacity-dmips-mhz = <1024>; 12248489980SSeiya Wang }; 12348489980SSeiya Wang 12448489980SSeiya Wang cpu-map { 12548489980SSeiya Wang cluster0 { 12648489980SSeiya Wang core0 { 12748489980SSeiya Wang cpu = <&cpu0>; 12848489980SSeiya Wang }; 12948489980SSeiya Wang core1 { 13048489980SSeiya Wang cpu = <&cpu1>; 13148489980SSeiya Wang }; 13248489980SSeiya Wang core2 { 13348489980SSeiya Wang cpu = <&cpu2>; 13448489980SSeiya Wang }; 13548489980SSeiya Wang core3 { 13648489980SSeiya Wang cpu = <&cpu3>; 13748489980SSeiya Wang }; 13848489980SSeiya Wang }; 13948489980SSeiya Wang 14048489980SSeiya Wang cluster1 { 14148489980SSeiya Wang core0 { 14248489980SSeiya Wang cpu = <&cpu4>; 14348489980SSeiya Wang }; 14448489980SSeiya Wang core1 { 14548489980SSeiya Wang cpu = <&cpu5>; 14648489980SSeiya Wang }; 14748489980SSeiya Wang core2 { 14848489980SSeiya Wang cpu = <&cpu6>; 14948489980SSeiya Wang }; 15048489980SSeiya Wang core3 { 15148489980SSeiya Wang cpu = <&cpu7>; 15248489980SSeiya Wang }; 15348489980SSeiya Wang }; 15448489980SSeiya Wang }; 15548489980SSeiya Wang 15648489980SSeiya Wang l2_0: l2-cache0 { 15748489980SSeiya Wang compatible = "cache"; 15848489980SSeiya Wang next-level-cache = <&l3_0>; 15948489980SSeiya Wang }; 16048489980SSeiya Wang 16148489980SSeiya Wang l2_1: l2-cache1 { 16248489980SSeiya Wang compatible = "cache"; 16348489980SSeiya Wang next-level-cache = <&l3_0>; 16448489980SSeiya Wang }; 16548489980SSeiya Wang 16648489980SSeiya Wang l3_0: l3-cache { 16748489980SSeiya Wang compatible = "cache"; 16848489980SSeiya Wang }; 169*9260918dSJames Liao 170*9260918dSJames Liao idle-states { 171*9260918dSJames Liao entry-method = "arm,psci"; 172*9260918dSJames Liao cpuoff_l: cpuoff_l { 173*9260918dSJames Liao compatible = "arm,idle-state"; 174*9260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 175*9260918dSJames Liao local-timer-stop; 176*9260918dSJames Liao entry-latency-us = <55>; 177*9260918dSJames Liao exit-latency-us = <140>; 178*9260918dSJames Liao min-residency-us = <780>; 179*9260918dSJames Liao }; 180*9260918dSJames Liao cpuoff_b: cpuoff_b { 181*9260918dSJames Liao compatible = "arm,idle-state"; 182*9260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 183*9260918dSJames Liao local-timer-stop; 184*9260918dSJames Liao entry-latency-us = <35>; 185*9260918dSJames Liao exit-latency-us = <145>; 186*9260918dSJames Liao min-residency-us = <720>; 187*9260918dSJames Liao }; 188*9260918dSJames Liao clusteroff_l: clusteroff_l { 189*9260918dSJames Liao compatible = "arm,idle-state"; 190*9260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 191*9260918dSJames Liao local-timer-stop; 192*9260918dSJames Liao entry-latency-us = <60>; 193*9260918dSJames Liao exit-latency-us = <155>; 194*9260918dSJames Liao min-residency-us = <860>; 195*9260918dSJames Liao }; 196*9260918dSJames Liao clusteroff_b: clusteroff_b { 197*9260918dSJames Liao compatible = "arm,idle-state"; 198*9260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 199*9260918dSJames Liao local-timer-stop; 200*9260918dSJames Liao entry-latency-us = <40>; 201*9260918dSJames Liao exit-latency-us = <155>; 202*9260918dSJames Liao min-residency-us = <780>; 203*9260918dSJames Liao }; 204*9260918dSJames Liao }; 20548489980SSeiya Wang }; 20648489980SSeiya Wang 20748489980SSeiya Wang pmu-a55 { 20848489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 20948489980SSeiya Wang interrupt-parent = <&gic>; 21048489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 21148489980SSeiya Wang }; 21248489980SSeiya Wang 21348489980SSeiya Wang pmu-a76 { 21448489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 21548489980SSeiya Wang interrupt-parent = <&gic>; 21648489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 21748489980SSeiya Wang }; 21848489980SSeiya Wang 21948489980SSeiya Wang psci { 22048489980SSeiya Wang compatible = "arm,psci-1.0"; 22148489980SSeiya Wang method = "smc"; 22248489980SSeiya Wang }; 22348489980SSeiya Wang 22448489980SSeiya Wang timer: timer { 22548489980SSeiya Wang compatible = "arm,armv8-timer"; 22648489980SSeiya Wang interrupt-parent = <&gic>; 22748489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 22848489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 22948489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 23048489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 23148489980SSeiya Wang clock-frequency = <13000000>; 23248489980SSeiya Wang }; 23348489980SSeiya Wang 23448489980SSeiya Wang soc { 23548489980SSeiya Wang #address-cells = <2>; 23648489980SSeiya Wang #size-cells = <2>; 23748489980SSeiya Wang compatible = "simple-bus"; 23848489980SSeiya Wang ranges; 23948489980SSeiya Wang 24048489980SSeiya Wang gic: interrupt-controller@c000000 { 24148489980SSeiya Wang compatible = "arm,gic-v3"; 24248489980SSeiya Wang #interrupt-cells = <4>; 24348489980SSeiya Wang #redistributor-regions = <1>; 24448489980SSeiya Wang interrupt-parent = <&gic>; 24548489980SSeiya Wang interrupt-controller; 24648489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 24748489980SSeiya Wang <0 0x0c040000 0 0x200000>; 24848489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 24948489980SSeiya Wang 25048489980SSeiya Wang ppi-partitions { 25148489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 25248489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 25348489980SSeiya Wang }; 25448489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 25548489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 25648489980SSeiya Wang }; 25748489980SSeiya Wang }; 25848489980SSeiya Wang }; 25948489980SSeiya Wang 26048489980SSeiya Wang pio: pinctrl@10005000 { 26148489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 26248489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 26348489980SSeiya Wang <0 0x11c20000 0 0x1000>, 26448489980SSeiya Wang <0 0x11d10000 0 0x1000>, 26548489980SSeiya Wang <0 0x11d30000 0 0x1000>, 26648489980SSeiya Wang <0 0x11d40000 0 0x1000>, 26748489980SSeiya Wang <0 0x11e20000 0 0x1000>, 26848489980SSeiya Wang <0 0x11e70000 0 0x1000>, 26948489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 27048489980SSeiya Wang <0 0x11f20000 0 0x1000>, 27148489980SSeiya Wang <0 0x11f30000 0 0x1000>, 27248489980SSeiya Wang <0 0x1000b000 0 0x1000>; 27348489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 27448489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 27548489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 27648489980SSeiya Wang "iocfg_tl", "eint"; 27748489980SSeiya Wang gpio-controller; 27848489980SSeiya Wang #gpio-cells = <2>; 27948489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 28048489980SSeiya Wang interrupt-controller; 28148489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 28248489980SSeiya Wang #interrupt-cells = <2>; 28348489980SSeiya Wang }; 28448489980SSeiya Wang 28548489980SSeiya Wang systimer: timer@10017000 { 28648489980SSeiya Wang compatible = "mediatek,mt8192-timer", 28748489980SSeiya Wang "mediatek,mt6765-timer"; 28848489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 28948489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 29048489980SSeiya Wang clocks = <&clk26m>; 29148489980SSeiya Wang clock-names = "clk13m"; 29248489980SSeiya Wang }; 29348489980SSeiya Wang 29448489980SSeiya Wang uart0: serial@11002000 { 29548489980SSeiya Wang compatible = "mediatek,mt8192-uart", 29648489980SSeiya Wang "mediatek,mt6577-uart"; 29748489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 29848489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 29948489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 30048489980SSeiya Wang clock-names = "baud", "bus"; 30148489980SSeiya Wang status = "disabled"; 30248489980SSeiya Wang }; 30348489980SSeiya Wang 30448489980SSeiya Wang uart1: serial@11003000 { 30548489980SSeiya Wang compatible = "mediatek,mt8192-uart", 30648489980SSeiya Wang "mediatek,mt6577-uart"; 30748489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 30848489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 30948489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 31048489980SSeiya Wang clock-names = "baud", "bus"; 31148489980SSeiya Wang status = "disabled"; 31248489980SSeiya Wang }; 31348489980SSeiya Wang 31448489980SSeiya Wang spi0: spi@1100a000 { 31548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 31648489980SSeiya Wang "mediatek,mt6765-spi"; 31748489980SSeiya Wang #address-cells = <1>; 31848489980SSeiya Wang #size-cells = <0>; 31948489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 32048489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 32148489980SSeiya Wang clocks = <&clk26m>, 32248489980SSeiya Wang <&clk26m>, 32348489980SSeiya Wang <&clk26m>; 32448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 32548489980SSeiya Wang status = "disabled"; 32648489980SSeiya Wang }; 32748489980SSeiya Wang 32848489980SSeiya Wang spi1: spi@11010000 { 32948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 33048489980SSeiya Wang "mediatek,mt6765-spi"; 33148489980SSeiya Wang #address-cells = <1>; 33248489980SSeiya Wang #size-cells = <0>; 33348489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 33448489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 33548489980SSeiya Wang clocks = <&clk26m>, 33648489980SSeiya Wang <&clk26m>, 33748489980SSeiya Wang <&clk26m>; 33848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 33948489980SSeiya Wang status = "disabled"; 34048489980SSeiya Wang }; 34148489980SSeiya Wang 34248489980SSeiya Wang spi2: spi@11012000 { 34348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 34448489980SSeiya Wang "mediatek,mt6765-spi"; 34548489980SSeiya Wang #address-cells = <1>; 34648489980SSeiya Wang #size-cells = <0>; 34748489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 34848489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 34948489980SSeiya Wang clocks = <&clk26m>, 35048489980SSeiya Wang <&clk26m>, 35148489980SSeiya Wang <&clk26m>; 35248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 35348489980SSeiya Wang status = "disabled"; 35448489980SSeiya Wang }; 35548489980SSeiya Wang 35648489980SSeiya Wang spi3: spi@11013000 { 35748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 35848489980SSeiya Wang "mediatek,mt6765-spi"; 35948489980SSeiya Wang #address-cells = <1>; 36048489980SSeiya Wang #size-cells = <0>; 36148489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 36248489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 36348489980SSeiya Wang clocks = <&clk26m>, 36448489980SSeiya Wang <&clk26m>, 36548489980SSeiya Wang <&clk26m>; 36648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 36748489980SSeiya Wang status = "disabled"; 36848489980SSeiya Wang }; 36948489980SSeiya Wang 37048489980SSeiya Wang spi4: spi@11018000 { 37148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 37248489980SSeiya Wang "mediatek,mt6765-spi"; 37348489980SSeiya Wang #address-cells = <1>; 37448489980SSeiya Wang #size-cells = <0>; 37548489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 37648489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 37748489980SSeiya Wang clocks = <&clk26m>, 37848489980SSeiya Wang <&clk26m>, 37948489980SSeiya Wang <&clk26m>; 38048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 38148489980SSeiya Wang status = "disabled"; 38248489980SSeiya Wang }; 38348489980SSeiya Wang 38448489980SSeiya Wang spi5: spi@11019000 { 38548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 38648489980SSeiya Wang "mediatek,mt6765-spi"; 38748489980SSeiya Wang #address-cells = <1>; 38848489980SSeiya Wang #size-cells = <0>; 38948489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 39048489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 39148489980SSeiya Wang clocks = <&clk26m>, 39248489980SSeiya Wang <&clk26m>, 39348489980SSeiya Wang <&clk26m>; 39448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 39548489980SSeiya Wang status = "disabled"; 39648489980SSeiya Wang }; 39748489980SSeiya Wang 39848489980SSeiya Wang spi6: spi@1101d000 { 39948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 40048489980SSeiya Wang "mediatek,mt6765-spi"; 40148489980SSeiya Wang #address-cells = <1>; 40248489980SSeiya Wang #size-cells = <0>; 40348489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 40448489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 40548489980SSeiya Wang clocks = <&clk26m>, 40648489980SSeiya Wang <&clk26m>, 40748489980SSeiya Wang <&clk26m>; 40848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 40948489980SSeiya Wang status = "disabled"; 41048489980SSeiya Wang }; 41148489980SSeiya Wang 41248489980SSeiya Wang spi7: spi@1101e000 { 41348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 41448489980SSeiya Wang "mediatek,mt6765-spi"; 41548489980SSeiya Wang #address-cells = <1>; 41648489980SSeiya Wang #size-cells = <0>; 41748489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 41848489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 41948489980SSeiya Wang clocks = <&clk26m>, 42048489980SSeiya Wang <&clk26m>, 42148489980SSeiya Wang <&clk26m>; 42248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 42348489980SSeiya Wang status = "disabled"; 42448489980SSeiya Wang }; 42548489980SSeiya Wang 426d0a197a0Sbayi cheng nor_flash: spi@11234000 { 427d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 428d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 429d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 430d0a197a0Sbayi cheng clocks = <&clk26m>, 431d0a197a0Sbayi cheng <&clk26m>, 432d0a197a0Sbayi cheng <&clk26m>; 433d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 434d0a197a0Sbayi cheng #address-cells = <1>; 435d0a197a0Sbayi cheng #size-cells = <0>; 436d0a197a0Sbayi cheng status = "disable"; 437d0a197a0Sbayi cheng }; 438d0a197a0Sbayi cheng 43948489980SSeiya Wang i2c3: i2c3@11cb0000 { 44048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 44148489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 44248489980SSeiya Wang <0 0x10217300 0 0x80>; 44348489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 44448489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 44548489980SSeiya Wang clock-names = "main", "dma"; 44648489980SSeiya Wang clock-div = <1>; 44748489980SSeiya Wang #address-cells = <1>; 44848489980SSeiya Wang #size-cells = <0>; 44948489980SSeiya Wang status = "disabled"; 45048489980SSeiya Wang }; 45148489980SSeiya Wang 45248489980SSeiya Wang i2c7: i2c7@11d00000 { 45348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 45448489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 45548489980SSeiya Wang <0 0x10217600 0 0x180>; 45648489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 45748489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 45848489980SSeiya Wang clock-names = "main", "dma"; 45948489980SSeiya Wang clock-div = <1>; 46048489980SSeiya Wang #address-cells = <1>; 46148489980SSeiya Wang #size-cells = <0>; 46248489980SSeiya Wang status = "disabled"; 46348489980SSeiya Wang }; 46448489980SSeiya Wang 46548489980SSeiya Wang i2c8: i2c8@11d01000 { 46648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 46748489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 46848489980SSeiya Wang <0 0x10217780 0 0x180>; 46948489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 47048489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 47148489980SSeiya Wang clock-names = "main", "dma"; 47248489980SSeiya Wang clock-div = <1>; 47348489980SSeiya Wang #address-cells = <1>; 47448489980SSeiya Wang #size-cells = <0>; 47548489980SSeiya Wang status = "disabled"; 47648489980SSeiya Wang }; 47748489980SSeiya Wang 47848489980SSeiya Wang i2c9: i2c9@11d02000 { 47948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 48048489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 48148489980SSeiya Wang <0 0x10217900 0 0x180>; 48248489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 48348489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 48448489980SSeiya Wang clock-names = "main", "dma"; 48548489980SSeiya Wang clock-div = <1>; 48648489980SSeiya Wang #address-cells = <1>; 48748489980SSeiya Wang #size-cells = <0>; 48848489980SSeiya Wang status = "disabled"; 48948489980SSeiya Wang }; 49048489980SSeiya Wang 49148489980SSeiya Wang i2c1: i2c1@11d20000 { 49248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 49348489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 49448489980SSeiya Wang <0 0x10217100 0 0x80>; 49548489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 49648489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 49748489980SSeiya Wang clock-names = "main", "dma"; 49848489980SSeiya Wang clock-div = <1>; 49948489980SSeiya Wang #address-cells = <1>; 50048489980SSeiya Wang #size-cells = <0>; 50148489980SSeiya Wang status = "disabled"; 50248489980SSeiya Wang }; 50348489980SSeiya Wang 50448489980SSeiya Wang i2c2: i2c2@11d21000 { 50548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 50648489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 50748489980SSeiya Wang <0 0x10217180 0 0x180>; 50848489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 50948489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 51048489980SSeiya Wang clock-names = "main", "dma"; 51148489980SSeiya Wang clock-div = <1>; 51248489980SSeiya Wang #address-cells = <1>; 51348489980SSeiya Wang #size-cells = <0>; 51448489980SSeiya Wang status = "disabled"; 51548489980SSeiya Wang }; 51648489980SSeiya Wang 51748489980SSeiya Wang i2c4: i2c4@11d22000 { 51848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 51948489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 52048489980SSeiya Wang <0 0x10217380 0 0x180>; 52148489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 52248489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 52348489980SSeiya Wang clock-names = "main", "dma"; 52448489980SSeiya Wang clock-div = <1>; 52548489980SSeiya Wang #address-cells = <1>; 52648489980SSeiya Wang #size-cells = <0>; 52748489980SSeiya Wang status = "disabled"; 52848489980SSeiya Wang }; 52948489980SSeiya Wang 53048489980SSeiya Wang i2c5: i2c5@11e00000 { 53148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 53248489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 53348489980SSeiya Wang <0 0x10217500 0 0x80>; 53448489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 53548489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 53648489980SSeiya Wang clock-names = "main", "dma"; 53748489980SSeiya Wang clock-div = <1>; 53848489980SSeiya Wang #address-cells = <1>; 53948489980SSeiya Wang #size-cells = <0>; 54048489980SSeiya Wang status = "disabled"; 54148489980SSeiya Wang }; 54248489980SSeiya Wang 54348489980SSeiya Wang i2c0: i2c0@11f00000 { 54448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 54548489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 54648489980SSeiya Wang <0 0x10217080 0 0x80>; 54748489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 54848489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 54948489980SSeiya Wang clock-names = "main", "dma"; 55048489980SSeiya Wang clock-div = <1>; 55148489980SSeiya Wang #address-cells = <1>; 55248489980SSeiya Wang #size-cells = <0>; 55348489980SSeiya Wang status = "disabled"; 55448489980SSeiya Wang }; 55548489980SSeiya Wang 55648489980SSeiya Wang i2c6: i2c6@11f01000 { 55748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 55848489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 55948489980SSeiya Wang <0 0x10217580 0 0x80>; 56048489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 56148489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 56248489980SSeiya Wang clock-names = "main", "dma"; 56348489980SSeiya Wang clock-div = <1>; 56448489980SSeiya Wang #address-cells = <1>; 56548489980SSeiya Wang #size-cells = <0>; 56648489980SSeiya Wang status = "disabled"; 56748489980SSeiya Wang }; 56848489980SSeiya Wang }; 56948489980SSeiya Wang}; 570