148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 114a65b0f1SAllen-KH Cheng#include <dt-bindings/memory/mt8192-larb-port.h> 1248489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 13e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h> 14994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 15*7d355378SAllen-KH Cheng#include <dt-bindings/reset/mt8192-resets.h> 1648489980SSeiya Wang 1748489980SSeiya Wang/ { 1848489980SSeiya Wang compatible = "mediatek,mt8192"; 1948489980SSeiya Wang interrupt-parent = <&gic>; 2048489980SSeiya Wang #address-cells = <2>; 2148489980SSeiya Wang #size-cells = <2>; 2248489980SSeiya Wang 2348489980SSeiya Wang clk26m: oscillator0 { 2448489980SSeiya Wang compatible = "fixed-clock"; 2548489980SSeiya Wang #clock-cells = <0>; 2648489980SSeiya Wang clock-frequency = <26000000>; 2748489980SSeiya Wang clock-output-names = "clk26m"; 2848489980SSeiya Wang }; 2948489980SSeiya Wang 3048489980SSeiya Wang clk32k: oscillator1 { 3148489980SSeiya Wang compatible = "fixed-clock"; 3248489980SSeiya Wang #clock-cells = <0>; 3348489980SSeiya Wang clock-frequency = <32768>; 3448489980SSeiya Wang clock-output-names = "clk32k"; 3548489980SSeiya Wang }; 3648489980SSeiya Wang 3748489980SSeiya Wang cpus { 3848489980SSeiya Wang #address-cells = <1>; 3948489980SSeiya Wang #size-cells = <0>; 4048489980SSeiya Wang 4148489980SSeiya Wang cpu0: cpu@0 { 4248489980SSeiya Wang device_type = "cpu"; 4348489980SSeiya Wang compatible = "arm,cortex-a55"; 4448489980SSeiya Wang reg = <0x000>; 4548489980SSeiya Wang enable-method = "psci"; 4648489980SSeiya Wang clock-frequency = <1701000000>; 47399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 4848489980SSeiya Wang next-level-cache = <&l2_0>; 4948489980SSeiya Wang capacity-dmips-mhz = <530>; 5048489980SSeiya Wang }; 5148489980SSeiya Wang 5248489980SSeiya Wang cpu1: cpu@100 { 5348489980SSeiya Wang device_type = "cpu"; 5448489980SSeiya Wang compatible = "arm,cortex-a55"; 5548489980SSeiya Wang reg = <0x100>; 5648489980SSeiya Wang enable-method = "psci"; 5748489980SSeiya Wang clock-frequency = <1701000000>; 58399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 5948489980SSeiya Wang next-level-cache = <&l2_0>; 6048489980SSeiya Wang capacity-dmips-mhz = <530>; 6148489980SSeiya Wang }; 6248489980SSeiya Wang 6348489980SSeiya Wang cpu2: cpu@200 { 6448489980SSeiya Wang device_type = "cpu"; 6548489980SSeiya Wang compatible = "arm,cortex-a55"; 6648489980SSeiya Wang reg = <0x200>; 6748489980SSeiya Wang enable-method = "psci"; 6848489980SSeiya Wang clock-frequency = <1701000000>; 69399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 7048489980SSeiya Wang next-level-cache = <&l2_0>; 7148489980SSeiya Wang capacity-dmips-mhz = <530>; 7248489980SSeiya Wang }; 7348489980SSeiya Wang 7448489980SSeiya Wang cpu3: cpu@300 { 7548489980SSeiya Wang device_type = "cpu"; 7648489980SSeiya Wang compatible = "arm,cortex-a55"; 7748489980SSeiya Wang reg = <0x300>; 7848489980SSeiya Wang enable-method = "psci"; 7948489980SSeiya Wang clock-frequency = <1701000000>; 80399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 8148489980SSeiya Wang next-level-cache = <&l2_0>; 8248489980SSeiya Wang capacity-dmips-mhz = <530>; 8348489980SSeiya Wang }; 8448489980SSeiya Wang 8548489980SSeiya Wang cpu4: cpu@400 { 8648489980SSeiya Wang device_type = "cpu"; 8748489980SSeiya Wang compatible = "arm,cortex-a76"; 8848489980SSeiya Wang reg = <0x400>; 8948489980SSeiya Wang enable-method = "psci"; 9048489980SSeiya Wang clock-frequency = <2171000000>; 91399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 9248489980SSeiya Wang next-level-cache = <&l2_1>; 9348489980SSeiya Wang capacity-dmips-mhz = <1024>; 9448489980SSeiya Wang }; 9548489980SSeiya Wang 9648489980SSeiya Wang cpu5: cpu@500 { 9748489980SSeiya Wang device_type = "cpu"; 9848489980SSeiya Wang compatible = "arm,cortex-a76"; 9948489980SSeiya Wang reg = <0x500>; 10048489980SSeiya Wang enable-method = "psci"; 10148489980SSeiya Wang clock-frequency = <2171000000>; 102399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 10348489980SSeiya Wang next-level-cache = <&l2_1>; 10448489980SSeiya Wang capacity-dmips-mhz = <1024>; 10548489980SSeiya Wang }; 10648489980SSeiya Wang 10748489980SSeiya Wang cpu6: cpu@600 { 10848489980SSeiya Wang device_type = "cpu"; 10948489980SSeiya Wang compatible = "arm,cortex-a76"; 11048489980SSeiya Wang reg = <0x600>; 11148489980SSeiya Wang enable-method = "psci"; 11248489980SSeiya Wang clock-frequency = <2171000000>; 113399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 11448489980SSeiya Wang next-level-cache = <&l2_1>; 11548489980SSeiya Wang capacity-dmips-mhz = <1024>; 11648489980SSeiya Wang }; 11748489980SSeiya Wang 11848489980SSeiya Wang cpu7: cpu@700 { 11948489980SSeiya Wang device_type = "cpu"; 12048489980SSeiya Wang compatible = "arm,cortex-a76"; 12148489980SSeiya Wang reg = <0x700>; 12248489980SSeiya Wang enable-method = "psci"; 12348489980SSeiya Wang clock-frequency = <2171000000>; 124399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 12548489980SSeiya Wang next-level-cache = <&l2_1>; 12648489980SSeiya Wang capacity-dmips-mhz = <1024>; 12748489980SSeiya Wang }; 12848489980SSeiya Wang 12948489980SSeiya Wang cpu-map { 13048489980SSeiya Wang cluster0 { 13148489980SSeiya Wang core0 { 13248489980SSeiya Wang cpu = <&cpu0>; 13348489980SSeiya Wang }; 13448489980SSeiya Wang core1 { 13548489980SSeiya Wang cpu = <&cpu1>; 13648489980SSeiya Wang }; 13748489980SSeiya Wang core2 { 13848489980SSeiya Wang cpu = <&cpu2>; 13948489980SSeiya Wang }; 14048489980SSeiya Wang core3 { 14148489980SSeiya Wang cpu = <&cpu3>; 14248489980SSeiya Wang }; 14348489980SSeiya Wang }; 14448489980SSeiya Wang 14548489980SSeiya Wang cluster1 { 14648489980SSeiya Wang core0 { 14748489980SSeiya Wang cpu = <&cpu4>; 14848489980SSeiya Wang }; 14948489980SSeiya Wang core1 { 15048489980SSeiya Wang cpu = <&cpu5>; 15148489980SSeiya Wang }; 15248489980SSeiya Wang core2 { 15348489980SSeiya Wang cpu = <&cpu6>; 15448489980SSeiya Wang }; 15548489980SSeiya Wang core3 { 15648489980SSeiya Wang cpu = <&cpu7>; 15748489980SSeiya Wang }; 15848489980SSeiya Wang }; 15948489980SSeiya Wang }; 16048489980SSeiya Wang 16148489980SSeiya Wang l2_0: l2-cache0 { 16248489980SSeiya Wang compatible = "cache"; 16348489980SSeiya Wang next-level-cache = <&l3_0>; 16448489980SSeiya Wang }; 16548489980SSeiya Wang 16648489980SSeiya Wang l2_1: l2-cache1 { 16748489980SSeiya Wang compatible = "cache"; 16848489980SSeiya Wang next-level-cache = <&l3_0>; 16948489980SSeiya Wang }; 17048489980SSeiya Wang 17148489980SSeiya Wang l3_0: l3-cache { 17248489980SSeiya Wang compatible = "cache"; 17348489980SSeiya Wang }; 1749260918dSJames Liao 1759260918dSJames Liao idle-states { 1762e599740SNícolas F. R. A. Prado entry-method = "psci"; 177399e23adSNícolas F. R. A. Prado cpu_sleep_l: cpu-sleep-l { 1789260918dSJames Liao compatible = "arm,idle-state"; 1799260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1809260918dSJames Liao local-timer-stop; 1819260918dSJames Liao entry-latency-us = <55>; 1829260918dSJames Liao exit-latency-us = <140>; 1839260918dSJames Liao min-residency-us = <780>; 1849260918dSJames Liao }; 185399e23adSNícolas F. R. A. Prado cpu_sleep_b: cpu-sleep-b { 1869260918dSJames Liao compatible = "arm,idle-state"; 1879260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1889260918dSJames Liao local-timer-stop; 1899260918dSJames Liao entry-latency-us = <35>; 1909260918dSJames Liao exit-latency-us = <145>; 1919260918dSJames Liao min-residency-us = <720>; 1929260918dSJames Liao }; 193399e23adSNícolas F. R. A. Prado cluster_sleep_l: cluster-sleep-l { 1949260918dSJames Liao compatible = "arm,idle-state"; 1959260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 1969260918dSJames Liao local-timer-stop; 1979260918dSJames Liao entry-latency-us = <60>; 1989260918dSJames Liao exit-latency-us = <155>; 1999260918dSJames Liao min-residency-us = <860>; 2009260918dSJames Liao }; 201399e23adSNícolas F. R. A. Prado cluster_sleep_b: cluster-sleep-b { 2029260918dSJames Liao compatible = "arm,idle-state"; 2039260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2049260918dSJames Liao local-timer-stop; 2059260918dSJames Liao entry-latency-us = <40>; 2069260918dSJames Liao exit-latency-us = <155>; 2079260918dSJames Liao min-residency-us = <780>; 2089260918dSJames Liao }; 2099260918dSJames Liao }; 21048489980SSeiya Wang }; 21148489980SSeiya Wang 21248489980SSeiya Wang pmu-a55 { 21348489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 21448489980SSeiya Wang interrupt-parent = <&gic>; 21548489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 21648489980SSeiya Wang }; 21748489980SSeiya Wang 21848489980SSeiya Wang pmu-a76 { 21948489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 22048489980SSeiya Wang interrupt-parent = <&gic>; 22148489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 22248489980SSeiya Wang }; 22348489980SSeiya Wang 22448489980SSeiya Wang psci { 22548489980SSeiya Wang compatible = "arm,psci-1.0"; 22648489980SSeiya Wang method = "smc"; 22748489980SSeiya Wang }; 22848489980SSeiya Wang 22948489980SSeiya Wang timer: timer { 23048489980SSeiya Wang compatible = "arm,armv8-timer"; 23148489980SSeiya Wang interrupt-parent = <&gic>; 23248489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 23348489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 23448489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 23548489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 23648489980SSeiya Wang clock-frequency = <13000000>; 23748489980SSeiya Wang }; 23848489980SSeiya Wang 23948489980SSeiya Wang soc { 24048489980SSeiya Wang #address-cells = <2>; 24148489980SSeiya Wang #size-cells = <2>; 24248489980SSeiya Wang compatible = "simple-bus"; 24348489980SSeiya Wang ranges; 24448489980SSeiya Wang 24548489980SSeiya Wang gic: interrupt-controller@c000000 { 24648489980SSeiya Wang compatible = "arm,gic-v3"; 24748489980SSeiya Wang #interrupt-cells = <4>; 24848489980SSeiya Wang #redistributor-regions = <1>; 24948489980SSeiya Wang interrupt-parent = <&gic>; 25048489980SSeiya Wang interrupt-controller; 25148489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 25248489980SSeiya Wang <0 0x0c040000 0 0x200000>; 25348489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 25448489980SSeiya Wang 25548489980SSeiya Wang ppi-partitions { 25648489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 25748489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 25848489980SSeiya Wang }; 25948489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 26048489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 26148489980SSeiya Wang }; 26248489980SSeiya Wang }; 26348489980SSeiya Wang }; 26448489980SSeiya Wang 2655d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 2665d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 2675d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 2685d2b897bSChun-Jie Chen #clock-cells = <1>; 2695d2b897bSChun-Jie Chen }; 2705d2b897bSChun-Jie Chen 2715d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 2725d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 2735d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 2745d2b897bSChun-Jie Chen #clock-cells = <1>; 275a30cc07fSRex-BC Chen #reset-cells = <1>; 2765d2b897bSChun-Jie Chen }; 2775d2b897bSChun-Jie Chen 2785d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 2795d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 2805d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 2815d2b897bSChun-Jie Chen #clock-cells = <1>; 2825d2b897bSChun-Jie Chen }; 2835d2b897bSChun-Jie Chen 28448489980SSeiya Wang pio: pinctrl@10005000 { 28548489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 28648489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 28748489980SSeiya Wang <0 0x11c20000 0 0x1000>, 28848489980SSeiya Wang <0 0x11d10000 0 0x1000>, 28948489980SSeiya Wang <0 0x11d30000 0 0x1000>, 29048489980SSeiya Wang <0 0x11d40000 0 0x1000>, 29148489980SSeiya Wang <0 0x11e20000 0 0x1000>, 29248489980SSeiya Wang <0 0x11e70000 0 0x1000>, 29348489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 29448489980SSeiya Wang <0 0x11f20000 0 0x1000>, 29548489980SSeiya Wang <0 0x11f30000 0 0x1000>, 29648489980SSeiya Wang <0 0x1000b000 0 0x1000>; 29748489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 29848489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 29948489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 30048489980SSeiya Wang "iocfg_tl", "eint"; 30148489980SSeiya Wang gpio-controller; 30248489980SSeiya Wang #gpio-cells = <2>; 30348489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 30448489980SSeiya Wang interrupt-controller; 30548489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 30648489980SSeiya Wang #interrupt-cells = <2>; 30748489980SSeiya Wang }; 30848489980SSeiya Wang 309994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 310d3dfd468STinghan Shen compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 311994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 312994a71a3SChun-Jie Chen 313994a71a3SChun-Jie Chen /* System Power Manager */ 314994a71a3SChun-Jie Chen spm: power-controller { 315994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 316994a71a3SChun-Jie Chen #address-cells = <1>; 317994a71a3SChun-Jie Chen #size-cells = <0>; 318994a71a3SChun-Jie Chen #power-domain-cells = <1>; 319994a71a3SChun-Jie Chen 320994a71a3SChun-Jie Chen /* power domain of the SoC */ 321994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 322994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 323994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 324994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 325994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 326994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 327994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 328994a71a3SChun-Jie Chen #power-domain-cells = <0>; 329994a71a3SChun-Jie Chen }; 330994a71a3SChun-Jie Chen 331994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 332994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 333994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 334994a71a3SChun-Jie Chen clock-names = "conn"; 335994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 336994a71a3SChun-Jie Chen #power-domain-cells = <0>; 337994a71a3SChun-Jie Chen }; 338994a71a3SChun-Jie Chen 339994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG0 { 340994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 341994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 342994a71a3SChun-Jie Chen clock-names = "mfg"; 343994a71a3SChun-Jie Chen #address-cells = <1>; 344994a71a3SChun-Jie Chen #size-cells = <0>; 345994a71a3SChun-Jie Chen #power-domain-cells = <1>; 346994a71a3SChun-Jie Chen 347994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG1 { 348994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 349994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 350994a71a3SChun-Jie Chen #address-cells = <1>; 351994a71a3SChun-Jie Chen #size-cells = <0>; 352994a71a3SChun-Jie Chen #power-domain-cells = <1>; 353994a71a3SChun-Jie Chen 354994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 355994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 356994a71a3SChun-Jie Chen #power-domain-cells = <0>; 357994a71a3SChun-Jie Chen }; 358994a71a3SChun-Jie Chen 359994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 360994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 361994a71a3SChun-Jie Chen #power-domain-cells = <0>; 362994a71a3SChun-Jie Chen }; 363994a71a3SChun-Jie Chen 364994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 365994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 366994a71a3SChun-Jie Chen #power-domain-cells = <0>; 367994a71a3SChun-Jie Chen }; 368994a71a3SChun-Jie Chen 369994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 370994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 371994a71a3SChun-Jie Chen #power-domain-cells = <0>; 372994a71a3SChun-Jie Chen }; 373994a71a3SChun-Jie Chen 374994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 375994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 376994a71a3SChun-Jie Chen #power-domain-cells = <0>; 377994a71a3SChun-Jie Chen }; 378994a71a3SChun-Jie Chen }; 379994a71a3SChun-Jie Chen }; 380994a71a3SChun-Jie Chen 381994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 382994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 383994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 384994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 385994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 386994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 387994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 388994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 389994a71a3SChun-Jie Chen "disp-3"; 390994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 391994a71a3SChun-Jie Chen #address-cells = <1>; 392994a71a3SChun-Jie Chen #size-cells = <0>; 393994a71a3SChun-Jie Chen #power-domain-cells = <1>; 394994a71a3SChun-Jie Chen 395994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 396994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 397994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 398994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 399994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 400994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 401994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 402994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 403994a71a3SChun-Jie Chen "ipe-3"; 404994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 405994a71a3SChun-Jie Chen #power-domain-cells = <0>; 406994a71a3SChun-Jie Chen }; 407994a71a3SChun-Jie Chen 408994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 409994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 410994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 411994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 412994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 413994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 414994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 415994a71a3SChun-Jie Chen #power-domain-cells = <0>; 416994a71a3SChun-Jie Chen }; 417994a71a3SChun-Jie Chen 418994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 419994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 420994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 421994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 422994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 423994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 424994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 425994a71a3SChun-Jie Chen #power-domain-cells = <0>; 426994a71a3SChun-Jie Chen }; 427994a71a3SChun-Jie Chen 428994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 429994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 430994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 431994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 432994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 433994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 434994a71a3SChun-Jie Chen #power-domain-cells = <0>; 435994a71a3SChun-Jie Chen }; 436994a71a3SChun-Jie Chen 437994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 438994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 439994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 440994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 441994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 442994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 443994a71a3SChun-Jie Chen #power-domain-cells = <0>; 444994a71a3SChun-Jie Chen }; 445994a71a3SChun-Jie Chen 446994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 447994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 448994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 449994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 450994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 451994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 452994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 453994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 454994a71a3SChun-Jie Chen #address-cells = <1>; 455994a71a3SChun-Jie Chen #size-cells = <0>; 456994a71a3SChun-Jie Chen #power-domain-cells = <1>; 457994a71a3SChun-Jie Chen 458994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 459994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 460994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 461994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 462994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 463994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 464994a71a3SChun-Jie Chen "vdec2-2"; 465994a71a3SChun-Jie Chen #power-domain-cells = <0>; 466994a71a3SChun-Jie Chen }; 467994a71a3SChun-Jie Chen }; 468994a71a3SChun-Jie Chen 469994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 470994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 471994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 472994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 473994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 474994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 475994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 476994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 477994a71a3SChun-Jie Chen "cam-3"; 478994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 479994a71a3SChun-Jie Chen #address-cells = <1>; 480994a71a3SChun-Jie Chen #size-cells = <0>; 481994a71a3SChun-Jie Chen #power-domain-cells = <1>; 482994a71a3SChun-Jie Chen 483994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 484994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 485994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 486994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 487994a71a3SChun-Jie Chen #power-domain-cells = <0>; 488994a71a3SChun-Jie Chen }; 489994a71a3SChun-Jie Chen 490994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 491994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 492994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 493994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 494994a71a3SChun-Jie Chen #power-domain-cells = <0>; 495994a71a3SChun-Jie Chen }; 496994a71a3SChun-Jie Chen 497994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 498994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 499994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 500994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 501994a71a3SChun-Jie Chen #power-domain-cells = <0>; 502994a71a3SChun-Jie Chen }; 503994a71a3SChun-Jie Chen }; 504994a71a3SChun-Jie Chen }; 505994a71a3SChun-Jie Chen }; 506994a71a3SChun-Jie Chen }; 507994a71a3SChun-Jie Chen 508d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 509d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 510d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 511d1986fbdSAllen-KH Cheng #reset-cells = <1>; 512d1986fbdSAllen-KH Cheng }; 513d1986fbdSAllen-KH Cheng 5145d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 5155d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 5165d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 5175d2b897bSChun-Jie Chen #clock-cells = <1>; 5185d2b897bSChun-Jie Chen }; 5195d2b897bSChun-Jie Chen 52048489980SSeiya Wang systimer: timer@10017000 { 52148489980SSeiya Wang compatible = "mediatek,mt8192-timer", 52248489980SSeiya Wang "mediatek,mt6765-timer"; 52348489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 52448489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 525dde3c175SAllen-KH Cheng clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 52648489980SSeiya Wang clock-names = "clk13m"; 52748489980SSeiya Wang }; 52848489980SSeiya Wang 529261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 530261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 531261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 532261691b4SAllen-KH Cheng reg-names = "pwrap"; 533261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 534261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 535261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 536261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 537261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 538261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 539261691b4SAllen-KH Cheng }; 540261691b4SAllen-KH Cheng 541a8bbcf70SAllen-KH Cheng spmi: spmi@10027000 { 542a8bbcf70SAllen-KH Cheng compatible = "mediatek,mt6873-spmi"; 543a8bbcf70SAllen-KH Cheng reg = <0 0x10027000 0 0x000e00>, 544a8bbcf70SAllen-KH Cheng <0 0x10029000 0 0x000100>; 545a8bbcf70SAllen-KH Cheng reg-names = "pmif", "spmimst"; 546a8bbcf70SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 547a8bbcf70SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>, 548a8bbcf70SAllen-KH Cheng <&topckgen CLK_TOP_SPMI_MST_SEL>; 549a8bbcf70SAllen-KH Cheng clock-names = "pmif_sys_ck", 550a8bbcf70SAllen-KH Cheng "pmif_tmr_ck", 551a8bbcf70SAllen-KH Cheng "spmimst_clk_mux"; 552a8bbcf70SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 553a8bbcf70SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 554a8bbcf70SAllen-KH Cheng }; 555a8bbcf70SAllen-KH Cheng 5565d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 5575d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 5585d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 5595d2b897bSChun-Jie Chen #clock-cells = <1>; 5605d2b897bSChun-Jie Chen }; 5615d2b897bSChun-Jie Chen 56248489980SSeiya Wang uart0: serial@11002000 { 56348489980SSeiya Wang compatible = "mediatek,mt8192-uart", 56448489980SSeiya Wang "mediatek,mt6577-uart"; 56548489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 56648489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 56773ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 56848489980SSeiya Wang clock-names = "baud", "bus"; 56948489980SSeiya Wang status = "disabled"; 57048489980SSeiya Wang }; 57148489980SSeiya Wang 57248489980SSeiya Wang uart1: serial@11003000 { 57348489980SSeiya Wang compatible = "mediatek,mt8192-uart", 57448489980SSeiya Wang "mediatek,mt6577-uart"; 57548489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 57648489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 57773ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 57848489980SSeiya Wang clock-names = "baud", "bus"; 57948489980SSeiya Wang status = "disabled"; 58048489980SSeiya Wang }; 58148489980SSeiya Wang 5825d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 5835d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 5845d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 5855d2b897bSChun-Jie Chen #clock-cells = <1>; 5865d2b897bSChun-Jie Chen }; 5875d2b897bSChun-Jie Chen 58848489980SSeiya Wang spi0: spi@1100a000 { 58948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 59048489980SSeiya Wang "mediatek,mt6765-spi"; 59148489980SSeiya Wang #address-cells = <1>; 59248489980SSeiya Wang #size-cells = <0>; 59348489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 59448489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 5957f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5967f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5977f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 59848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 59948489980SSeiya Wang status = "disabled"; 60048489980SSeiya Wang }; 60148489980SSeiya Wang 60218222e05SAllen-KH Cheng pwm0: pwm@1100e000 { 60318222e05SAllen-KH Cheng compatible = "mediatek,mt8183-disp-pwm"; 60418222e05SAllen-KH Cheng reg = <0 0x1100e000 0 0x1000>; 60518222e05SAllen-KH Cheng interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 60618222e05SAllen-KH Cheng #pwm-cells = <2>; 60718222e05SAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 60818222e05SAllen-KH Cheng <&infracfg CLK_INFRA_DISP_PWM>; 60918222e05SAllen-KH Cheng clock-names = "main", "mm"; 61018222e05SAllen-KH Cheng status = "disabled"; 61118222e05SAllen-KH Cheng }; 61218222e05SAllen-KH Cheng 61348489980SSeiya Wang spi1: spi@11010000 { 61448489980SSeiya Wang compatible = "mediatek,mt8192-spi", 61548489980SSeiya Wang "mediatek,mt6765-spi"; 61648489980SSeiya Wang #address-cells = <1>; 61748489980SSeiya Wang #size-cells = <0>; 61848489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 61948489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 6207f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6217f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6227f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 62348489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 62448489980SSeiya Wang status = "disabled"; 62548489980SSeiya Wang }; 62648489980SSeiya Wang 62748489980SSeiya Wang spi2: spi@11012000 { 62848489980SSeiya Wang compatible = "mediatek,mt8192-spi", 62948489980SSeiya Wang "mediatek,mt6765-spi"; 63048489980SSeiya Wang #address-cells = <1>; 63148489980SSeiya Wang #size-cells = <0>; 63248489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 63348489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 6347f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6357f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6367f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 63748489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 63848489980SSeiya Wang status = "disabled"; 63948489980SSeiya Wang }; 64048489980SSeiya Wang 64148489980SSeiya Wang spi3: spi@11013000 { 64248489980SSeiya Wang compatible = "mediatek,mt8192-spi", 64348489980SSeiya Wang "mediatek,mt6765-spi"; 64448489980SSeiya Wang #address-cells = <1>; 64548489980SSeiya Wang #size-cells = <0>; 64648489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 64748489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 6487f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6497f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6507f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 65148489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 65248489980SSeiya Wang status = "disabled"; 65348489980SSeiya Wang }; 65448489980SSeiya Wang 65548489980SSeiya Wang spi4: spi@11018000 { 65648489980SSeiya Wang compatible = "mediatek,mt8192-spi", 65748489980SSeiya Wang "mediatek,mt6765-spi"; 65848489980SSeiya Wang #address-cells = <1>; 65948489980SSeiya Wang #size-cells = <0>; 66048489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 66148489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 6627f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6637f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6647f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 66548489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 66648489980SSeiya Wang status = "disabled"; 66748489980SSeiya Wang }; 66848489980SSeiya Wang 66948489980SSeiya Wang spi5: spi@11019000 { 67048489980SSeiya Wang compatible = "mediatek,mt8192-spi", 67148489980SSeiya Wang "mediatek,mt6765-spi"; 67248489980SSeiya Wang #address-cells = <1>; 67348489980SSeiya Wang #size-cells = <0>; 67448489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 67548489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 6767f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6777f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6787f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 67948489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 68048489980SSeiya Wang status = "disabled"; 68148489980SSeiya Wang }; 68248489980SSeiya Wang 68348489980SSeiya Wang spi6: spi@1101d000 { 68448489980SSeiya Wang compatible = "mediatek,mt8192-spi", 68548489980SSeiya Wang "mediatek,mt6765-spi"; 68648489980SSeiya Wang #address-cells = <1>; 68748489980SSeiya Wang #size-cells = <0>; 68848489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 68948489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 6907f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6917f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6927f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 69348489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 69448489980SSeiya Wang status = "disabled"; 69548489980SSeiya Wang }; 69648489980SSeiya Wang 69748489980SSeiya Wang spi7: spi@1101e000 { 69848489980SSeiya Wang compatible = "mediatek,mt8192-spi", 69948489980SSeiya Wang "mediatek,mt6765-spi"; 70048489980SSeiya Wang #address-cells = <1>; 70148489980SSeiya Wang #size-cells = <0>; 70248489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 70348489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 7047f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7057f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7067f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 70748489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 70848489980SSeiya Wang status = "disabled"; 70948489980SSeiya Wang }; 71048489980SSeiya Wang 711c63556ecSAllen-KH Cheng scp: scp@10500000 { 712c63556ecSAllen-KH Cheng compatible = "mediatek,mt8192-scp"; 713c63556ecSAllen-KH Cheng reg = <0 0x10500000 0 0x100000>, 714c7510476SNícolas F. R. A. Prado <0 0x10720000 0 0xe0000>, 715c7510476SNícolas F. R. A. Prado <0 0x10700000 0 0x8000>; 716c7510476SNícolas F. R. A. Prado reg-names = "sram", "cfg", "l1tcm"; 717c63556ecSAllen-KH Cheng interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 718c63556ecSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SCPSYS>; 719c63556ecSAllen-KH Cheng clock-names = "main"; 720c63556ecSAllen-KH Cheng status = "disabled"; 721c63556ecSAllen-KH Cheng }; 722c63556ecSAllen-KH Cheng 723e5aac225SAllen-KH Cheng xhci: usb@11200000 { 724e5aac225SAllen-KH Cheng compatible = "mediatek,mt8192-xhci", 725e5aac225SAllen-KH Cheng "mediatek,mtk-xhci"; 726e5aac225SAllen-KH Cheng reg = <0 0x11200000 0 0x1000>, 727e5aac225SAllen-KH Cheng <0 0x11203e00 0 0x0100>; 728e5aac225SAllen-KH Cheng reg-names = "mac", "ippc"; 729e5aac225SAllen-KH Cheng interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 730e5aac225SAllen-KH Cheng interrupt-names = "host"; 731e5aac225SAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>, 732e5aac225SAllen-KH Cheng <&u3port0 PHY_TYPE_USB3>; 733e5aac225SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 734e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 735e5aac225SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 736e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 737e5aac225SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SSUSB>, 738e5aac225SAllen-KH Cheng <&infracfg CLK_INFRA_SSUSB_XHCI>, 739e5aac225SAllen-KH Cheng <&apmixedsys CLK_APMIXED_USBPLL>; 740e5aac225SAllen-KH Cheng clock-names = "sys_ck", "xhci_ck", "ref_ck"; 741e5aac225SAllen-KH Cheng wakeup-source; 742e5aac225SAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 102>; 743e5aac225SAllen-KH Cheng status = "disabled"; 744e5aac225SAllen-KH Cheng }; 745e5aac225SAllen-KH Cheng 7461afd9b62SAllen-KH Cheng audsys: syscon@11210000 { 7471afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audsys", "syscon"; 7481afd9b62SAllen-KH Cheng reg = <0 0x11210000 0 0x2000>; 7491afd9b62SAllen-KH Cheng #clock-cells = <1>; 7501afd9b62SAllen-KH Cheng 7511afd9b62SAllen-KH Cheng afe: mt8192-afe-pcm { 7521afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audio"; 7531afd9b62SAllen-KH Cheng interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 7541afd9b62SAllen-KH Cheng resets = <&watchdog 17>; 7551afd9b62SAllen-KH Cheng reset-names = "audiosys"; 7561afd9b62SAllen-KH Cheng mediatek,apmixedsys = <&apmixedsys>; 7571afd9b62SAllen-KH Cheng mediatek,infracfg = <&infracfg>; 7581afd9b62SAllen-KH Cheng mediatek,topckgen = <&topckgen>; 7591afd9b62SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 7601afd9b62SAllen-KH Cheng clocks = <&audsys CLK_AUD_AFE>, 7611afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC>, 7621afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_PREDIS>, 7631afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC>, 7641afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC>, 7651afd9b62SAllen-KH Cheng <&audsys CLK_AUD_22M>, 7661afd9b62SAllen-KH Cheng <&audsys CLK_AUD_24M>, 7671afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL_TUNER>, 7681afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL2_TUNER>, 7691afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TDM>, 7701afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TML>, 7711afd9b62SAllen-KH Cheng <&audsys CLK_AUD_NLE>, 7721afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_HIRES>, 7731afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES>, 7741afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES_TML>, 7751afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 7761afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC>, 7771afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_PREDIS>, 7781afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_TML>, 7791afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_HIRES>, 7801afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO>, 7811afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO_26M_B>, 7821afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_SEL>, 7831afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 7841afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D4_D4>, 7851afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_1_SEL>, 7861afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1>, 7871afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_2_SEL>, 7881afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2>, 7891afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 7901afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1_D4>, 7911afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 7921afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2_D4>, 7931afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 7941afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 7951afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 7961afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 7971afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 7981afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 7991afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 8001afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 8011afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 8021afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 8031afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV0>, 8041afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV1>, 8051afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV2>, 8061afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV3>, 8071afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV4>, 8081afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIVB>, 8091afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV5>, 8101afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV6>, 8111afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV7>, 8121afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV8>, 8131afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV9>, 8141afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_H_SEL>, 8151afd9b62SAllen-KH Cheng <&clk26m>; 8161afd9b62SAllen-KH Cheng clock-names = "aud_afe_clk", 8171afd9b62SAllen-KH Cheng "aud_dac_clk", 8181afd9b62SAllen-KH Cheng "aud_dac_predis_clk", 8191afd9b62SAllen-KH Cheng "aud_adc_clk", 8201afd9b62SAllen-KH Cheng "aud_adda6_adc_clk", 8211afd9b62SAllen-KH Cheng "aud_apll22m_clk", 8221afd9b62SAllen-KH Cheng "aud_apll24m_clk", 8231afd9b62SAllen-KH Cheng "aud_apll1_tuner_clk", 8241afd9b62SAllen-KH Cheng "aud_apll2_tuner_clk", 8251afd9b62SAllen-KH Cheng "aud_tdm_clk", 8261afd9b62SAllen-KH Cheng "aud_tml_clk", 8271afd9b62SAllen-KH Cheng "aud_nle", 8281afd9b62SAllen-KH Cheng "aud_dac_hires_clk", 8291afd9b62SAllen-KH Cheng "aud_adc_hires_clk", 8301afd9b62SAllen-KH Cheng "aud_adc_hires_tml", 8311afd9b62SAllen-KH Cheng "aud_adda6_adc_hires_clk", 8321afd9b62SAllen-KH Cheng "aud_3rd_dac_clk", 8331afd9b62SAllen-KH Cheng "aud_3rd_dac_predis_clk", 8341afd9b62SAllen-KH Cheng "aud_3rd_dac_tml", 8351afd9b62SAllen-KH Cheng "aud_3rd_dac_hires_clk", 8361afd9b62SAllen-KH Cheng "aud_infra_clk", 8371afd9b62SAllen-KH Cheng "aud_infra_26m_clk", 8381afd9b62SAllen-KH Cheng "top_mux_audio", 8391afd9b62SAllen-KH Cheng "top_mux_audio_int", 8401afd9b62SAllen-KH Cheng "top_mainpll_d4_d4", 8411afd9b62SAllen-KH Cheng "top_mux_aud_1", 8421afd9b62SAllen-KH Cheng "top_apll1_ck", 8431afd9b62SAllen-KH Cheng "top_mux_aud_2", 8441afd9b62SAllen-KH Cheng "top_apll2_ck", 8451afd9b62SAllen-KH Cheng "top_mux_aud_eng1", 8461afd9b62SAllen-KH Cheng "top_apll1_d4", 8471afd9b62SAllen-KH Cheng "top_mux_aud_eng2", 8481afd9b62SAllen-KH Cheng "top_apll2_d4", 8491afd9b62SAllen-KH Cheng "top_i2s0_m_sel", 8501afd9b62SAllen-KH Cheng "top_i2s1_m_sel", 8511afd9b62SAllen-KH Cheng "top_i2s2_m_sel", 8521afd9b62SAllen-KH Cheng "top_i2s3_m_sel", 8531afd9b62SAllen-KH Cheng "top_i2s4_m_sel", 8541afd9b62SAllen-KH Cheng "top_i2s5_m_sel", 8551afd9b62SAllen-KH Cheng "top_i2s6_m_sel", 8561afd9b62SAllen-KH Cheng "top_i2s7_m_sel", 8571afd9b62SAllen-KH Cheng "top_i2s8_m_sel", 8581afd9b62SAllen-KH Cheng "top_i2s9_m_sel", 8591afd9b62SAllen-KH Cheng "top_apll12_div0", 8601afd9b62SAllen-KH Cheng "top_apll12_div1", 8611afd9b62SAllen-KH Cheng "top_apll12_div2", 8621afd9b62SAllen-KH Cheng "top_apll12_div3", 8631afd9b62SAllen-KH Cheng "top_apll12_div4", 8641afd9b62SAllen-KH Cheng "top_apll12_divb", 8651afd9b62SAllen-KH Cheng "top_apll12_div5", 8661afd9b62SAllen-KH Cheng "top_apll12_div6", 8671afd9b62SAllen-KH Cheng "top_apll12_div7", 8681afd9b62SAllen-KH Cheng "top_apll12_div8", 8691afd9b62SAllen-KH Cheng "top_apll12_div9", 8701afd9b62SAllen-KH Cheng "top_mux_audio_h", 8711afd9b62SAllen-KH Cheng "top_clk26m_clk"; 8721afd9b62SAllen-KH Cheng }; 8731afd9b62SAllen-KH Cheng }; 8741afd9b62SAllen-KH Cheng 875e530d080SAllen-KH Cheng pcie: pcie@11230000 { 876e530d080SAllen-KH Cheng compatible = "mediatek,mt8192-pcie"; 877e530d080SAllen-KH Cheng device_type = "pci"; 878e530d080SAllen-KH Cheng reg = <0 0x11230000 0 0x2000>; 879e530d080SAllen-KH Cheng reg-names = "pcie-mac"; 880e530d080SAllen-KH Cheng #address-cells = <3>; 881e530d080SAllen-KH Cheng #size-cells = <2>; 882e530d080SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 883e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_26M>, 884e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_96M>, 885e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_32K>, 886e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_PERI_26M>, 887e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 888e530d080SAllen-KH Cheng clock-names = "pl_250m", "tl_26m", "tl_96m", 889e530d080SAllen-KH Cheng "tl_32k", "peri_26m", "top_133m"; 890e530d080SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 891e530d080SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 892e530d080SAllen-KH Cheng interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 893e530d080SAllen-KH Cheng bus-range = <0x00 0xff>; 894e530d080SAllen-KH Cheng ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 895e530d080SAllen-KH Cheng <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 896e530d080SAllen-KH Cheng #interrupt-cells = <1>; 897e530d080SAllen-KH Cheng interrupt-map-mask = <0 0 0 7>; 898e530d080SAllen-KH Cheng interrupt-map = <0 0 0 1 &pcie_intc0 0>, 899e530d080SAllen-KH Cheng <0 0 0 2 &pcie_intc0 1>, 900e530d080SAllen-KH Cheng <0 0 0 3 &pcie_intc0 2>, 901e530d080SAllen-KH Cheng <0 0 0 4 &pcie_intc0 3>; 902e530d080SAllen-KH Cheng 903e530d080SAllen-KH Cheng pcie_intc0: interrupt-controller { 904e530d080SAllen-KH Cheng interrupt-controller; 905e530d080SAllen-KH Cheng #address-cells = <0>; 906e530d080SAllen-KH Cheng #interrupt-cells = <1>; 907e530d080SAllen-KH Cheng }; 908e530d080SAllen-KH Cheng }; 909e530d080SAllen-KH Cheng 910d0a197a0Sbayi cheng nor_flash: spi@11234000 { 911d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 912d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 913d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 914aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 915aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 916aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 917d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 918aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 919aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 920d0a197a0Sbayi cheng #address-cells = <1>; 921d0a197a0Sbayi cheng #size-cells = <0>; 92227f0eb16SAllen-KH Cheng status = "disabled"; 923d0a197a0Sbayi cheng }; 924d0a197a0Sbayi cheng 9254d50a433SAllen-KH Cheng efuse: efuse@11c10000 { 926fda0541cSChunfeng Yun compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 9274d50a433SAllen-KH Cheng reg = <0 0x11c10000 0 0x1000>; 9284d50a433SAllen-KH Cheng #address-cells = <1>; 9294d50a433SAllen-KH Cheng #size-cells = <1>; 9304d50a433SAllen-KH Cheng 9314d50a433SAllen-KH Cheng lvts_e_data1: data1@1c0 { 9324d50a433SAllen-KH Cheng reg = <0x1c0 0x58>; 9334d50a433SAllen-KH Cheng }; 9344d50a433SAllen-KH Cheng 9354d50a433SAllen-KH Cheng svs_calibration: calib@580 { 9364d50a433SAllen-KH Cheng reg = <0x580 0x68>; 9374d50a433SAllen-KH Cheng }; 9384d50a433SAllen-KH Cheng }; 9394d50a433SAllen-KH Cheng 9407f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 94148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 94248489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 94348489980SSeiya Wang <0 0x10217300 0 0x80>; 94448489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 94522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 94622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 94748489980SSeiya Wang clock-names = "main", "dma"; 94848489980SSeiya Wang clock-div = <1>; 94948489980SSeiya Wang #address-cells = <1>; 95048489980SSeiya Wang #size-cells = <0>; 95148489980SSeiya Wang status = "disabled"; 95248489980SSeiya Wang }; 95348489980SSeiya Wang 9545d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 9555d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 9565d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 9575d2b897bSChun-Jie Chen #clock-cells = <1>; 9585d2b897bSChun-Jie Chen }; 9595d2b897bSChun-Jie Chen 9607f1a9f47SFabien Parent i2c7: i2c@11d00000 { 96148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 96248489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 96348489980SSeiya Wang <0 0x10217600 0 0x180>; 96448489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 96522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 96622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 96748489980SSeiya Wang clock-names = "main", "dma"; 96848489980SSeiya Wang clock-div = <1>; 96948489980SSeiya Wang #address-cells = <1>; 97048489980SSeiya Wang #size-cells = <0>; 97148489980SSeiya Wang status = "disabled"; 97248489980SSeiya Wang }; 97348489980SSeiya Wang 9747f1a9f47SFabien Parent i2c8: i2c@11d01000 { 97548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 97648489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 97748489980SSeiya Wang <0 0x10217780 0 0x180>; 97848489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 97922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 98022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 98148489980SSeiya Wang clock-names = "main", "dma"; 98248489980SSeiya Wang clock-div = <1>; 98348489980SSeiya Wang #address-cells = <1>; 98448489980SSeiya Wang #size-cells = <0>; 98548489980SSeiya Wang status = "disabled"; 98648489980SSeiya Wang }; 98748489980SSeiya Wang 9887f1a9f47SFabien Parent i2c9: i2c@11d02000 { 98948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 99048489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 99148489980SSeiya Wang <0 0x10217900 0 0x180>; 99248489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 99322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 99422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 99548489980SSeiya Wang clock-names = "main", "dma"; 99648489980SSeiya Wang clock-div = <1>; 99748489980SSeiya Wang #address-cells = <1>; 99848489980SSeiya Wang #size-cells = <0>; 99948489980SSeiya Wang status = "disabled"; 100048489980SSeiya Wang }; 100148489980SSeiya Wang 10025d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 10035d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 10045d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 10055d2b897bSChun-Jie Chen #clock-cells = <1>; 10065d2b897bSChun-Jie Chen }; 10075d2b897bSChun-Jie Chen 10087f1a9f47SFabien Parent i2c1: i2c@11d20000 { 100948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 101048489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 101148489980SSeiya Wang <0 0x10217100 0 0x80>; 101248489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 101322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 101422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 101548489980SSeiya Wang clock-names = "main", "dma"; 101648489980SSeiya Wang clock-div = <1>; 101748489980SSeiya Wang #address-cells = <1>; 101848489980SSeiya Wang #size-cells = <0>; 101948489980SSeiya Wang status = "disabled"; 102048489980SSeiya Wang }; 102148489980SSeiya Wang 10227f1a9f47SFabien Parent i2c2: i2c@11d21000 { 102348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 102448489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 102548489980SSeiya Wang <0 0x10217180 0 0x180>; 102648489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 102722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 102822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 102948489980SSeiya Wang clock-names = "main", "dma"; 103048489980SSeiya Wang clock-div = <1>; 103148489980SSeiya Wang #address-cells = <1>; 103248489980SSeiya Wang #size-cells = <0>; 103348489980SSeiya Wang status = "disabled"; 103448489980SSeiya Wang }; 103548489980SSeiya Wang 10367f1a9f47SFabien Parent i2c4: i2c@11d22000 { 103748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 103848489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 103948489980SSeiya Wang <0 0x10217380 0 0x180>; 104048489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 104122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 104222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 104348489980SSeiya Wang clock-names = "main", "dma"; 104448489980SSeiya Wang clock-div = <1>; 104548489980SSeiya Wang #address-cells = <1>; 104648489980SSeiya Wang #size-cells = <0>; 104748489980SSeiya Wang status = "disabled"; 104848489980SSeiya Wang }; 104948489980SSeiya Wang 10505d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 10515d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 10525d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 10535d2b897bSChun-Jie Chen #clock-cells = <1>; 10545d2b897bSChun-Jie Chen }; 10555d2b897bSChun-Jie Chen 10567f1a9f47SFabien Parent i2c5: i2c@11e00000 { 105748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 105848489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 105948489980SSeiya Wang <0 0x10217500 0 0x80>; 106048489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 106122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 106222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 106348489980SSeiya Wang clock-names = "main", "dma"; 106448489980SSeiya Wang clock-div = <1>; 106548489980SSeiya Wang #address-cells = <1>; 106648489980SSeiya Wang #size-cells = <0>; 106748489980SSeiya Wang status = "disabled"; 106848489980SSeiya Wang }; 106948489980SSeiya Wang 10705d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 10715d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 10725d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 10735d2b897bSChun-Jie Chen #clock-cells = <1>; 10745d2b897bSChun-Jie Chen }; 10755d2b897bSChun-Jie Chen 107640de66b8SAllen-KH Cheng u3phy0: t-phy@11e40000 { 107740de66b8SAllen-KH Cheng compatible = "mediatek,mt8192-tphy", 107840de66b8SAllen-KH Cheng "mediatek,generic-tphy-v2"; 107940de66b8SAllen-KH Cheng #address-cells = <1>; 108040de66b8SAllen-KH Cheng #size-cells = <1>; 108140de66b8SAllen-KH Cheng ranges = <0x0 0x0 0x11e40000 0x1000>; 108240de66b8SAllen-KH Cheng 108340de66b8SAllen-KH Cheng u2port0: usb-phy@0 { 108440de66b8SAllen-KH Cheng reg = <0x0 0x700>; 108540de66b8SAllen-KH Cheng clocks = <&clk26m>; 108640de66b8SAllen-KH Cheng clock-names = "ref"; 108740de66b8SAllen-KH Cheng #phy-cells = <1>; 108840de66b8SAllen-KH Cheng }; 108940de66b8SAllen-KH Cheng 109040de66b8SAllen-KH Cheng u3port0: usb-phy@700 { 109140de66b8SAllen-KH Cheng reg = <0x700 0x900>; 109240de66b8SAllen-KH Cheng clocks = <&clk26m>; 109340de66b8SAllen-KH Cheng clock-names = "ref"; 109440de66b8SAllen-KH Cheng #phy-cells = <1>; 109540de66b8SAllen-KH Cheng }; 109640de66b8SAllen-KH Cheng }; 109740de66b8SAllen-KH Cheng 109885c4ec6fSAllen-KH Cheng mipi_tx0: dsi-phy@11e50000 { 109985c4ec6fSAllen-KH Cheng compatible = "mediatek,mt8183-mipi-tx"; 110085c4ec6fSAllen-KH Cheng reg = <0 0x11e50000 0 0x1000>; 110185c4ec6fSAllen-KH Cheng clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 110285c4ec6fSAllen-KH Cheng #clock-cells = <0>; 110385c4ec6fSAllen-KH Cheng #phy-cells = <0>; 110485c4ec6fSAllen-KH Cheng clock-output-names = "mipi_tx0_pll"; 110585c4ec6fSAllen-KH Cheng status = "disabled"; 110685c4ec6fSAllen-KH Cheng }; 110785c4ec6fSAllen-KH Cheng 11087f1a9f47SFabien Parent i2c0: i2c@11f00000 { 110948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 111048489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 111148489980SSeiya Wang <0 0x10217080 0 0x80>; 111248489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 111322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 111422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 111548489980SSeiya Wang clock-names = "main", "dma"; 111648489980SSeiya Wang clock-div = <1>; 111748489980SSeiya Wang #address-cells = <1>; 111848489980SSeiya Wang #size-cells = <0>; 111948489980SSeiya Wang status = "disabled"; 112048489980SSeiya Wang }; 112148489980SSeiya Wang 11227f1a9f47SFabien Parent i2c6: i2c@11f01000 { 112348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 112448489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 112548489980SSeiya Wang <0 0x10217580 0 0x80>; 112648489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 112722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 112822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 112948489980SSeiya Wang clock-names = "main", "dma"; 113048489980SSeiya Wang clock-div = <1>; 113148489980SSeiya Wang #address-cells = <1>; 113248489980SSeiya Wang #size-cells = <0>; 113348489980SSeiya Wang status = "disabled"; 113448489980SSeiya Wang }; 11355d2b897bSChun-Jie Chen 11365d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 11375d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 11385d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 11395d2b897bSChun-Jie Chen #clock-cells = <1>; 11405d2b897bSChun-Jie Chen }; 11415d2b897bSChun-Jie Chen 11425d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 11435d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 11445d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 11455d2b897bSChun-Jie Chen #clock-cells = <1>; 11465d2b897bSChun-Jie Chen }; 11475d2b897bSChun-Jie Chen 1148db61337eSAllen-KH Cheng mmc0: mmc@11f60000 { 1149db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1150db61337eSAllen-KH Cheng reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1151db61337eSAllen-KH Cheng interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1152db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1153db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1154db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1155db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1156db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1157db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1158db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1159db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1160db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1161db61337eSAllen-KH Cheng status = "disabled"; 1162db61337eSAllen-KH Cheng }; 1163db61337eSAllen-KH Cheng 1164db61337eSAllen-KH Cheng mmc1: mmc@11f70000 { 1165db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1166db61337eSAllen-KH Cheng reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1167db61337eSAllen-KH Cheng interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1168db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1169db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1170db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1171db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1172db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1173db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1174db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1175db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1176db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1177db61337eSAllen-KH Cheng status = "disabled"; 11785d2b897bSChun-Jie Chen }; 11795d2b897bSChun-Jie Chen 11805d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 11815d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 11825d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 11835d2b897bSChun-Jie Chen #clock-cells = <1>; 11845d2b897bSChun-Jie Chen }; 11855d2b897bSChun-Jie Chen 11865d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 11875d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 11885d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 11895d2b897bSChun-Jie Chen #clock-cells = <1>; 1190*7d355378SAllen-KH Cheng #reset-cells = <1>; 11915d2b897bSChun-Jie Chen }; 11925d2b897bSChun-Jie Chen 11934a65b0f1SAllen-KH Cheng smi_common: smi@14002000 { 11944a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-common"; 11954a65b0f1SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 11964a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 11974a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 11984a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 11994a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>; 12004a65b0f1SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 12014a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12024a65b0f1SAllen-KH Cheng }; 12034a65b0f1SAllen-KH Cheng 12044a65b0f1SAllen-KH Cheng larb0: larb@14003000 { 12054a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12064a65b0f1SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 12074a65b0f1SAllen-KH Cheng mediatek,larb-id = <0>; 12084a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12094a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 12104a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12114a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12124a65b0f1SAllen-KH Cheng }; 12134a65b0f1SAllen-KH Cheng 12144a65b0f1SAllen-KH Cheng larb1: larb@14004000 { 12154a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12164a65b0f1SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 12174a65b0f1SAllen-KH Cheng mediatek,larb-id = <1>; 12184a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12194a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 12204a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12214a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12224a65b0f1SAllen-KH Cheng }; 12234a65b0f1SAllen-KH Cheng 1224b2edd519SAllen-KH Cheng dpi0: dpi@14016000 { 1225b2edd519SAllen-KH Cheng compatible = "mediatek,mt8192-dpi"; 1226b2edd519SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1227b2edd519SAllen-KH Cheng interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1228b2edd519SAllen-KH Cheng clocks = <&mmsys CLK_MM_DPI_DPI0>, 1229b2edd519SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI0>, 1230b2edd519SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 1231b2edd519SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 1232b2edd519SAllen-KH Cheng status = "disabled"; 1233b2edd519SAllen-KH Cheng }; 1234b2edd519SAllen-KH Cheng 12354a65b0f1SAllen-KH Cheng iommu0: m4u@1401d000 { 12364a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-m4u"; 12374a65b0f1SAllen-KH Cheng reg = <0 0x1401d000 0 0x1000>; 12384a65b0f1SAllen-KH Cheng mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 12394a65b0f1SAllen-KH Cheng <&larb4>, <&larb5>, <&larb7>, 12404a65b0f1SAllen-KH Cheng <&larb9>, <&larb11>, <&larb13>, 12414a65b0f1SAllen-KH Cheng <&larb14>, <&larb16>, <&larb17>, 12424a65b0f1SAllen-KH Cheng <&larb18>, <&larb19>, <&larb20>; 12434a65b0f1SAllen-KH Cheng interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 12444a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 12454a65b0f1SAllen-KH Cheng clock-names = "bclk"; 12464a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12474a65b0f1SAllen-KH Cheng #iommu-cells = <1>; 12484a65b0f1SAllen-KH Cheng }; 12494a65b0f1SAllen-KH Cheng 12505d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 12515d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 12525d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 12535d2b897bSChun-Jie Chen #clock-cells = <1>; 12545d2b897bSChun-Jie Chen }; 12555d2b897bSChun-Jie Chen 12564a65b0f1SAllen-KH Cheng larb9: larb@1502e000 { 12574a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12584a65b0f1SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 12594a65b0f1SAllen-KH Cheng mediatek,larb-id = <9>; 12604a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12614a65b0f1SAllen-KH Cheng clocks = <&imgsys CLK_IMG_LARB9>, 12624a65b0f1SAllen-KH Cheng <&imgsys CLK_IMG_LARB9>; 12634a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12644a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 12654a65b0f1SAllen-KH Cheng }; 12664a65b0f1SAllen-KH Cheng 12675d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 12685d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 12695d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 12705d2b897bSChun-Jie Chen #clock-cells = <1>; 12715d2b897bSChun-Jie Chen }; 12725d2b897bSChun-Jie Chen 12734a65b0f1SAllen-KH Cheng larb11: larb@1582e000 { 12744a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12754a65b0f1SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 12764a65b0f1SAllen-KH Cheng mediatek,larb-id = <11>; 12774a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12784a65b0f1SAllen-KH Cheng clocks = <&imgsys2 CLK_IMG2_LARB11>, 12794a65b0f1SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB11>; 12804a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12814a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 12824a65b0f1SAllen-KH Cheng }; 12834a65b0f1SAllen-KH Cheng 12844a65b0f1SAllen-KH Cheng larb5: larb@1600d000 { 12854a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12864a65b0f1SAllen-KH Cheng reg = <0 0x1600d000 0 0x1000>; 12874a65b0f1SAllen-KH Cheng mediatek,larb-id = <5>; 12884a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12894a65b0f1SAllen-KH Cheng clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 12904a65b0f1SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 12914a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12924a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 12934a65b0f1SAllen-KH Cheng }; 12944a65b0f1SAllen-KH Cheng 12955d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 12965d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 12975d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 12985d2b897bSChun-Jie Chen #clock-cells = <1>; 12995d2b897bSChun-Jie Chen }; 13005d2b897bSChun-Jie Chen 13014a65b0f1SAllen-KH Cheng larb4: larb@1602e000 { 13024a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13034a65b0f1SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 13044a65b0f1SAllen-KH Cheng mediatek,larb-id = <4>; 13054a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13064a65b0f1SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 13074a65b0f1SAllen-KH Cheng <&vdecsys CLK_VDEC_SOC_LARB1>; 13084a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13094a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 13104a65b0f1SAllen-KH Cheng }; 13114a65b0f1SAllen-KH Cheng 13125d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 13135d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 13145d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 13155d2b897bSChun-Jie Chen #clock-cells = <1>; 13165d2b897bSChun-Jie Chen }; 13175d2b897bSChun-Jie Chen 13185d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 13195d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 13205d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 13215d2b897bSChun-Jie Chen #clock-cells = <1>; 13225d2b897bSChun-Jie Chen }; 13235d2b897bSChun-Jie Chen 13244a65b0f1SAllen-KH Cheng larb7: larb@17010000 { 13254a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13264a65b0f1SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 13274a65b0f1SAllen-KH Cheng mediatek,larb-id = <7>; 13284a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13294a65b0f1SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET0_LARB>, 13304a65b0f1SAllen-KH Cheng <&vencsys CLK_VENC_SET1_VENC>; 13314a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13324a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 13334a65b0f1SAllen-KH Cheng }; 13344a65b0f1SAllen-KH Cheng 1335aa8f3711SAllen-KH Cheng vcodec_enc: vcodec@17020000 { 1336aa8f3711SAllen-KH Cheng compatible = "mediatek,mt8192-vcodec-enc"; 1337aa8f3711SAllen-KH Cheng reg = <0 0x17020000 0 0x2000>; 1338aa8f3711SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1339aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REC>, 1340aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1341aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1342aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1343aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1344aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1345aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1346aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1347aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1348aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1349aa8f3711SAllen-KH Cheng interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1350aa8f3711SAllen-KH Cheng mediatek,scp = <&scp>; 1351aa8f3711SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1352aa8f3711SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET1_VENC>; 1353aa8f3711SAllen-KH Cheng clock-names = "venc-set1"; 1354aa8f3711SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1355aa8f3711SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1356aa8f3711SAllen-KH Cheng }; 1357aa8f3711SAllen-KH Cheng 13585d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 13595d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 13605d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 13615d2b897bSChun-Jie Chen #clock-cells = <1>; 13625d2b897bSChun-Jie Chen }; 13635d2b897bSChun-Jie Chen 13644a65b0f1SAllen-KH Cheng larb13: larb@1a001000 { 13654a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13664a65b0f1SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 13674a65b0f1SAllen-KH Cheng mediatek,larb-id = <13>; 13684a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13694a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 13704a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB13>; 13714a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13724a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 13734a65b0f1SAllen-KH Cheng }; 13744a65b0f1SAllen-KH Cheng 13754a65b0f1SAllen-KH Cheng larb14: larb@1a002000 { 13764a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13774a65b0f1SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 13784a65b0f1SAllen-KH Cheng mediatek,larb-id = <14>; 13794a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13804a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 13814a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB14>; 13824a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13834a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 13844a65b0f1SAllen-KH Cheng }; 13854a65b0f1SAllen-KH Cheng 13864a65b0f1SAllen-KH Cheng larb16: larb@1a00f000 { 13874a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13884a65b0f1SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 13894a65b0f1SAllen-KH Cheng mediatek,larb-id = <16>; 13904a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13914a65b0f1SAllen-KH Cheng clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 13924a65b0f1SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX>; 13934a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13944a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 13954a65b0f1SAllen-KH Cheng }; 13964a65b0f1SAllen-KH Cheng 13974a65b0f1SAllen-KH Cheng larb17: larb@1a010000 { 13984a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13994a65b0f1SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 14004a65b0f1SAllen-KH Cheng mediatek,larb-id = <17>; 14014a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14024a65b0f1SAllen-KH Cheng clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 14034a65b0f1SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX>; 14044a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14054a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 14064a65b0f1SAllen-KH Cheng }; 14074a65b0f1SAllen-KH Cheng 14084a65b0f1SAllen-KH Cheng larb18: larb@1a011000 { 14094a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14104a65b0f1SAllen-KH Cheng reg = <0 0x1a011000 0 0x1000>; 14114a65b0f1SAllen-KH Cheng mediatek,larb-id = <18>; 14124a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14134a65b0f1SAllen-KH Cheng clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 14144a65b0f1SAllen-KH Cheng <&camsys_rawc CLK_CAM_RAWC_CAM>; 14154a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14164a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 14174a65b0f1SAllen-KH Cheng }; 14184a65b0f1SAllen-KH Cheng 14195d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 14205d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 14215d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 14225d2b897bSChun-Jie Chen #clock-cells = <1>; 14235d2b897bSChun-Jie Chen }; 14245d2b897bSChun-Jie Chen 14255d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 14265d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 14275d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 14285d2b897bSChun-Jie Chen #clock-cells = <1>; 14295d2b897bSChun-Jie Chen }; 14305d2b897bSChun-Jie Chen 14315d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 14325d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 14335d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 14345d2b897bSChun-Jie Chen #clock-cells = <1>; 14355d2b897bSChun-Jie Chen }; 14365d2b897bSChun-Jie Chen 14375d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 14385d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 14395d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 14405d2b897bSChun-Jie Chen #clock-cells = <1>; 14415d2b897bSChun-Jie Chen }; 14425d2b897bSChun-Jie Chen 14434a65b0f1SAllen-KH Cheng larb20: larb@1b00f000 { 14444a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14454a65b0f1SAllen-KH Cheng reg = <0 0x1b00f000 0 0x1000>; 14464a65b0f1SAllen-KH Cheng mediatek,larb-id = <20>; 14474a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14484a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 14494a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB20>; 14504a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14514a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 14524a65b0f1SAllen-KH Cheng }; 14534a65b0f1SAllen-KH Cheng 14544a65b0f1SAllen-KH Cheng larb19: larb@1b10f000 { 14554a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14564a65b0f1SAllen-KH Cheng reg = <0 0x1b10f000 0 0x1000>; 14574a65b0f1SAllen-KH Cheng mediatek,larb-id = <19>; 14584a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14594a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 14604a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB19>; 14614a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14624a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 14634a65b0f1SAllen-KH Cheng }; 14644a65b0f1SAllen-KH Cheng 14655d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 14665d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 14675d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 14685d2b897bSChun-Jie Chen #clock-cells = <1>; 14695d2b897bSChun-Jie Chen }; 14704a65b0f1SAllen-KH Cheng 14714a65b0f1SAllen-KH Cheng larb2: larb@1f002000 { 14724a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14734a65b0f1SAllen-KH Cheng reg = <0 0x1f002000 0 0x1000>; 14744a65b0f1SAllen-KH Cheng mediatek,larb-id = <2>; 14754a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14764a65b0f1SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, 14774a65b0f1SAllen-KH Cheng <&mdpsys CLK_MDP_SMI0>; 14784a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14794a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 14804a65b0f1SAllen-KH Cheng }; 148148489980SSeiya Wang }; 148248489980SSeiya Wang}; 1483