148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 8*5d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 1148489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 1248489980SSeiya Wang 1348489980SSeiya Wang/ { 1448489980SSeiya Wang compatible = "mediatek,mt8192"; 1548489980SSeiya Wang interrupt-parent = <&gic>; 1648489980SSeiya Wang #address-cells = <2>; 1748489980SSeiya Wang #size-cells = <2>; 1848489980SSeiya Wang 1948489980SSeiya Wang clk26m: oscillator0 { 2048489980SSeiya Wang compatible = "fixed-clock"; 2148489980SSeiya Wang #clock-cells = <0>; 2248489980SSeiya Wang clock-frequency = <26000000>; 2348489980SSeiya Wang clock-output-names = "clk26m"; 2448489980SSeiya Wang }; 2548489980SSeiya Wang 2648489980SSeiya Wang clk32k: oscillator1 { 2748489980SSeiya Wang compatible = "fixed-clock"; 2848489980SSeiya Wang #clock-cells = <0>; 2948489980SSeiya Wang clock-frequency = <32768>; 3048489980SSeiya Wang clock-output-names = "clk32k"; 3148489980SSeiya Wang }; 3248489980SSeiya Wang 3348489980SSeiya Wang cpus { 3448489980SSeiya Wang #address-cells = <1>; 3548489980SSeiya Wang #size-cells = <0>; 3648489980SSeiya Wang 3748489980SSeiya Wang cpu0: cpu@0 { 3848489980SSeiya Wang device_type = "cpu"; 3948489980SSeiya Wang compatible = "arm,cortex-a55"; 4048489980SSeiya Wang reg = <0x000>; 4148489980SSeiya Wang enable-method = "psci"; 4248489980SSeiya Wang clock-frequency = <1701000000>; 439260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 4448489980SSeiya Wang next-level-cache = <&l2_0>; 4548489980SSeiya Wang capacity-dmips-mhz = <530>; 4648489980SSeiya Wang }; 4748489980SSeiya Wang 4848489980SSeiya Wang cpu1: cpu@100 { 4948489980SSeiya Wang device_type = "cpu"; 5048489980SSeiya Wang compatible = "arm,cortex-a55"; 5148489980SSeiya Wang reg = <0x100>; 5248489980SSeiya Wang enable-method = "psci"; 5348489980SSeiya Wang clock-frequency = <1701000000>; 549260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 5548489980SSeiya Wang next-level-cache = <&l2_0>; 5648489980SSeiya Wang capacity-dmips-mhz = <530>; 5748489980SSeiya Wang }; 5848489980SSeiya Wang 5948489980SSeiya Wang cpu2: cpu@200 { 6048489980SSeiya Wang device_type = "cpu"; 6148489980SSeiya Wang compatible = "arm,cortex-a55"; 6248489980SSeiya Wang reg = <0x200>; 6348489980SSeiya Wang enable-method = "psci"; 6448489980SSeiya Wang clock-frequency = <1701000000>; 659260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 6648489980SSeiya Wang next-level-cache = <&l2_0>; 6748489980SSeiya Wang capacity-dmips-mhz = <530>; 6848489980SSeiya Wang }; 6948489980SSeiya Wang 7048489980SSeiya Wang cpu3: cpu@300 { 7148489980SSeiya Wang device_type = "cpu"; 7248489980SSeiya Wang compatible = "arm,cortex-a55"; 7348489980SSeiya Wang reg = <0x300>; 7448489980SSeiya Wang enable-method = "psci"; 7548489980SSeiya Wang clock-frequency = <1701000000>; 769260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 7748489980SSeiya Wang next-level-cache = <&l2_0>; 7848489980SSeiya Wang capacity-dmips-mhz = <530>; 7948489980SSeiya Wang }; 8048489980SSeiya Wang 8148489980SSeiya Wang cpu4: cpu@400 { 8248489980SSeiya Wang device_type = "cpu"; 8348489980SSeiya Wang compatible = "arm,cortex-a76"; 8448489980SSeiya Wang reg = <0x400>; 8548489980SSeiya Wang enable-method = "psci"; 8648489980SSeiya Wang clock-frequency = <2171000000>; 879260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 8848489980SSeiya Wang next-level-cache = <&l2_1>; 8948489980SSeiya Wang capacity-dmips-mhz = <1024>; 9048489980SSeiya Wang }; 9148489980SSeiya Wang 9248489980SSeiya Wang cpu5: cpu@500 { 9348489980SSeiya Wang device_type = "cpu"; 9448489980SSeiya Wang compatible = "arm,cortex-a76"; 9548489980SSeiya Wang reg = <0x500>; 9648489980SSeiya Wang enable-method = "psci"; 9748489980SSeiya Wang clock-frequency = <2171000000>; 989260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 9948489980SSeiya Wang next-level-cache = <&l2_1>; 10048489980SSeiya Wang capacity-dmips-mhz = <1024>; 10148489980SSeiya Wang }; 10248489980SSeiya Wang 10348489980SSeiya Wang cpu6: cpu@600 { 10448489980SSeiya Wang device_type = "cpu"; 10548489980SSeiya Wang compatible = "arm,cortex-a76"; 10648489980SSeiya Wang reg = <0x600>; 10748489980SSeiya Wang enable-method = "psci"; 10848489980SSeiya Wang clock-frequency = <2171000000>; 1099260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 11048489980SSeiya Wang next-level-cache = <&l2_1>; 11148489980SSeiya Wang capacity-dmips-mhz = <1024>; 11248489980SSeiya Wang }; 11348489980SSeiya Wang 11448489980SSeiya Wang cpu7: cpu@700 { 11548489980SSeiya Wang device_type = "cpu"; 11648489980SSeiya Wang compatible = "arm,cortex-a76"; 11748489980SSeiya Wang reg = <0x700>; 11848489980SSeiya Wang enable-method = "psci"; 11948489980SSeiya Wang clock-frequency = <2171000000>; 1209260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 12148489980SSeiya Wang next-level-cache = <&l2_1>; 12248489980SSeiya Wang capacity-dmips-mhz = <1024>; 12348489980SSeiya Wang }; 12448489980SSeiya Wang 12548489980SSeiya Wang cpu-map { 12648489980SSeiya Wang cluster0 { 12748489980SSeiya Wang core0 { 12848489980SSeiya Wang cpu = <&cpu0>; 12948489980SSeiya Wang }; 13048489980SSeiya Wang core1 { 13148489980SSeiya Wang cpu = <&cpu1>; 13248489980SSeiya Wang }; 13348489980SSeiya Wang core2 { 13448489980SSeiya Wang cpu = <&cpu2>; 13548489980SSeiya Wang }; 13648489980SSeiya Wang core3 { 13748489980SSeiya Wang cpu = <&cpu3>; 13848489980SSeiya Wang }; 13948489980SSeiya Wang }; 14048489980SSeiya Wang 14148489980SSeiya Wang cluster1 { 14248489980SSeiya Wang core0 { 14348489980SSeiya Wang cpu = <&cpu4>; 14448489980SSeiya Wang }; 14548489980SSeiya Wang core1 { 14648489980SSeiya Wang cpu = <&cpu5>; 14748489980SSeiya Wang }; 14848489980SSeiya Wang core2 { 14948489980SSeiya Wang cpu = <&cpu6>; 15048489980SSeiya Wang }; 15148489980SSeiya Wang core3 { 15248489980SSeiya Wang cpu = <&cpu7>; 15348489980SSeiya Wang }; 15448489980SSeiya Wang }; 15548489980SSeiya Wang }; 15648489980SSeiya Wang 15748489980SSeiya Wang l2_0: l2-cache0 { 15848489980SSeiya Wang compatible = "cache"; 15948489980SSeiya Wang next-level-cache = <&l3_0>; 16048489980SSeiya Wang }; 16148489980SSeiya Wang 16248489980SSeiya Wang l2_1: l2-cache1 { 16348489980SSeiya Wang compatible = "cache"; 16448489980SSeiya Wang next-level-cache = <&l3_0>; 16548489980SSeiya Wang }; 16648489980SSeiya Wang 16748489980SSeiya Wang l3_0: l3-cache { 16848489980SSeiya Wang compatible = "cache"; 16948489980SSeiya Wang }; 1709260918dSJames Liao 1719260918dSJames Liao idle-states { 1729260918dSJames Liao entry-method = "arm,psci"; 1739260918dSJames Liao cpuoff_l: cpuoff_l { 1749260918dSJames Liao compatible = "arm,idle-state"; 1759260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1769260918dSJames Liao local-timer-stop; 1779260918dSJames Liao entry-latency-us = <55>; 1789260918dSJames Liao exit-latency-us = <140>; 1799260918dSJames Liao min-residency-us = <780>; 1809260918dSJames Liao }; 1819260918dSJames Liao cpuoff_b: cpuoff_b { 1829260918dSJames Liao compatible = "arm,idle-state"; 1839260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1849260918dSJames Liao local-timer-stop; 1859260918dSJames Liao entry-latency-us = <35>; 1869260918dSJames Liao exit-latency-us = <145>; 1879260918dSJames Liao min-residency-us = <720>; 1889260918dSJames Liao }; 1899260918dSJames Liao clusteroff_l: clusteroff_l { 1909260918dSJames Liao compatible = "arm,idle-state"; 1919260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 1929260918dSJames Liao local-timer-stop; 1939260918dSJames Liao entry-latency-us = <60>; 1949260918dSJames Liao exit-latency-us = <155>; 1959260918dSJames Liao min-residency-us = <860>; 1969260918dSJames Liao }; 1979260918dSJames Liao clusteroff_b: clusteroff_b { 1989260918dSJames Liao compatible = "arm,idle-state"; 1999260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2009260918dSJames Liao local-timer-stop; 2019260918dSJames Liao entry-latency-us = <40>; 2029260918dSJames Liao exit-latency-us = <155>; 2039260918dSJames Liao min-residency-us = <780>; 2049260918dSJames Liao }; 2059260918dSJames Liao }; 20648489980SSeiya Wang }; 20748489980SSeiya Wang 20848489980SSeiya Wang pmu-a55 { 20948489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 21048489980SSeiya Wang interrupt-parent = <&gic>; 21148489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 21248489980SSeiya Wang }; 21348489980SSeiya Wang 21448489980SSeiya Wang pmu-a76 { 21548489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 21648489980SSeiya Wang interrupt-parent = <&gic>; 21748489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 21848489980SSeiya Wang }; 21948489980SSeiya Wang 22048489980SSeiya Wang psci { 22148489980SSeiya Wang compatible = "arm,psci-1.0"; 22248489980SSeiya Wang method = "smc"; 22348489980SSeiya Wang }; 22448489980SSeiya Wang 22548489980SSeiya Wang timer: timer { 22648489980SSeiya Wang compatible = "arm,armv8-timer"; 22748489980SSeiya Wang interrupt-parent = <&gic>; 22848489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 22948489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 23048489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 23148489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 23248489980SSeiya Wang clock-frequency = <13000000>; 23348489980SSeiya Wang }; 23448489980SSeiya Wang 23548489980SSeiya Wang soc { 23648489980SSeiya Wang #address-cells = <2>; 23748489980SSeiya Wang #size-cells = <2>; 23848489980SSeiya Wang compatible = "simple-bus"; 23948489980SSeiya Wang ranges; 24048489980SSeiya Wang 24148489980SSeiya Wang gic: interrupt-controller@c000000 { 24248489980SSeiya Wang compatible = "arm,gic-v3"; 24348489980SSeiya Wang #interrupt-cells = <4>; 24448489980SSeiya Wang #redistributor-regions = <1>; 24548489980SSeiya Wang interrupt-parent = <&gic>; 24648489980SSeiya Wang interrupt-controller; 24748489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 24848489980SSeiya Wang <0 0x0c040000 0 0x200000>; 24948489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 25048489980SSeiya Wang 25148489980SSeiya Wang ppi-partitions { 25248489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 25348489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 25448489980SSeiya Wang }; 25548489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 25648489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 25748489980SSeiya Wang }; 25848489980SSeiya Wang }; 25948489980SSeiya Wang }; 26048489980SSeiya Wang 261*5d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 262*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 263*5d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 264*5d2b897bSChun-Jie Chen #clock-cells = <1>; 265*5d2b897bSChun-Jie Chen }; 266*5d2b897bSChun-Jie Chen 267*5d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 268*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 269*5d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 270*5d2b897bSChun-Jie Chen #clock-cells = <1>; 271*5d2b897bSChun-Jie Chen }; 272*5d2b897bSChun-Jie Chen 273*5d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 274*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 275*5d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 276*5d2b897bSChun-Jie Chen #clock-cells = <1>; 277*5d2b897bSChun-Jie Chen }; 278*5d2b897bSChun-Jie Chen 27948489980SSeiya Wang pio: pinctrl@10005000 { 28048489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 28148489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 28248489980SSeiya Wang <0 0x11c20000 0 0x1000>, 28348489980SSeiya Wang <0 0x11d10000 0 0x1000>, 28448489980SSeiya Wang <0 0x11d30000 0 0x1000>, 28548489980SSeiya Wang <0 0x11d40000 0 0x1000>, 28648489980SSeiya Wang <0 0x11e20000 0 0x1000>, 28748489980SSeiya Wang <0 0x11e70000 0 0x1000>, 28848489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 28948489980SSeiya Wang <0 0x11f20000 0 0x1000>, 29048489980SSeiya Wang <0 0x11f30000 0 0x1000>, 29148489980SSeiya Wang <0 0x1000b000 0 0x1000>; 29248489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 29348489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 29448489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 29548489980SSeiya Wang "iocfg_tl", "eint"; 29648489980SSeiya Wang gpio-controller; 29748489980SSeiya Wang #gpio-cells = <2>; 29848489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 29948489980SSeiya Wang interrupt-controller; 30048489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 30148489980SSeiya Wang #interrupt-cells = <2>; 30248489980SSeiya Wang }; 30348489980SSeiya Wang 304*5d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 305*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 306*5d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 307*5d2b897bSChun-Jie Chen #clock-cells = <1>; 308*5d2b897bSChun-Jie Chen }; 309*5d2b897bSChun-Jie Chen 31048489980SSeiya Wang systimer: timer@10017000 { 31148489980SSeiya Wang compatible = "mediatek,mt8192-timer", 31248489980SSeiya Wang "mediatek,mt6765-timer"; 31348489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 31448489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 31548489980SSeiya Wang clocks = <&clk26m>; 31648489980SSeiya Wang clock-names = "clk13m"; 31748489980SSeiya Wang }; 31848489980SSeiya Wang 319*5d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 320*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 321*5d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 322*5d2b897bSChun-Jie Chen #clock-cells = <1>; 323*5d2b897bSChun-Jie Chen }; 324*5d2b897bSChun-Jie Chen 32548489980SSeiya Wang uart0: serial@11002000 { 32648489980SSeiya Wang compatible = "mediatek,mt8192-uart", 32748489980SSeiya Wang "mediatek,mt6577-uart"; 32848489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 32948489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 33048489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 33148489980SSeiya Wang clock-names = "baud", "bus"; 33248489980SSeiya Wang status = "disabled"; 33348489980SSeiya Wang }; 33448489980SSeiya Wang 33548489980SSeiya Wang uart1: serial@11003000 { 33648489980SSeiya Wang compatible = "mediatek,mt8192-uart", 33748489980SSeiya Wang "mediatek,mt6577-uart"; 33848489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 33948489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 34048489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 34148489980SSeiya Wang clock-names = "baud", "bus"; 34248489980SSeiya Wang status = "disabled"; 34348489980SSeiya Wang }; 34448489980SSeiya Wang 345*5d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 346*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 347*5d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 348*5d2b897bSChun-Jie Chen #clock-cells = <1>; 349*5d2b897bSChun-Jie Chen }; 350*5d2b897bSChun-Jie Chen 35148489980SSeiya Wang spi0: spi@1100a000 { 35248489980SSeiya Wang compatible = "mediatek,mt8192-spi", 35348489980SSeiya Wang "mediatek,mt6765-spi"; 35448489980SSeiya Wang #address-cells = <1>; 35548489980SSeiya Wang #size-cells = <0>; 35648489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 35748489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 35848489980SSeiya Wang clocks = <&clk26m>, 35948489980SSeiya Wang <&clk26m>, 36048489980SSeiya Wang <&clk26m>; 36148489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 36248489980SSeiya Wang status = "disabled"; 36348489980SSeiya Wang }; 36448489980SSeiya Wang 36548489980SSeiya Wang spi1: spi@11010000 { 36648489980SSeiya Wang compatible = "mediatek,mt8192-spi", 36748489980SSeiya Wang "mediatek,mt6765-spi"; 36848489980SSeiya Wang #address-cells = <1>; 36948489980SSeiya Wang #size-cells = <0>; 37048489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 37148489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 37248489980SSeiya Wang clocks = <&clk26m>, 37348489980SSeiya Wang <&clk26m>, 37448489980SSeiya Wang <&clk26m>; 37548489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 37648489980SSeiya Wang status = "disabled"; 37748489980SSeiya Wang }; 37848489980SSeiya Wang 37948489980SSeiya Wang spi2: spi@11012000 { 38048489980SSeiya Wang compatible = "mediatek,mt8192-spi", 38148489980SSeiya Wang "mediatek,mt6765-spi"; 38248489980SSeiya Wang #address-cells = <1>; 38348489980SSeiya Wang #size-cells = <0>; 38448489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 38548489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 38648489980SSeiya Wang clocks = <&clk26m>, 38748489980SSeiya Wang <&clk26m>, 38848489980SSeiya Wang <&clk26m>; 38948489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 39048489980SSeiya Wang status = "disabled"; 39148489980SSeiya Wang }; 39248489980SSeiya Wang 39348489980SSeiya Wang spi3: spi@11013000 { 39448489980SSeiya Wang compatible = "mediatek,mt8192-spi", 39548489980SSeiya Wang "mediatek,mt6765-spi"; 39648489980SSeiya Wang #address-cells = <1>; 39748489980SSeiya Wang #size-cells = <0>; 39848489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 39948489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 40048489980SSeiya Wang clocks = <&clk26m>, 40148489980SSeiya Wang <&clk26m>, 40248489980SSeiya Wang <&clk26m>; 40348489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 40448489980SSeiya Wang status = "disabled"; 40548489980SSeiya Wang }; 40648489980SSeiya Wang 40748489980SSeiya Wang spi4: spi@11018000 { 40848489980SSeiya Wang compatible = "mediatek,mt8192-spi", 40948489980SSeiya Wang "mediatek,mt6765-spi"; 41048489980SSeiya Wang #address-cells = <1>; 41148489980SSeiya Wang #size-cells = <0>; 41248489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 41348489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 41448489980SSeiya Wang clocks = <&clk26m>, 41548489980SSeiya Wang <&clk26m>, 41648489980SSeiya Wang <&clk26m>; 41748489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 41848489980SSeiya Wang status = "disabled"; 41948489980SSeiya Wang }; 42048489980SSeiya Wang 42148489980SSeiya Wang spi5: spi@11019000 { 42248489980SSeiya Wang compatible = "mediatek,mt8192-spi", 42348489980SSeiya Wang "mediatek,mt6765-spi"; 42448489980SSeiya Wang #address-cells = <1>; 42548489980SSeiya Wang #size-cells = <0>; 42648489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 42748489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 42848489980SSeiya Wang clocks = <&clk26m>, 42948489980SSeiya Wang <&clk26m>, 43048489980SSeiya Wang <&clk26m>; 43148489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 43248489980SSeiya Wang status = "disabled"; 43348489980SSeiya Wang }; 43448489980SSeiya Wang 43548489980SSeiya Wang spi6: spi@1101d000 { 43648489980SSeiya Wang compatible = "mediatek,mt8192-spi", 43748489980SSeiya Wang "mediatek,mt6765-spi"; 43848489980SSeiya Wang #address-cells = <1>; 43948489980SSeiya Wang #size-cells = <0>; 44048489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 44148489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 44248489980SSeiya Wang clocks = <&clk26m>, 44348489980SSeiya Wang <&clk26m>, 44448489980SSeiya Wang <&clk26m>; 44548489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 44648489980SSeiya Wang status = "disabled"; 44748489980SSeiya Wang }; 44848489980SSeiya Wang 44948489980SSeiya Wang spi7: spi@1101e000 { 45048489980SSeiya Wang compatible = "mediatek,mt8192-spi", 45148489980SSeiya Wang "mediatek,mt6765-spi"; 45248489980SSeiya Wang #address-cells = <1>; 45348489980SSeiya Wang #size-cells = <0>; 45448489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 45548489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 45648489980SSeiya Wang clocks = <&clk26m>, 45748489980SSeiya Wang <&clk26m>, 45848489980SSeiya Wang <&clk26m>; 45948489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 46048489980SSeiya Wang status = "disabled"; 46148489980SSeiya Wang }; 46248489980SSeiya Wang 463d0a197a0Sbayi cheng nor_flash: spi@11234000 { 464d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 465d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 466d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 467d0a197a0Sbayi cheng clocks = <&clk26m>, 468d0a197a0Sbayi cheng <&clk26m>, 469d0a197a0Sbayi cheng <&clk26m>; 470d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 471d0a197a0Sbayi cheng #address-cells = <1>; 472d0a197a0Sbayi cheng #size-cells = <0>; 473d0a197a0Sbayi cheng status = "disable"; 474d0a197a0Sbayi cheng }; 475d0a197a0Sbayi cheng 476*5d2b897bSChun-Jie Chen audsys: clock-controller@11210000 { 477*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-audsys", "syscon"; 478*5d2b897bSChun-Jie Chen reg = <0 0x11210000 0 0x1000>; 479*5d2b897bSChun-Jie Chen #clock-cells = <1>; 480*5d2b897bSChun-Jie Chen }; 481*5d2b897bSChun-Jie Chen 48248489980SSeiya Wang i2c3: i2c3@11cb0000 { 48348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 48448489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 48548489980SSeiya Wang <0 0x10217300 0 0x80>; 48648489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 48748489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 48848489980SSeiya Wang clock-names = "main", "dma"; 48948489980SSeiya Wang clock-div = <1>; 49048489980SSeiya Wang #address-cells = <1>; 49148489980SSeiya Wang #size-cells = <0>; 49248489980SSeiya Wang status = "disabled"; 49348489980SSeiya Wang }; 49448489980SSeiya Wang 495*5d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 496*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 497*5d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 498*5d2b897bSChun-Jie Chen #clock-cells = <1>; 499*5d2b897bSChun-Jie Chen }; 500*5d2b897bSChun-Jie Chen 50148489980SSeiya Wang i2c7: i2c7@11d00000 { 50248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 50348489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 50448489980SSeiya Wang <0 0x10217600 0 0x180>; 50548489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 50648489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 50748489980SSeiya Wang clock-names = "main", "dma"; 50848489980SSeiya Wang clock-div = <1>; 50948489980SSeiya Wang #address-cells = <1>; 51048489980SSeiya Wang #size-cells = <0>; 51148489980SSeiya Wang status = "disabled"; 51248489980SSeiya Wang }; 51348489980SSeiya Wang 51448489980SSeiya Wang i2c8: i2c8@11d01000 { 51548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 51648489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 51748489980SSeiya Wang <0 0x10217780 0 0x180>; 51848489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 51948489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 52048489980SSeiya Wang clock-names = "main", "dma"; 52148489980SSeiya Wang clock-div = <1>; 52248489980SSeiya Wang #address-cells = <1>; 52348489980SSeiya Wang #size-cells = <0>; 52448489980SSeiya Wang status = "disabled"; 52548489980SSeiya Wang }; 52648489980SSeiya Wang 52748489980SSeiya Wang i2c9: i2c9@11d02000 { 52848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 52948489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 53048489980SSeiya Wang <0 0x10217900 0 0x180>; 53148489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 53248489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 53348489980SSeiya Wang clock-names = "main", "dma"; 53448489980SSeiya Wang clock-div = <1>; 53548489980SSeiya Wang #address-cells = <1>; 53648489980SSeiya Wang #size-cells = <0>; 53748489980SSeiya Wang status = "disabled"; 53848489980SSeiya Wang }; 53948489980SSeiya Wang 540*5d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 541*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 542*5d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 543*5d2b897bSChun-Jie Chen #clock-cells = <1>; 544*5d2b897bSChun-Jie Chen }; 545*5d2b897bSChun-Jie Chen 54648489980SSeiya Wang i2c1: i2c1@11d20000 { 54748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 54848489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 54948489980SSeiya Wang <0 0x10217100 0 0x80>; 55048489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 55148489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 55248489980SSeiya Wang clock-names = "main", "dma"; 55348489980SSeiya Wang clock-div = <1>; 55448489980SSeiya Wang #address-cells = <1>; 55548489980SSeiya Wang #size-cells = <0>; 55648489980SSeiya Wang status = "disabled"; 55748489980SSeiya Wang }; 55848489980SSeiya Wang 55948489980SSeiya Wang i2c2: i2c2@11d21000 { 56048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 56148489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 56248489980SSeiya Wang <0 0x10217180 0 0x180>; 56348489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 56448489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 56548489980SSeiya Wang clock-names = "main", "dma"; 56648489980SSeiya Wang clock-div = <1>; 56748489980SSeiya Wang #address-cells = <1>; 56848489980SSeiya Wang #size-cells = <0>; 56948489980SSeiya Wang status = "disabled"; 57048489980SSeiya Wang }; 57148489980SSeiya Wang 57248489980SSeiya Wang i2c4: i2c4@11d22000 { 57348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 57448489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 57548489980SSeiya Wang <0 0x10217380 0 0x180>; 57648489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 57748489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 57848489980SSeiya Wang clock-names = "main", "dma"; 57948489980SSeiya Wang clock-div = <1>; 58048489980SSeiya Wang #address-cells = <1>; 58148489980SSeiya Wang #size-cells = <0>; 58248489980SSeiya Wang status = "disabled"; 58348489980SSeiya Wang }; 58448489980SSeiya Wang 585*5d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 586*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 587*5d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 588*5d2b897bSChun-Jie Chen #clock-cells = <1>; 589*5d2b897bSChun-Jie Chen }; 590*5d2b897bSChun-Jie Chen 59148489980SSeiya Wang i2c5: i2c5@11e00000 { 59248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 59348489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 59448489980SSeiya Wang <0 0x10217500 0 0x80>; 59548489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 59648489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 59748489980SSeiya Wang clock-names = "main", "dma"; 59848489980SSeiya Wang clock-div = <1>; 59948489980SSeiya Wang #address-cells = <1>; 60048489980SSeiya Wang #size-cells = <0>; 60148489980SSeiya Wang status = "disabled"; 60248489980SSeiya Wang }; 60348489980SSeiya Wang 604*5d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 605*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 606*5d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 607*5d2b897bSChun-Jie Chen #clock-cells = <1>; 608*5d2b897bSChun-Jie Chen }; 609*5d2b897bSChun-Jie Chen 61048489980SSeiya Wang i2c0: i2c0@11f00000 { 61148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 61248489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 61348489980SSeiya Wang <0 0x10217080 0 0x80>; 61448489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 61548489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 61648489980SSeiya Wang clock-names = "main", "dma"; 61748489980SSeiya Wang clock-div = <1>; 61848489980SSeiya Wang #address-cells = <1>; 61948489980SSeiya Wang #size-cells = <0>; 62048489980SSeiya Wang status = "disabled"; 62148489980SSeiya Wang }; 62248489980SSeiya Wang 62348489980SSeiya Wang i2c6: i2c6@11f01000 { 62448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 62548489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 62648489980SSeiya Wang <0 0x10217580 0 0x80>; 62748489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 62848489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 62948489980SSeiya Wang clock-names = "main", "dma"; 63048489980SSeiya Wang clock-div = <1>; 63148489980SSeiya Wang #address-cells = <1>; 63248489980SSeiya Wang #size-cells = <0>; 63348489980SSeiya Wang status = "disabled"; 63448489980SSeiya Wang }; 635*5d2b897bSChun-Jie Chen 636*5d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 637*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 638*5d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 639*5d2b897bSChun-Jie Chen #clock-cells = <1>; 640*5d2b897bSChun-Jie Chen }; 641*5d2b897bSChun-Jie Chen 642*5d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 643*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 644*5d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 645*5d2b897bSChun-Jie Chen #clock-cells = <1>; 646*5d2b897bSChun-Jie Chen }; 647*5d2b897bSChun-Jie Chen 648*5d2b897bSChun-Jie Chen msdc: clock-controller@11f60000 { 649*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc"; 650*5d2b897bSChun-Jie Chen reg = <0 0x11f60000 0 0x1000>; 651*5d2b897bSChun-Jie Chen #clock-cells = <1>; 652*5d2b897bSChun-Jie Chen }; 653*5d2b897bSChun-Jie Chen 654*5d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 655*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 656*5d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 657*5d2b897bSChun-Jie Chen #clock-cells = <1>; 658*5d2b897bSChun-Jie Chen }; 659*5d2b897bSChun-Jie Chen 660*5d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 661*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 662*5d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 663*5d2b897bSChun-Jie Chen #clock-cells = <1>; 664*5d2b897bSChun-Jie Chen }; 665*5d2b897bSChun-Jie Chen 666*5d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 667*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 668*5d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 669*5d2b897bSChun-Jie Chen #clock-cells = <1>; 670*5d2b897bSChun-Jie Chen }; 671*5d2b897bSChun-Jie Chen 672*5d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 673*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 674*5d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 675*5d2b897bSChun-Jie Chen #clock-cells = <1>; 676*5d2b897bSChun-Jie Chen }; 677*5d2b897bSChun-Jie Chen 678*5d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 679*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 680*5d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 681*5d2b897bSChun-Jie Chen #clock-cells = <1>; 682*5d2b897bSChun-Jie Chen }; 683*5d2b897bSChun-Jie Chen 684*5d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 685*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 686*5d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 687*5d2b897bSChun-Jie Chen #clock-cells = <1>; 688*5d2b897bSChun-Jie Chen }; 689*5d2b897bSChun-Jie Chen 690*5d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 691*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 692*5d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 693*5d2b897bSChun-Jie Chen #clock-cells = <1>; 694*5d2b897bSChun-Jie Chen }; 695*5d2b897bSChun-Jie Chen 696*5d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 697*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 698*5d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 699*5d2b897bSChun-Jie Chen #clock-cells = <1>; 700*5d2b897bSChun-Jie Chen }; 701*5d2b897bSChun-Jie Chen 702*5d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 703*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 704*5d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 705*5d2b897bSChun-Jie Chen #clock-cells = <1>; 706*5d2b897bSChun-Jie Chen }; 707*5d2b897bSChun-Jie Chen 708*5d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 709*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 710*5d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 711*5d2b897bSChun-Jie Chen #clock-cells = <1>; 712*5d2b897bSChun-Jie Chen }; 713*5d2b897bSChun-Jie Chen 714*5d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 715*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 716*5d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 717*5d2b897bSChun-Jie Chen #clock-cells = <1>; 718*5d2b897bSChun-Jie Chen }; 719*5d2b897bSChun-Jie Chen 720*5d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 721*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 722*5d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 723*5d2b897bSChun-Jie Chen #clock-cells = <1>; 724*5d2b897bSChun-Jie Chen }; 725*5d2b897bSChun-Jie Chen 726*5d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 727*5d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 728*5d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 729*5d2b897bSChun-Jie Chen #clock-cells = <1>; 730*5d2b897bSChun-Jie Chen }; 73148489980SSeiya Wang }; 73248489980SSeiya Wang}; 733