148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 1148489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 12e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h> 13994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 1448489980SSeiya Wang 1548489980SSeiya Wang/ { 1648489980SSeiya Wang compatible = "mediatek,mt8192"; 1748489980SSeiya Wang interrupt-parent = <&gic>; 1848489980SSeiya Wang #address-cells = <2>; 1948489980SSeiya Wang #size-cells = <2>; 2048489980SSeiya Wang 2148489980SSeiya Wang clk26m: oscillator0 { 2248489980SSeiya Wang compatible = "fixed-clock"; 2348489980SSeiya Wang #clock-cells = <0>; 2448489980SSeiya Wang clock-frequency = <26000000>; 2548489980SSeiya Wang clock-output-names = "clk26m"; 2648489980SSeiya Wang }; 2748489980SSeiya Wang 2848489980SSeiya Wang clk32k: oscillator1 { 2948489980SSeiya Wang compatible = "fixed-clock"; 3048489980SSeiya Wang #clock-cells = <0>; 3148489980SSeiya Wang clock-frequency = <32768>; 3248489980SSeiya Wang clock-output-names = "clk32k"; 3348489980SSeiya Wang }; 3448489980SSeiya Wang 3548489980SSeiya Wang cpus { 3648489980SSeiya Wang #address-cells = <1>; 3748489980SSeiya Wang #size-cells = <0>; 3848489980SSeiya Wang 3948489980SSeiya Wang cpu0: cpu@0 { 4048489980SSeiya Wang device_type = "cpu"; 4148489980SSeiya Wang compatible = "arm,cortex-a55"; 4248489980SSeiya Wang reg = <0x000>; 4348489980SSeiya Wang enable-method = "psci"; 4448489980SSeiya Wang clock-frequency = <1701000000>; 459260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 4648489980SSeiya Wang next-level-cache = <&l2_0>; 4748489980SSeiya Wang capacity-dmips-mhz = <530>; 4848489980SSeiya Wang }; 4948489980SSeiya Wang 5048489980SSeiya Wang cpu1: cpu@100 { 5148489980SSeiya Wang device_type = "cpu"; 5248489980SSeiya Wang compatible = "arm,cortex-a55"; 5348489980SSeiya Wang reg = <0x100>; 5448489980SSeiya Wang enable-method = "psci"; 5548489980SSeiya Wang clock-frequency = <1701000000>; 569260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 5748489980SSeiya Wang next-level-cache = <&l2_0>; 5848489980SSeiya Wang capacity-dmips-mhz = <530>; 5948489980SSeiya Wang }; 6048489980SSeiya Wang 6148489980SSeiya Wang cpu2: cpu@200 { 6248489980SSeiya Wang device_type = "cpu"; 6348489980SSeiya Wang compatible = "arm,cortex-a55"; 6448489980SSeiya Wang reg = <0x200>; 6548489980SSeiya Wang enable-method = "psci"; 6648489980SSeiya Wang clock-frequency = <1701000000>; 679260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 6848489980SSeiya Wang next-level-cache = <&l2_0>; 6948489980SSeiya Wang capacity-dmips-mhz = <530>; 7048489980SSeiya Wang }; 7148489980SSeiya Wang 7248489980SSeiya Wang cpu3: cpu@300 { 7348489980SSeiya Wang device_type = "cpu"; 7448489980SSeiya Wang compatible = "arm,cortex-a55"; 7548489980SSeiya Wang reg = <0x300>; 7648489980SSeiya Wang enable-method = "psci"; 7748489980SSeiya Wang clock-frequency = <1701000000>; 789260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 7948489980SSeiya Wang next-level-cache = <&l2_0>; 8048489980SSeiya Wang capacity-dmips-mhz = <530>; 8148489980SSeiya Wang }; 8248489980SSeiya Wang 8348489980SSeiya Wang cpu4: cpu@400 { 8448489980SSeiya Wang device_type = "cpu"; 8548489980SSeiya Wang compatible = "arm,cortex-a76"; 8648489980SSeiya Wang reg = <0x400>; 8748489980SSeiya Wang enable-method = "psci"; 8848489980SSeiya Wang clock-frequency = <2171000000>; 899260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 9048489980SSeiya Wang next-level-cache = <&l2_1>; 9148489980SSeiya Wang capacity-dmips-mhz = <1024>; 9248489980SSeiya Wang }; 9348489980SSeiya Wang 9448489980SSeiya Wang cpu5: cpu@500 { 9548489980SSeiya Wang device_type = "cpu"; 9648489980SSeiya Wang compatible = "arm,cortex-a76"; 9748489980SSeiya Wang reg = <0x500>; 9848489980SSeiya Wang enable-method = "psci"; 9948489980SSeiya Wang clock-frequency = <2171000000>; 1009260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 10148489980SSeiya Wang next-level-cache = <&l2_1>; 10248489980SSeiya Wang capacity-dmips-mhz = <1024>; 10348489980SSeiya Wang }; 10448489980SSeiya Wang 10548489980SSeiya Wang cpu6: cpu@600 { 10648489980SSeiya Wang device_type = "cpu"; 10748489980SSeiya Wang compatible = "arm,cortex-a76"; 10848489980SSeiya Wang reg = <0x600>; 10948489980SSeiya Wang enable-method = "psci"; 11048489980SSeiya Wang clock-frequency = <2171000000>; 1119260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 11248489980SSeiya Wang next-level-cache = <&l2_1>; 11348489980SSeiya Wang capacity-dmips-mhz = <1024>; 11448489980SSeiya Wang }; 11548489980SSeiya Wang 11648489980SSeiya Wang cpu7: cpu@700 { 11748489980SSeiya Wang device_type = "cpu"; 11848489980SSeiya Wang compatible = "arm,cortex-a76"; 11948489980SSeiya Wang reg = <0x700>; 12048489980SSeiya Wang enable-method = "psci"; 12148489980SSeiya Wang clock-frequency = <2171000000>; 1229260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 12348489980SSeiya Wang next-level-cache = <&l2_1>; 12448489980SSeiya Wang capacity-dmips-mhz = <1024>; 12548489980SSeiya Wang }; 12648489980SSeiya Wang 12748489980SSeiya Wang cpu-map { 12848489980SSeiya Wang cluster0 { 12948489980SSeiya Wang core0 { 13048489980SSeiya Wang cpu = <&cpu0>; 13148489980SSeiya Wang }; 13248489980SSeiya Wang core1 { 13348489980SSeiya Wang cpu = <&cpu1>; 13448489980SSeiya Wang }; 13548489980SSeiya Wang core2 { 13648489980SSeiya Wang cpu = <&cpu2>; 13748489980SSeiya Wang }; 13848489980SSeiya Wang core3 { 13948489980SSeiya Wang cpu = <&cpu3>; 14048489980SSeiya Wang }; 14148489980SSeiya Wang }; 14248489980SSeiya Wang 14348489980SSeiya Wang cluster1 { 14448489980SSeiya Wang core0 { 14548489980SSeiya Wang cpu = <&cpu4>; 14648489980SSeiya Wang }; 14748489980SSeiya Wang core1 { 14848489980SSeiya Wang cpu = <&cpu5>; 14948489980SSeiya Wang }; 15048489980SSeiya Wang core2 { 15148489980SSeiya Wang cpu = <&cpu6>; 15248489980SSeiya Wang }; 15348489980SSeiya Wang core3 { 15448489980SSeiya Wang cpu = <&cpu7>; 15548489980SSeiya Wang }; 15648489980SSeiya Wang }; 15748489980SSeiya Wang }; 15848489980SSeiya Wang 15948489980SSeiya Wang l2_0: l2-cache0 { 16048489980SSeiya Wang compatible = "cache"; 16148489980SSeiya Wang next-level-cache = <&l3_0>; 16248489980SSeiya Wang }; 16348489980SSeiya Wang 16448489980SSeiya Wang l2_1: l2-cache1 { 16548489980SSeiya Wang compatible = "cache"; 16648489980SSeiya Wang next-level-cache = <&l3_0>; 16748489980SSeiya Wang }; 16848489980SSeiya Wang 16948489980SSeiya Wang l3_0: l3-cache { 17048489980SSeiya Wang compatible = "cache"; 17148489980SSeiya Wang }; 1729260918dSJames Liao 1739260918dSJames Liao idle-states { 1749260918dSJames Liao entry-method = "arm,psci"; 1759260918dSJames Liao cpuoff_l: cpuoff_l { 1769260918dSJames Liao compatible = "arm,idle-state"; 1779260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1789260918dSJames Liao local-timer-stop; 1799260918dSJames Liao entry-latency-us = <55>; 1809260918dSJames Liao exit-latency-us = <140>; 1819260918dSJames Liao min-residency-us = <780>; 1829260918dSJames Liao }; 1839260918dSJames Liao cpuoff_b: cpuoff_b { 1849260918dSJames Liao compatible = "arm,idle-state"; 1859260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1869260918dSJames Liao local-timer-stop; 1879260918dSJames Liao entry-latency-us = <35>; 1889260918dSJames Liao exit-latency-us = <145>; 1899260918dSJames Liao min-residency-us = <720>; 1909260918dSJames Liao }; 1919260918dSJames Liao clusteroff_l: clusteroff_l { 1929260918dSJames Liao compatible = "arm,idle-state"; 1939260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 1949260918dSJames Liao local-timer-stop; 1959260918dSJames Liao entry-latency-us = <60>; 1969260918dSJames Liao exit-latency-us = <155>; 1979260918dSJames Liao min-residency-us = <860>; 1989260918dSJames Liao }; 1999260918dSJames Liao clusteroff_b: clusteroff_b { 2009260918dSJames Liao compatible = "arm,idle-state"; 2019260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2029260918dSJames Liao local-timer-stop; 2039260918dSJames Liao entry-latency-us = <40>; 2049260918dSJames Liao exit-latency-us = <155>; 2059260918dSJames Liao min-residency-us = <780>; 2069260918dSJames Liao }; 2079260918dSJames Liao }; 20848489980SSeiya Wang }; 20948489980SSeiya Wang 21048489980SSeiya Wang pmu-a55 { 21148489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 21248489980SSeiya Wang interrupt-parent = <&gic>; 21348489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 21448489980SSeiya Wang }; 21548489980SSeiya Wang 21648489980SSeiya Wang pmu-a76 { 21748489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 21848489980SSeiya Wang interrupt-parent = <&gic>; 21948489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 22048489980SSeiya Wang }; 22148489980SSeiya Wang 22248489980SSeiya Wang psci { 22348489980SSeiya Wang compatible = "arm,psci-1.0"; 22448489980SSeiya Wang method = "smc"; 22548489980SSeiya Wang }; 22648489980SSeiya Wang 22748489980SSeiya Wang timer: timer { 22848489980SSeiya Wang compatible = "arm,armv8-timer"; 22948489980SSeiya Wang interrupt-parent = <&gic>; 23048489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 23148489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 23248489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 23348489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 23448489980SSeiya Wang clock-frequency = <13000000>; 23548489980SSeiya Wang }; 23648489980SSeiya Wang 23748489980SSeiya Wang soc { 23848489980SSeiya Wang #address-cells = <2>; 23948489980SSeiya Wang #size-cells = <2>; 24048489980SSeiya Wang compatible = "simple-bus"; 24148489980SSeiya Wang ranges; 24248489980SSeiya Wang 24348489980SSeiya Wang gic: interrupt-controller@c000000 { 24448489980SSeiya Wang compatible = "arm,gic-v3"; 24548489980SSeiya Wang #interrupt-cells = <4>; 24648489980SSeiya Wang #redistributor-regions = <1>; 24748489980SSeiya Wang interrupt-parent = <&gic>; 24848489980SSeiya Wang interrupt-controller; 24948489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 25048489980SSeiya Wang <0 0x0c040000 0 0x200000>; 25148489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 25248489980SSeiya Wang 25348489980SSeiya Wang ppi-partitions { 25448489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 25548489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 25648489980SSeiya Wang }; 25748489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 25848489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 25948489980SSeiya Wang }; 26048489980SSeiya Wang }; 26148489980SSeiya Wang }; 26248489980SSeiya Wang 2635d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 2645d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 2655d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 2665d2b897bSChun-Jie Chen #clock-cells = <1>; 2675d2b897bSChun-Jie Chen }; 2685d2b897bSChun-Jie Chen 2695d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 2705d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 2715d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 2725d2b897bSChun-Jie Chen #clock-cells = <1>; 2735d2b897bSChun-Jie Chen }; 2745d2b897bSChun-Jie Chen 2755d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 2765d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 2775d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 2785d2b897bSChun-Jie Chen #clock-cells = <1>; 2795d2b897bSChun-Jie Chen }; 2805d2b897bSChun-Jie Chen 28148489980SSeiya Wang pio: pinctrl@10005000 { 28248489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 28348489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 28448489980SSeiya Wang <0 0x11c20000 0 0x1000>, 28548489980SSeiya Wang <0 0x11d10000 0 0x1000>, 28648489980SSeiya Wang <0 0x11d30000 0 0x1000>, 28748489980SSeiya Wang <0 0x11d40000 0 0x1000>, 28848489980SSeiya Wang <0 0x11e20000 0 0x1000>, 28948489980SSeiya Wang <0 0x11e70000 0 0x1000>, 29048489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 29148489980SSeiya Wang <0 0x11f20000 0 0x1000>, 29248489980SSeiya Wang <0 0x11f30000 0 0x1000>, 29348489980SSeiya Wang <0 0x1000b000 0 0x1000>; 29448489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 29548489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 29648489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 29748489980SSeiya Wang "iocfg_tl", "eint"; 29848489980SSeiya Wang gpio-controller; 29948489980SSeiya Wang #gpio-cells = <2>; 30048489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 30148489980SSeiya Wang interrupt-controller; 30248489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 30348489980SSeiya Wang #interrupt-cells = <2>; 30448489980SSeiya Wang }; 30548489980SSeiya Wang 306994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 307994a71a3SChun-Jie Chen compatible = "syscon", "simple-mfd"; 308994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 309994a71a3SChun-Jie Chen #power-domain-cells = <1>; 310994a71a3SChun-Jie Chen 311994a71a3SChun-Jie Chen /* System Power Manager */ 312994a71a3SChun-Jie Chen spm: power-controller { 313994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 314994a71a3SChun-Jie Chen #address-cells = <1>; 315994a71a3SChun-Jie Chen #size-cells = <0>; 316994a71a3SChun-Jie Chen #power-domain-cells = <1>; 317994a71a3SChun-Jie Chen 318994a71a3SChun-Jie Chen /* power domain of the SoC */ 319994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 320994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 321994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 322994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 323994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 324994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 325994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 326994a71a3SChun-Jie Chen #power-domain-cells = <0>; 327994a71a3SChun-Jie Chen }; 328994a71a3SChun-Jie Chen 329994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 330994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 331994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 332994a71a3SChun-Jie Chen clock-names = "conn"; 333994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 334994a71a3SChun-Jie Chen #power-domain-cells = <0>; 335994a71a3SChun-Jie Chen }; 336994a71a3SChun-Jie Chen 337994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG0 { 338994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 339994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 340994a71a3SChun-Jie Chen clock-names = "mfg"; 341994a71a3SChun-Jie Chen #address-cells = <1>; 342994a71a3SChun-Jie Chen #size-cells = <0>; 343994a71a3SChun-Jie Chen #power-domain-cells = <1>; 344994a71a3SChun-Jie Chen 345994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG1 { 346994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 347994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 348994a71a3SChun-Jie Chen #address-cells = <1>; 349994a71a3SChun-Jie Chen #size-cells = <0>; 350994a71a3SChun-Jie Chen #power-domain-cells = <1>; 351994a71a3SChun-Jie Chen 352994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 353994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 354994a71a3SChun-Jie Chen #power-domain-cells = <0>; 355994a71a3SChun-Jie Chen }; 356994a71a3SChun-Jie Chen 357994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 358994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 359994a71a3SChun-Jie Chen #power-domain-cells = <0>; 360994a71a3SChun-Jie Chen }; 361994a71a3SChun-Jie Chen 362994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 363994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 364994a71a3SChun-Jie Chen #power-domain-cells = <0>; 365994a71a3SChun-Jie Chen }; 366994a71a3SChun-Jie Chen 367994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 368994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 369994a71a3SChun-Jie Chen #power-domain-cells = <0>; 370994a71a3SChun-Jie Chen }; 371994a71a3SChun-Jie Chen 372994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 373994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 374994a71a3SChun-Jie Chen #power-domain-cells = <0>; 375994a71a3SChun-Jie Chen }; 376994a71a3SChun-Jie Chen }; 377994a71a3SChun-Jie Chen }; 378994a71a3SChun-Jie Chen 379994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 380994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 381994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 382994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 383994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 384994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 385994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 386994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 387994a71a3SChun-Jie Chen "disp-3"; 388994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 389994a71a3SChun-Jie Chen #address-cells = <1>; 390994a71a3SChun-Jie Chen #size-cells = <0>; 391994a71a3SChun-Jie Chen #power-domain-cells = <1>; 392994a71a3SChun-Jie Chen 393994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 394994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 395994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 396994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 397994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 398994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 399994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 400994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 401994a71a3SChun-Jie Chen "ipe-3"; 402994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 403994a71a3SChun-Jie Chen #power-domain-cells = <0>; 404994a71a3SChun-Jie Chen }; 405994a71a3SChun-Jie Chen 406994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 407994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 408994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 409994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 410994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 411994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 412994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 413994a71a3SChun-Jie Chen #power-domain-cells = <0>; 414994a71a3SChun-Jie Chen }; 415994a71a3SChun-Jie Chen 416994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 417994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 418994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 419994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 420994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 421994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 422994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 423994a71a3SChun-Jie Chen #power-domain-cells = <0>; 424994a71a3SChun-Jie Chen }; 425994a71a3SChun-Jie Chen 426994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 427994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 428994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 429994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 430994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 431994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 432994a71a3SChun-Jie Chen #power-domain-cells = <0>; 433994a71a3SChun-Jie Chen }; 434994a71a3SChun-Jie Chen 435994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 436994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 437994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 438994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 439994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 440994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 441994a71a3SChun-Jie Chen #power-domain-cells = <0>; 442994a71a3SChun-Jie Chen }; 443994a71a3SChun-Jie Chen 444994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 445994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 446994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 447994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 448994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 449994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 450994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 451994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 452994a71a3SChun-Jie Chen #address-cells = <1>; 453994a71a3SChun-Jie Chen #size-cells = <0>; 454994a71a3SChun-Jie Chen #power-domain-cells = <1>; 455994a71a3SChun-Jie Chen 456994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 457994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 458994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 459994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 460994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 461994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 462994a71a3SChun-Jie Chen "vdec2-2"; 463994a71a3SChun-Jie Chen #power-domain-cells = <0>; 464994a71a3SChun-Jie Chen }; 465994a71a3SChun-Jie Chen }; 466994a71a3SChun-Jie Chen 467994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 468994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 469994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 470994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 471994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 472994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 473994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 474994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 475994a71a3SChun-Jie Chen "cam-3"; 476994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 477994a71a3SChun-Jie Chen #address-cells = <1>; 478994a71a3SChun-Jie Chen #size-cells = <0>; 479994a71a3SChun-Jie Chen #power-domain-cells = <1>; 480994a71a3SChun-Jie Chen 481994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 482994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 483994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 484994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 485994a71a3SChun-Jie Chen #power-domain-cells = <0>; 486994a71a3SChun-Jie Chen }; 487994a71a3SChun-Jie Chen 488994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 489994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 490994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 491994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 492994a71a3SChun-Jie Chen #power-domain-cells = <0>; 493994a71a3SChun-Jie Chen }; 494994a71a3SChun-Jie Chen 495994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 496994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 497994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 498994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 499994a71a3SChun-Jie Chen #power-domain-cells = <0>; 500994a71a3SChun-Jie Chen }; 501994a71a3SChun-Jie Chen }; 502994a71a3SChun-Jie Chen }; 503994a71a3SChun-Jie Chen }; 504994a71a3SChun-Jie Chen }; 505994a71a3SChun-Jie Chen 506d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 507d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 508d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 509d1986fbdSAllen-KH Cheng #reset-cells = <1>; 510d1986fbdSAllen-KH Cheng }; 511d1986fbdSAllen-KH Cheng 5125d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 5135d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 5145d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 5155d2b897bSChun-Jie Chen #clock-cells = <1>; 5165d2b897bSChun-Jie Chen }; 5175d2b897bSChun-Jie Chen 51848489980SSeiya Wang systimer: timer@10017000 { 51948489980SSeiya Wang compatible = "mediatek,mt8192-timer", 52048489980SSeiya Wang "mediatek,mt6765-timer"; 52148489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 52248489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 523dde3c175SAllen-KH Cheng clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 52448489980SSeiya Wang clock-names = "clk13m"; 52548489980SSeiya Wang }; 52648489980SSeiya Wang 527261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 528261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 529261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 530261691b4SAllen-KH Cheng reg-names = "pwrap"; 531261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 532261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 533261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 534261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 535261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 536261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 537261691b4SAllen-KH Cheng }; 538261691b4SAllen-KH Cheng 5395d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 5405d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 5415d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 5425d2b897bSChun-Jie Chen #clock-cells = <1>; 5435d2b897bSChun-Jie Chen }; 5445d2b897bSChun-Jie Chen 54548489980SSeiya Wang uart0: serial@11002000 { 54648489980SSeiya Wang compatible = "mediatek,mt8192-uart", 54748489980SSeiya Wang "mediatek,mt6577-uart"; 54848489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 54948489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 55073ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 55148489980SSeiya Wang clock-names = "baud", "bus"; 55248489980SSeiya Wang status = "disabled"; 55348489980SSeiya Wang }; 55448489980SSeiya Wang 55548489980SSeiya Wang uart1: serial@11003000 { 55648489980SSeiya Wang compatible = "mediatek,mt8192-uart", 55748489980SSeiya Wang "mediatek,mt6577-uart"; 55848489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 55948489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 56073ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 56148489980SSeiya Wang clock-names = "baud", "bus"; 56248489980SSeiya Wang status = "disabled"; 56348489980SSeiya Wang }; 56448489980SSeiya Wang 5655d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 5665d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 5675d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 5685d2b897bSChun-Jie Chen #clock-cells = <1>; 5695d2b897bSChun-Jie Chen }; 5705d2b897bSChun-Jie Chen 57148489980SSeiya Wang spi0: spi@1100a000 { 57248489980SSeiya Wang compatible = "mediatek,mt8192-spi", 57348489980SSeiya Wang "mediatek,mt6765-spi"; 57448489980SSeiya Wang #address-cells = <1>; 57548489980SSeiya Wang #size-cells = <0>; 57648489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 57748489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 5787f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5797f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5807f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 58148489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 58248489980SSeiya Wang status = "disabled"; 58348489980SSeiya Wang }; 58448489980SSeiya Wang 58548489980SSeiya Wang spi1: spi@11010000 { 58648489980SSeiya Wang compatible = "mediatek,mt8192-spi", 58748489980SSeiya Wang "mediatek,mt6765-spi"; 58848489980SSeiya Wang #address-cells = <1>; 58948489980SSeiya Wang #size-cells = <0>; 59048489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 59148489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 5927f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5937f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5947f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 59548489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 59648489980SSeiya Wang status = "disabled"; 59748489980SSeiya Wang }; 59848489980SSeiya Wang 59948489980SSeiya Wang spi2: spi@11012000 { 60048489980SSeiya Wang compatible = "mediatek,mt8192-spi", 60148489980SSeiya Wang "mediatek,mt6765-spi"; 60248489980SSeiya Wang #address-cells = <1>; 60348489980SSeiya Wang #size-cells = <0>; 60448489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 60548489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 6067f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6077f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6087f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 60948489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 61048489980SSeiya Wang status = "disabled"; 61148489980SSeiya Wang }; 61248489980SSeiya Wang 61348489980SSeiya Wang spi3: spi@11013000 { 61448489980SSeiya Wang compatible = "mediatek,mt8192-spi", 61548489980SSeiya Wang "mediatek,mt6765-spi"; 61648489980SSeiya Wang #address-cells = <1>; 61748489980SSeiya Wang #size-cells = <0>; 61848489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 61948489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 6207f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6217f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6227f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 62348489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 62448489980SSeiya Wang status = "disabled"; 62548489980SSeiya Wang }; 62648489980SSeiya Wang 62748489980SSeiya Wang spi4: spi@11018000 { 62848489980SSeiya Wang compatible = "mediatek,mt8192-spi", 62948489980SSeiya Wang "mediatek,mt6765-spi"; 63048489980SSeiya Wang #address-cells = <1>; 63148489980SSeiya Wang #size-cells = <0>; 63248489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 63348489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 6347f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6357f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6367f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 63748489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 63848489980SSeiya Wang status = "disabled"; 63948489980SSeiya Wang }; 64048489980SSeiya Wang 64148489980SSeiya Wang spi5: spi@11019000 { 64248489980SSeiya Wang compatible = "mediatek,mt8192-spi", 64348489980SSeiya Wang "mediatek,mt6765-spi"; 64448489980SSeiya Wang #address-cells = <1>; 64548489980SSeiya Wang #size-cells = <0>; 64648489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 64748489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 6487f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6497f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6507f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 65148489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 65248489980SSeiya Wang status = "disabled"; 65348489980SSeiya Wang }; 65448489980SSeiya Wang 65548489980SSeiya Wang spi6: spi@1101d000 { 65648489980SSeiya Wang compatible = "mediatek,mt8192-spi", 65748489980SSeiya Wang "mediatek,mt6765-spi"; 65848489980SSeiya Wang #address-cells = <1>; 65948489980SSeiya Wang #size-cells = <0>; 66048489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 66148489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 6627f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6637f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6647f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 66548489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 66648489980SSeiya Wang status = "disabled"; 66748489980SSeiya Wang }; 66848489980SSeiya Wang 66948489980SSeiya Wang spi7: spi@1101e000 { 67048489980SSeiya Wang compatible = "mediatek,mt8192-spi", 67148489980SSeiya Wang "mediatek,mt6765-spi"; 67248489980SSeiya Wang #address-cells = <1>; 67348489980SSeiya Wang #size-cells = <0>; 67448489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 67548489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 6767f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6777f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6787f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 67948489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 68048489980SSeiya Wang status = "disabled"; 68148489980SSeiya Wang }; 68248489980SSeiya Wang 683c63556ecSAllen-KH Cheng scp: scp@10500000 { 684c63556ecSAllen-KH Cheng compatible = "mediatek,mt8192-scp"; 685c63556ecSAllen-KH Cheng reg = <0 0x10500000 0 0x100000>, 686c63556ecSAllen-KH Cheng <0 0x10700000 0 0x8000>, 687c63556ecSAllen-KH Cheng <0 0x10720000 0 0xe0000>; 688c63556ecSAllen-KH Cheng reg-names = "sram", "l1tcm", "cfg"; 689c63556ecSAllen-KH Cheng interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 690c63556ecSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SCPSYS>; 691c63556ecSAllen-KH Cheng clock-names = "main"; 692c63556ecSAllen-KH Cheng status = "disabled"; 693c63556ecSAllen-KH Cheng }; 694c63556ecSAllen-KH Cheng 695e5aac225SAllen-KH Cheng xhci: usb@11200000 { 696e5aac225SAllen-KH Cheng compatible = "mediatek,mt8192-xhci", 697e5aac225SAllen-KH Cheng "mediatek,mtk-xhci"; 698e5aac225SAllen-KH Cheng reg = <0 0x11200000 0 0x1000>, 699e5aac225SAllen-KH Cheng <0 0x11203e00 0 0x0100>; 700e5aac225SAllen-KH Cheng reg-names = "mac", "ippc"; 701e5aac225SAllen-KH Cheng interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 702e5aac225SAllen-KH Cheng interrupt-names = "host"; 703e5aac225SAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>, 704e5aac225SAllen-KH Cheng <&u3port0 PHY_TYPE_USB3>; 705e5aac225SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 706e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 707e5aac225SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 708e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 709e5aac225SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SSUSB>, 710e5aac225SAllen-KH Cheng <&infracfg CLK_INFRA_SSUSB_XHCI>, 711e5aac225SAllen-KH Cheng <&apmixedsys CLK_APMIXED_USBPLL>; 712e5aac225SAllen-KH Cheng clock-names = "sys_ck", "xhci_ck", "ref_ck"; 713e5aac225SAllen-KH Cheng wakeup-source; 714e5aac225SAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 102>; 715e5aac225SAllen-KH Cheng status = "disabled"; 716e5aac225SAllen-KH Cheng }; 717e5aac225SAllen-KH Cheng 718d0a197a0Sbayi cheng nor_flash: spi@11234000 { 719d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 720d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 721d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 722aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 723aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 724aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 725d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 726aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 727aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 728d0a197a0Sbayi cheng #address-cells = <1>; 729d0a197a0Sbayi cheng #size-cells = <0>; 73027f0eb16SAllen-KH Cheng status = "disabled"; 731d0a197a0Sbayi cheng }; 732d0a197a0Sbayi cheng 7335d2b897bSChun-Jie Chen audsys: clock-controller@11210000 { 7345d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-audsys", "syscon"; 7355d2b897bSChun-Jie Chen reg = <0 0x11210000 0 0x1000>; 7365d2b897bSChun-Jie Chen #clock-cells = <1>; 7375d2b897bSChun-Jie Chen }; 7385d2b897bSChun-Jie Chen 739*4d50a433SAllen-KH Cheng efuse: efuse@11c10000 { 740*4d50a433SAllen-KH Cheng compatible = "mediatek,efuse"; 741*4d50a433SAllen-KH Cheng reg = <0 0x11c10000 0 0x1000>; 742*4d50a433SAllen-KH Cheng #address-cells = <1>; 743*4d50a433SAllen-KH Cheng #size-cells = <1>; 744*4d50a433SAllen-KH Cheng 745*4d50a433SAllen-KH Cheng lvts_e_data1: data1@1c0 { 746*4d50a433SAllen-KH Cheng reg = <0x1c0 0x58>; 747*4d50a433SAllen-KH Cheng }; 748*4d50a433SAllen-KH Cheng 749*4d50a433SAllen-KH Cheng svs_calibration: calib@580 { 750*4d50a433SAllen-KH Cheng reg = <0x580 0x68>; 751*4d50a433SAllen-KH Cheng }; 752*4d50a433SAllen-KH Cheng }; 753*4d50a433SAllen-KH Cheng 7547f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 75548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 75648489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 75748489980SSeiya Wang <0 0x10217300 0 0x80>; 75848489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 75922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 76022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 76148489980SSeiya Wang clock-names = "main", "dma"; 76248489980SSeiya Wang clock-div = <1>; 76348489980SSeiya Wang #address-cells = <1>; 76448489980SSeiya Wang #size-cells = <0>; 76548489980SSeiya Wang status = "disabled"; 76648489980SSeiya Wang }; 76748489980SSeiya Wang 7685d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 7695d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 7705d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 7715d2b897bSChun-Jie Chen #clock-cells = <1>; 7725d2b897bSChun-Jie Chen }; 7735d2b897bSChun-Jie Chen 7747f1a9f47SFabien Parent i2c7: i2c@11d00000 { 77548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 77648489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 77748489980SSeiya Wang <0 0x10217600 0 0x180>; 77848489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 77922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 78022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 78148489980SSeiya Wang clock-names = "main", "dma"; 78248489980SSeiya Wang clock-div = <1>; 78348489980SSeiya Wang #address-cells = <1>; 78448489980SSeiya Wang #size-cells = <0>; 78548489980SSeiya Wang status = "disabled"; 78648489980SSeiya Wang }; 78748489980SSeiya Wang 7887f1a9f47SFabien Parent i2c8: i2c@11d01000 { 78948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 79048489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 79148489980SSeiya Wang <0 0x10217780 0 0x180>; 79248489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 79322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 79422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 79548489980SSeiya Wang clock-names = "main", "dma"; 79648489980SSeiya Wang clock-div = <1>; 79748489980SSeiya Wang #address-cells = <1>; 79848489980SSeiya Wang #size-cells = <0>; 79948489980SSeiya Wang status = "disabled"; 80048489980SSeiya Wang }; 80148489980SSeiya Wang 8027f1a9f47SFabien Parent i2c9: i2c@11d02000 { 80348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 80448489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 80548489980SSeiya Wang <0 0x10217900 0 0x180>; 80648489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 80722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 80822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 80948489980SSeiya Wang clock-names = "main", "dma"; 81048489980SSeiya Wang clock-div = <1>; 81148489980SSeiya Wang #address-cells = <1>; 81248489980SSeiya Wang #size-cells = <0>; 81348489980SSeiya Wang status = "disabled"; 81448489980SSeiya Wang }; 81548489980SSeiya Wang 8165d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 8175d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 8185d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 8195d2b897bSChun-Jie Chen #clock-cells = <1>; 8205d2b897bSChun-Jie Chen }; 8215d2b897bSChun-Jie Chen 8227f1a9f47SFabien Parent i2c1: i2c@11d20000 { 82348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 82448489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 82548489980SSeiya Wang <0 0x10217100 0 0x80>; 82648489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 82722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 82822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 82948489980SSeiya Wang clock-names = "main", "dma"; 83048489980SSeiya Wang clock-div = <1>; 83148489980SSeiya Wang #address-cells = <1>; 83248489980SSeiya Wang #size-cells = <0>; 83348489980SSeiya Wang status = "disabled"; 83448489980SSeiya Wang }; 83548489980SSeiya Wang 8367f1a9f47SFabien Parent i2c2: i2c@11d21000 { 83748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 83848489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 83948489980SSeiya Wang <0 0x10217180 0 0x180>; 84048489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 84122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 84222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 84348489980SSeiya Wang clock-names = "main", "dma"; 84448489980SSeiya Wang clock-div = <1>; 84548489980SSeiya Wang #address-cells = <1>; 84648489980SSeiya Wang #size-cells = <0>; 84748489980SSeiya Wang status = "disabled"; 84848489980SSeiya Wang }; 84948489980SSeiya Wang 8507f1a9f47SFabien Parent i2c4: i2c@11d22000 { 85148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 85248489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 85348489980SSeiya Wang <0 0x10217380 0 0x180>; 85448489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 85522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 85622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 85748489980SSeiya Wang clock-names = "main", "dma"; 85848489980SSeiya Wang clock-div = <1>; 85948489980SSeiya Wang #address-cells = <1>; 86048489980SSeiya Wang #size-cells = <0>; 86148489980SSeiya Wang status = "disabled"; 86248489980SSeiya Wang }; 86348489980SSeiya Wang 8645d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 8655d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 8665d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 8675d2b897bSChun-Jie Chen #clock-cells = <1>; 8685d2b897bSChun-Jie Chen }; 8695d2b897bSChun-Jie Chen 8707f1a9f47SFabien Parent i2c5: i2c@11e00000 { 87148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 87248489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 87348489980SSeiya Wang <0 0x10217500 0 0x80>; 87448489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 87522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 87622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 87748489980SSeiya Wang clock-names = "main", "dma"; 87848489980SSeiya Wang clock-div = <1>; 87948489980SSeiya Wang #address-cells = <1>; 88048489980SSeiya Wang #size-cells = <0>; 88148489980SSeiya Wang status = "disabled"; 88248489980SSeiya Wang }; 88348489980SSeiya Wang 8845d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 8855d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 8865d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 8875d2b897bSChun-Jie Chen #clock-cells = <1>; 8885d2b897bSChun-Jie Chen }; 8895d2b897bSChun-Jie Chen 89040de66b8SAllen-KH Cheng u3phy0: t-phy@11e40000 { 89140de66b8SAllen-KH Cheng compatible = "mediatek,mt8192-tphy", 89240de66b8SAllen-KH Cheng "mediatek,generic-tphy-v2"; 89340de66b8SAllen-KH Cheng #address-cells = <1>; 89440de66b8SAllen-KH Cheng #size-cells = <1>; 89540de66b8SAllen-KH Cheng ranges = <0x0 0x0 0x11e40000 0x1000>; 89640de66b8SAllen-KH Cheng 89740de66b8SAllen-KH Cheng u2port0: usb-phy@0 { 89840de66b8SAllen-KH Cheng reg = <0x0 0x700>; 89940de66b8SAllen-KH Cheng clocks = <&clk26m>; 90040de66b8SAllen-KH Cheng clock-names = "ref"; 90140de66b8SAllen-KH Cheng #phy-cells = <1>; 90240de66b8SAllen-KH Cheng }; 90340de66b8SAllen-KH Cheng 90440de66b8SAllen-KH Cheng u3port0: usb-phy@700 { 90540de66b8SAllen-KH Cheng reg = <0x700 0x900>; 90640de66b8SAllen-KH Cheng clocks = <&clk26m>; 90740de66b8SAllen-KH Cheng clock-names = "ref"; 90840de66b8SAllen-KH Cheng #phy-cells = <1>; 90940de66b8SAllen-KH Cheng }; 91040de66b8SAllen-KH Cheng }; 91140de66b8SAllen-KH Cheng 9127f1a9f47SFabien Parent i2c0: i2c@11f00000 { 91348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 91448489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 91548489980SSeiya Wang <0 0x10217080 0 0x80>; 91648489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 91722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 91822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 91948489980SSeiya Wang clock-names = "main", "dma"; 92048489980SSeiya Wang clock-div = <1>; 92148489980SSeiya Wang #address-cells = <1>; 92248489980SSeiya Wang #size-cells = <0>; 92348489980SSeiya Wang status = "disabled"; 92448489980SSeiya Wang }; 92548489980SSeiya Wang 9267f1a9f47SFabien Parent i2c6: i2c@11f01000 { 92748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 92848489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 92948489980SSeiya Wang <0 0x10217580 0 0x80>; 93048489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 93122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 93222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 93348489980SSeiya Wang clock-names = "main", "dma"; 93448489980SSeiya Wang clock-div = <1>; 93548489980SSeiya Wang #address-cells = <1>; 93648489980SSeiya Wang #size-cells = <0>; 93748489980SSeiya Wang status = "disabled"; 93848489980SSeiya Wang }; 9395d2b897bSChun-Jie Chen 9405d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 9415d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 9425d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 9435d2b897bSChun-Jie Chen #clock-cells = <1>; 9445d2b897bSChun-Jie Chen }; 9455d2b897bSChun-Jie Chen 9465d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 9475d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 9485d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 9495d2b897bSChun-Jie Chen #clock-cells = <1>; 9505d2b897bSChun-Jie Chen }; 9515d2b897bSChun-Jie Chen 9525d2b897bSChun-Jie Chen msdc: clock-controller@11f60000 { 9535d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc"; 9545d2b897bSChun-Jie Chen reg = <0 0x11f60000 0 0x1000>; 9555d2b897bSChun-Jie Chen #clock-cells = <1>; 9565d2b897bSChun-Jie Chen }; 9575d2b897bSChun-Jie Chen 9585d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 9595d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 9605d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 9615d2b897bSChun-Jie Chen #clock-cells = <1>; 9625d2b897bSChun-Jie Chen }; 9635d2b897bSChun-Jie Chen 9645d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 9655d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 9665d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 9675d2b897bSChun-Jie Chen #clock-cells = <1>; 9685d2b897bSChun-Jie Chen }; 9695d2b897bSChun-Jie Chen 9705d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 9715d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 9725d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 9735d2b897bSChun-Jie Chen #clock-cells = <1>; 9745d2b897bSChun-Jie Chen }; 9755d2b897bSChun-Jie Chen 9765d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 9775d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 9785d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 9795d2b897bSChun-Jie Chen #clock-cells = <1>; 9805d2b897bSChun-Jie Chen }; 9815d2b897bSChun-Jie Chen 9825d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 9835d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 9845d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 9855d2b897bSChun-Jie Chen #clock-cells = <1>; 9865d2b897bSChun-Jie Chen }; 9875d2b897bSChun-Jie Chen 9885d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 9895d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 9905d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 9915d2b897bSChun-Jie Chen #clock-cells = <1>; 9925d2b897bSChun-Jie Chen }; 9935d2b897bSChun-Jie Chen 9945d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 9955d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 9965d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 9975d2b897bSChun-Jie Chen #clock-cells = <1>; 9985d2b897bSChun-Jie Chen }; 9995d2b897bSChun-Jie Chen 10005d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 10015d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 10025d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 10035d2b897bSChun-Jie Chen #clock-cells = <1>; 10045d2b897bSChun-Jie Chen }; 10055d2b897bSChun-Jie Chen 10065d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 10075d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 10085d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 10095d2b897bSChun-Jie Chen #clock-cells = <1>; 10105d2b897bSChun-Jie Chen }; 10115d2b897bSChun-Jie Chen 10125d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 10135d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 10145d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 10155d2b897bSChun-Jie Chen #clock-cells = <1>; 10165d2b897bSChun-Jie Chen }; 10175d2b897bSChun-Jie Chen 10185d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 10195d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 10205d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 10215d2b897bSChun-Jie Chen #clock-cells = <1>; 10225d2b897bSChun-Jie Chen }; 10235d2b897bSChun-Jie Chen 10245d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 10255d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 10265d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 10275d2b897bSChun-Jie Chen #clock-cells = <1>; 10285d2b897bSChun-Jie Chen }; 10295d2b897bSChun-Jie Chen 10305d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 10315d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 10325d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 10335d2b897bSChun-Jie Chen #clock-cells = <1>; 10345d2b897bSChun-Jie Chen }; 103548489980SSeiya Wang }; 103648489980SSeiya Wang}; 1037