148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 9b4b75bacSAllen-KH Cheng#include <dt-bindings/gce/mt8192-gce.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1148489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 124a65b0f1SAllen-KH Cheng#include <dt-bindings/memory/mt8192-larb-port.h> 1348489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h> 15994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 167d355378SAllen-KH Cheng#include <dt-bindings/reset/mt8192-resets.h> 1748489980SSeiya Wang 1848489980SSeiya Wang/ { 1948489980SSeiya Wang compatible = "mediatek,mt8192"; 2048489980SSeiya Wang interrupt-parent = <&gic>; 2148489980SSeiya Wang #address-cells = <2>; 2248489980SSeiya Wang #size-cells = <2>; 2348489980SSeiya Wang 24b4b75bacSAllen-KH Cheng aliases { 25b4b75bacSAllen-KH Cheng ovl0 = &ovl0; 26b4b75bacSAllen-KH Cheng ovl-2l0 = &ovl_2l0; 27b4b75bacSAllen-KH Cheng ovl-2l2 = &ovl_2l2; 28b4b75bacSAllen-KH Cheng rdma0 = &rdma0; 29b4b75bacSAllen-KH Cheng rdma4 = &rdma4; 30b4b75bacSAllen-KH Cheng }; 31b4b75bacSAllen-KH Cheng 32f19f68e5SChen-Yu Tsai clk13m: fixed-factor-clock-13m { 33f19f68e5SChen-Yu Tsai compatible = "fixed-factor-clock"; 34f19f68e5SChen-Yu Tsai #clock-cells = <0>; 35f19f68e5SChen-Yu Tsai clocks = <&clk26m>; 36f19f68e5SChen-Yu Tsai clock-div = <2>; 37f19f68e5SChen-Yu Tsai clock-mult = <1>; 38f19f68e5SChen-Yu Tsai clock-output-names = "clk13m"; 39f19f68e5SChen-Yu Tsai }; 40f19f68e5SChen-Yu Tsai 4148489980SSeiya Wang clk26m: oscillator0 { 4248489980SSeiya Wang compatible = "fixed-clock"; 4348489980SSeiya Wang #clock-cells = <0>; 4448489980SSeiya Wang clock-frequency = <26000000>; 4548489980SSeiya Wang clock-output-names = "clk26m"; 4648489980SSeiya Wang }; 4748489980SSeiya Wang 4848489980SSeiya Wang clk32k: oscillator1 { 4948489980SSeiya Wang compatible = "fixed-clock"; 5048489980SSeiya Wang #clock-cells = <0>; 5148489980SSeiya Wang clock-frequency = <32768>; 5248489980SSeiya Wang clock-output-names = "clk32k"; 5348489980SSeiya Wang }; 5448489980SSeiya Wang 5548489980SSeiya Wang cpus { 5648489980SSeiya Wang #address-cells = <1>; 5748489980SSeiya Wang #size-cells = <0>; 5848489980SSeiya Wang 5948489980SSeiya Wang cpu0: cpu@0 { 6048489980SSeiya Wang device_type = "cpu"; 6148489980SSeiya Wang compatible = "arm,cortex-a55"; 6248489980SSeiya Wang reg = <0x000>; 6348489980SSeiya Wang enable-method = "psci"; 6448489980SSeiya Wang clock-frequency = <1701000000>; 65090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 6629288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 6729288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 6829288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 6929288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 7029288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 7129288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 7248489980SSeiya Wang next-level-cache = <&l2_0>; 7348489980SSeiya Wang capacity-dmips-mhz = <530>; 7448489980SSeiya Wang }; 7548489980SSeiya Wang 7648489980SSeiya Wang cpu1: cpu@100 { 7748489980SSeiya Wang device_type = "cpu"; 7848489980SSeiya Wang compatible = "arm,cortex-a55"; 7948489980SSeiya Wang reg = <0x100>; 8048489980SSeiya Wang enable-method = "psci"; 8148489980SSeiya Wang clock-frequency = <1701000000>; 82090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 8329288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 8429288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 8529288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 8629288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 8729288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 8829288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 8948489980SSeiya Wang next-level-cache = <&l2_0>; 9048489980SSeiya Wang capacity-dmips-mhz = <530>; 9148489980SSeiya Wang }; 9248489980SSeiya Wang 9348489980SSeiya Wang cpu2: cpu@200 { 9448489980SSeiya Wang device_type = "cpu"; 9548489980SSeiya Wang compatible = "arm,cortex-a55"; 9648489980SSeiya Wang reg = <0x200>; 9748489980SSeiya Wang enable-method = "psci"; 9848489980SSeiya Wang clock-frequency = <1701000000>; 99090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 10029288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 10129288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 10229288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 10329288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 10429288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 10529288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 10648489980SSeiya Wang next-level-cache = <&l2_0>; 10748489980SSeiya Wang capacity-dmips-mhz = <530>; 10848489980SSeiya Wang }; 10948489980SSeiya Wang 11048489980SSeiya Wang cpu3: cpu@300 { 11148489980SSeiya Wang device_type = "cpu"; 11248489980SSeiya Wang compatible = "arm,cortex-a55"; 11348489980SSeiya Wang reg = <0x300>; 11448489980SSeiya Wang enable-method = "psci"; 11548489980SSeiya Wang clock-frequency = <1701000000>; 116090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 11729288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 11829288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 11929288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 12029288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 12129288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 12229288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 12348489980SSeiya Wang next-level-cache = <&l2_0>; 12448489980SSeiya Wang capacity-dmips-mhz = <530>; 12548489980SSeiya Wang }; 12648489980SSeiya Wang 12748489980SSeiya Wang cpu4: cpu@400 { 12848489980SSeiya Wang device_type = "cpu"; 12948489980SSeiya Wang compatible = "arm,cortex-a76"; 13048489980SSeiya Wang reg = <0x400>; 13148489980SSeiya Wang enable-method = "psci"; 13248489980SSeiya Wang clock-frequency = <2171000000>; 133090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 13429288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 13529288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 13629288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 13729288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 13829288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 13929288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 14048489980SSeiya Wang next-level-cache = <&l2_1>; 14148489980SSeiya Wang capacity-dmips-mhz = <1024>; 14248489980SSeiya Wang }; 14348489980SSeiya Wang 14448489980SSeiya Wang cpu5: cpu@500 { 14548489980SSeiya Wang device_type = "cpu"; 14648489980SSeiya Wang compatible = "arm,cortex-a76"; 14748489980SSeiya Wang reg = <0x500>; 14848489980SSeiya Wang enable-method = "psci"; 14948489980SSeiya Wang clock-frequency = <2171000000>; 150090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 15129288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 15229288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 15329288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 15429288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 15529288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 15629288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 15748489980SSeiya Wang next-level-cache = <&l2_1>; 15848489980SSeiya Wang capacity-dmips-mhz = <1024>; 15948489980SSeiya Wang }; 16048489980SSeiya Wang 16148489980SSeiya Wang cpu6: cpu@600 { 16248489980SSeiya Wang device_type = "cpu"; 16348489980SSeiya Wang compatible = "arm,cortex-a76"; 16448489980SSeiya Wang reg = <0x600>; 16548489980SSeiya Wang enable-method = "psci"; 16648489980SSeiya Wang clock-frequency = <2171000000>; 167090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 16829288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 16929288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 17029288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 17129288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 17229288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 17329288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 17448489980SSeiya Wang next-level-cache = <&l2_1>; 17548489980SSeiya Wang capacity-dmips-mhz = <1024>; 17648489980SSeiya Wang }; 17748489980SSeiya Wang 17848489980SSeiya Wang cpu7: cpu@700 { 17948489980SSeiya Wang device_type = "cpu"; 18048489980SSeiya Wang compatible = "arm,cortex-a76"; 18148489980SSeiya Wang reg = <0x700>; 18248489980SSeiya Wang enable-method = "psci"; 18348489980SSeiya Wang clock-frequency = <2171000000>; 184090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 18529288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 18629288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 18729288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 18829288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 18929288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 19029288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 19148489980SSeiya Wang next-level-cache = <&l2_1>; 19248489980SSeiya Wang capacity-dmips-mhz = <1024>; 19348489980SSeiya Wang }; 19448489980SSeiya Wang 19548489980SSeiya Wang cpu-map { 19648489980SSeiya Wang cluster0 { 19748489980SSeiya Wang core0 { 19848489980SSeiya Wang cpu = <&cpu0>; 19948489980SSeiya Wang }; 20048489980SSeiya Wang core1 { 20148489980SSeiya Wang cpu = <&cpu1>; 20248489980SSeiya Wang }; 20348489980SSeiya Wang core2 { 20448489980SSeiya Wang cpu = <&cpu2>; 20548489980SSeiya Wang }; 20648489980SSeiya Wang core3 { 20748489980SSeiya Wang cpu = <&cpu3>; 20848489980SSeiya Wang }; 209160ce54dSAngeloGioacchino Del Regno core4 { 21048489980SSeiya Wang cpu = <&cpu4>; 21148489980SSeiya Wang }; 212160ce54dSAngeloGioacchino Del Regno core5 { 21348489980SSeiya Wang cpu = <&cpu5>; 21448489980SSeiya Wang }; 215160ce54dSAngeloGioacchino Del Regno core6 { 21648489980SSeiya Wang cpu = <&cpu6>; 21748489980SSeiya Wang }; 218160ce54dSAngeloGioacchino Del Regno core7 { 21948489980SSeiya Wang cpu = <&cpu7>; 22048489980SSeiya Wang }; 22148489980SSeiya Wang }; 22248489980SSeiya Wang }; 22348489980SSeiya Wang 22448489980SSeiya Wang l2_0: l2-cache0 { 22548489980SSeiya Wang compatible = "cache"; 226ce459b1dSPierre Gondois cache-level = <2>; 22729288babSAngeloGioacchino Del Regno cache-size = <131072>; 22829288babSAngeloGioacchino Del Regno cache-line-size = <64>; 22929288babSAngeloGioacchino Del Regno cache-sets = <512>; 23048489980SSeiya Wang next-level-cache = <&l3_0>; 231*492061bfSKrzysztof Kozlowski cache-unified; 23248489980SSeiya Wang }; 23348489980SSeiya Wang 23448489980SSeiya Wang l2_1: l2-cache1 { 23548489980SSeiya Wang compatible = "cache"; 236ce459b1dSPierre Gondois cache-level = <2>; 23729288babSAngeloGioacchino Del Regno cache-size = <262144>; 23829288babSAngeloGioacchino Del Regno cache-line-size = <64>; 23929288babSAngeloGioacchino Del Regno cache-sets = <512>; 24048489980SSeiya Wang next-level-cache = <&l3_0>; 241*492061bfSKrzysztof Kozlowski cache-unified; 24248489980SSeiya Wang }; 24348489980SSeiya Wang 24448489980SSeiya Wang l3_0: l3-cache { 24548489980SSeiya Wang compatible = "cache"; 246ce459b1dSPierre Gondois cache-level = <3>; 24729288babSAngeloGioacchino Del Regno cache-size = <2097152>; 24829288babSAngeloGioacchino Del Regno cache-line-size = <64>; 24929288babSAngeloGioacchino Del Regno cache-sets = <2048>; 25029288babSAngeloGioacchino Del Regno cache-unified; 25148489980SSeiya Wang }; 2529260918dSJames Liao 2539260918dSJames Liao idle-states { 2542e599740SNícolas F. R. A. Prado entry-method = "psci"; 255090bd20cSAngeloGioacchino Del Regno cpu_ret_l: cpu-retention-l { 2569260918dSJames Liao compatible = "arm,idle-state"; 2579260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 2589260918dSJames Liao local-timer-stop; 2599260918dSJames Liao entry-latency-us = <55>; 2609260918dSJames Liao exit-latency-us = <140>; 2619260918dSJames Liao min-residency-us = <780>; 2629260918dSJames Liao }; 263090bd20cSAngeloGioacchino Del Regno cpu_ret_b: cpu-retention-b { 2649260918dSJames Liao compatible = "arm,idle-state"; 2659260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 2669260918dSJames Liao local-timer-stop; 2679260918dSJames Liao entry-latency-us = <35>; 2689260918dSJames Liao exit-latency-us = <145>; 2699260918dSJames Liao min-residency-us = <720>; 2709260918dSJames Liao }; 271090bd20cSAngeloGioacchino Del Regno cpu_off_l: cpu-off-l { 2729260918dSJames Liao compatible = "arm,idle-state"; 2739260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2749260918dSJames Liao local-timer-stop; 2759260918dSJames Liao entry-latency-us = <60>; 2769260918dSJames Liao exit-latency-us = <155>; 2779260918dSJames Liao min-residency-us = <860>; 2789260918dSJames Liao }; 279090bd20cSAngeloGioacchino Del Regno cpu_off_b: cpu-off-b { 2809260918dSJames Liao compatible = "arm,idle-state"; 2819260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2829260918dSJames Liao local-timer-stop; 2839260918dSJames Liao entry-latency-us = <40>; 2849260918dSJames Liao exit-latency-us = <155>; 2859260918dSJames Liao min-residency-us = <780>; 2869260918dSJames Liao }; 2879260918dSJames Liao }; 28848489980SSeiya Wang }; 28948489980SSeiya Wang 29048489980SSeiya Wang pmu-a55 { 29148489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 29248489980SSeiya Wang interrupt-parent = <&gic>; 29348489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 29448489980SSeiya Wang }; 29548489980SSeiya Wang 29648489980SSeiya Wang pmu-a76 { 29748489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 29848489980SSeiya Wang interrupt-parent = <&gic>; 29948489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 30048489980SSeiya Wang }; 30148489980SSeiya Wang 30248489980SSeiya Wang psci { 30348489980SSeiya Wang compatible = "arm,psci-1.0"; 30448489980SSeiya Wang method = "smc"; 30548489980SSeiya Wang }; 30648489980SSeiya Wang 30748489980SSeiya Wang timer: timer { 30848489980SSeiya Wang compatible = "arm,armv8-timer"; 30948489980SSeiya Wang interrupt-parent = <&gic>; 31048489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 31148489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 31248489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 31348489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 31448489980SSeiya Wang clock-frequency = <13000000>; 31548489980SSeiya Wang }; 31648489980SSeiya Wang 317e1233345SAlyssa Rosenzweig gpu_opp_table: opp-table-0 { 318e1233345SAlyssa Rosenzweig compatible = "operating-points-v2"; 319e1233345SAlyssa Rosenzweig opp-shared; 320e1233345SAlyssa Rosenzweig 321e1233345SAlyssa Rosenzweig opp-358000000 { 322e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <358000000>; 323e1233345SAlyssa Rosenzweig opp-microvolt = <606250>; 324e1233345SAlyssa Rosenzweig }; 325e1233345SAlyssa Rosenzweig 326e1233345SAlyssa Rosenzweig opp-399000000 { 327e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <399000000>; 328e1233345SAlyssa Rosenzweig opp-microvolt = <618750>; 329e1233345SAlyssa Rosenzweig }; 330e1233345SAlyssa Rosenzweig 331e1233345SAlyssa Rosenzweig opp-440000000 { 332e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <440000000>; 333e1233345SAlyssa Rosenzweig opp-microvolt = <631250>; 334e1233345SAlyssa Rosenzweig }; 335e1233345SAlyssa Rosenzweig 336e1233345SAlyssa Rosenzweig opp-482000000 { 337e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <482000000>; 338e1233345SAlyssa Rosenzweig opp-microvolt = <643750>; 339e1233345SAlyssa Rosenzweig }; 340e1233345SAlyssa Rosenzweig 341e1233345SAlyssa Rosenzweig opp-523000000 { 342e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <523000000>; 343e1233345SAlyssa Rosenzweig opp-microvolt = <656250>; 344e1233345SAlyssa Rosenzweig }; 345e1233345SAlyssa Rosenzweig 346e1233345SAlyssa Rosenzweig opp-564000000 { 347e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <564000000>; 348e1233345SAlyssa Rosenzweig opp-microvolt = <668750>; 349e1233345SAlyssa Rosenzweig }; 350e1233345SAlyssa Rosenzweig 351e1233345SAlyssa Rosenzweig opp-605000000 { 352e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <605000000>; 353e1233345SAlyssa Rosenzweig opp-microvolt = <681250>; 354e1233345SAlyssa Rosenzweig }; 355e1233345SAlyssa Rosenzweig 356e1233345SAlyssa Rosenzweig opp-647000000 { 357e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <647000000>; 358e1233345SAlyssa Rosenzweig opp-microvolt = <693750>; 359e1233345SAlyssa Rosenzweig }; 360e1233345SAlyssa Rosenzweig 361e1233345SAlyssa Rosenzweig opp-688000000 { 362e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <688000000>; 363e1233345SAlyssa Rosenzweig opp-microvolt = <706250>; 364e1233345SAlyssa Rosenzweig }; 365e1233345SAlyssa Rosenzweig 366e1233345SAlyssa Rosenzweig opp-724000000 { 367e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <724000000>; 368e1233345SAlyssa Rosenzweig opp-microvolt = <725000>; 369e1233345SAlyssa Rosenzweig }; 370e1233345SAlyssa Rosenzweig 371e1233345SAlyssa Rosenzweig opp-748000000 { 372e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <748000000>; 373e1233345SAlyssa Rosenzweig opp-microvolt = <737500>; 374e1233345SAlyssa Rosenzweig }; 375e1233345SAlyssa Rosenzweig 376e1233345SAlyssa Rosenzweig opp-772000000 { 377e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <772000000>; 378e1233345SAlyssa Rosenzweig opp-microvolt = <750000>; 379e1233345SAlyssa Rosenzweig }; 380e1233345SAlyssa Rosenzweig 381e1233345SAlyssa Rosenzweig opp-795000000 { 382e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <795000000>; 383e1233345SAlyssa Rosenzweig opp-microvolt = <762500>; 384e1233345SAlyssa Rosenzweig }; 385e1233345SAlyssa Rosenzweig 386e1233345SAlyssa Rosenzweig opp-819000000 { 387e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <819000000>; 388e1233345SAlyssa Rosenzweig opp-microvolt = <775000>; 389e1233345SAlyssa Rosenzweig }; 390e1233345SAlyssa Rosenzweig 391e1233345SAlyssa Rosenzweig opp-843000000 { 392e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <843000000>; 393e1233345SAlyssa Rosenzweig opp-microvolt = <787500>; 394e1233345SAlyssa Rosenzweig }; 395e1233345SAlyssa Rosenzweig 396e1233345SAlyssa Rosenzweig opp-866000000 { 397e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <866000000>; 398e1233345SAlyssa Rosenzweig opp-microvolt = <800000>; 399e1233345SAlyssa Rosenzweig }; 400e1233345SAlyssa Rosenzweig }; 401e1233345SAlyssa Rosenzweig 40248489980SSeiya Wang soc { 40348489980SSeiya Wang #address-cells = <2>; 40448489980SSeiya Wang #size-cells = <2>; 40548489980SSeiya Wang compatible = "simple-bus"; 40648489980SSeiya Wang ranges; 40748489980SSeiya Wang 40848489980SSeiya Wang gic: interrupt-controller@c000000 { 40948489980SSeiya Wang compatible = "arm,gic-v3"; 41048489980SSeiya Wang #interrupt-cells = <4>; 41148489980SSeiya Wang #redistributor-regions = <1>; 41248489980SSeiya Wang interrupt-parent = <&gic>; 41348489980SSeiya Wang interrupt-controller; 41448489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 41548489980SSeiya Wang <0 0x0c040000 0 0x200000>; 41648489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 41748489980SSeiya Wang 41848489980SSeiya Wang ppi-partitions { 41948489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 42048489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 42148489980SSeiya Wang }; 42248489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 42348489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 42448489980SSeiya Wang }; 42548489980SSeiya Wang }; 42648489980SSeiya Wang }; 42748489980SSeiya Wang 4285d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 4295d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 4305d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 4315d2b897bSChun-Jie Chen #clock-cells = <1>; 4325d2b897bSChun-Jie Chen }; 4335d2b897bSChun-Jie Chen 4345d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 4355d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 4365d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 4375d2b897bSChun-Jie Chen #clock-cells = <1>; 438a30cc07fSRex-BC Chen #reset-cells = <1>; 4395d2b897bSChun-Jie Chen }; 4405d2b897bSChun-Jie Chen 4415d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 4425d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 4435d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 4445d2b897bSChun-Jie Chen #clock-cells = <1>; 4455d2b897bSChun-Jie Chen }; 4465d2b897bSChun-Jie Chen 44748489980SSeiya Wang pio: pinctrl@10005000 { 44848489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 44948489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 45048489980SSeiya Wang <0 0x11c20000 0 0x1000>, 45148489980SSeiya Wang <0 0x11d10000 0 0x1000>, 45248489980SSeiya Wang <0 0x11d30000 0 0x1000>, 45348489980SSeiya Wang <0 0x11d40000 0 0x1000>, 45448489980SSeiya Wang <0 0x11e20000 0 0x1000>, 45548489980SSeiya Wang <0 0x11e70000 0 0x1000>, 45648489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 45748489980SSeiya Wang <0 0x11f20000 0 0x1000>, 45848489980SSeiya Wang <0 0x11f30000 0 0x1000>, 45948489980SSeiya Wang <0 0x1000b000 0 0x1000>; 46048489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 46148489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 46248489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 46348489980SSeiya Wang "iocfg_tl", "eint"; 46448489980SSeiya Wang gpio-controller; 46548489980SSeiya Wang #gpio-cells = <2>; 46648489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 46748489980SSeiya Wang interrupt-controller; 46848489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 46948489980SSeiya Wang #interrupt-cells = <2>; 47048489980SSeiya Wang }; 47148489980SSeiya Wang 472994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 473d3dfd468STinghan Shen compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 474994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 475994a71a3SChun-Jie Chen 476994a71a3SChun-Jie Chen /* System Power Manager */ 477994a71a3SChun-Jie Chen spm: power-controller { 478994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 479994a71a3SChun-Jie Chen #address-cells = <1>; 480994a71a3SChun-Jie Chen #size-cells = <0>; 481994a71a3SChun-Jie Chen #power-domain-cells = <1>; 482994a71a3SChun-Jie Chen 483994a71a3SChun-Jie Chen /* power domain of the SoC */ 484994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 485994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 486994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 487994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 488994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 489994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 490994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 491994a71a3SChun-Jie Chen #power-domain-cells = <0>; 492994a71a3SChun-Jie Chen }; 493994a71a3SChun-Jie Chen 494994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 495994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 496994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 497994a71a3SChun-Jie Chen clock-names = "conn"; 498994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 499994a71a3SChun-Jie Chen #power-domain-cells = <0>; 500994a71a3SChun-Jie Chen }; 501994a71a3SChun-Jie Chen 5026fe90cc5SNícolas F. R. A. Prado mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { 503994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 50461348fe9SAngeloGioacchino Del Regno clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, 50561348fe9SAngeloGioacchino Del Regno <&topckgen CLK_TOP_MFG_REF_SEL>; 50661348fe9SAngeloGioacchino Del Regno clock-names = "mfg", "alt"; 507994a71a3SChun-Jie Chen #address-cells = <1>; 508994a71a3SChun-Jie Chen #size-cells = <0>; 509994a71a3SChun-Jie Chen #power-domain-cells = <1>; 510994a71a3SChun-Jie Chen 5113daabcb2SAngeloGioacchino Del Regno mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 { 512994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 513994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 514994a71a3SChun-Jie Chen #address-cells = <1>; 515994a71a3SChun-Jie Chen #size-cells = <0>; 516994a71a3SChun-Jie Chen #power-domain-cells = <1>; 517994a71a3SChun-Jie Chen 518994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 519994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 520994a71a3SChun-Jie Chen #power-domain-cells = <0>; 521994a71a3SChun-Jie Chen }; 522994a71a3SChun-Jie Chen 523994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 524994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 525994a71a3SChun-Jie Chen #power-domain-cells = <0>; 526994a71a3SChun-Jie Chen }; 527994a71a3SChun-Jie Chen 528994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 529994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 530994a71a3SChun-Jie Chen #power-domain-cells = <0>; 531994a71a3SChun-Jie Chen }; 532994a71a3SChun-Jie Chen 533994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 534994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 535994a71a3SChun-Jie Chen #power-domain-cells = <0>; 536994a71a3SChun-Jie Chen }; 537994a71a3SChun-Jie Chen 538994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 539994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 540994a71a3SChun-Jie Chen #power-domain-cells = <0>; 541994a71a3SChun-Jie Chen }; 542994a71a3SChun-Jie Chen }; 543994a71a3SChun-Jie Chen }; 544994a71a3SChun-Jie Chen 545994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 546994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 547994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 548994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 549994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 550994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 551994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 552994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 553994a71a3SChun-Jie Chen "disp-3"; 554994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 555994a71a3SChun-Jie Chen #address-cells = <1>; 556994a71a3SChun-Jie Chen #size-cells = <0>; 557994a71a3SChun-Jie Chen #power-domain-cells = <1>; 558994a71a3SChun-Jie Chen 559994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 560994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 561994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 562994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 563994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 564994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 565994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 566994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 567994a71a3SChun-Jie Chen "ipe-3"; 568994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 569994a71a3SChun-Jie Chen #power-domain-cells = <0>; 570994a71a3SChun-Jie Chen }; 571994a71a3SChun-Jie Chen 572994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 573994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 574994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 575994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 576994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 577994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 578994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 579994a71a3SChun-Jie Chen #power-domain-cells = <0>; 580994a71a3SChun-Jie Chen }; 581994a71a3SChun-Jie Chen 582994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 583994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 584994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 585994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 586994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 587994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 588994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 589994a71a3SChun-Jie Chen #power-domain-cells = <0>; 590994a71a3SChun-Jie Chen }; 591994a71a3SChun-Jie Chen 592994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 593994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 594994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 595994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 596994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 597994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 598994a71a3SChun-Jie Chen #power-domain-cells = <0>; 599994a71a3SChun-Jie Chen }; 600994a71a3SChun-Jie Chen 601994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 602994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 603994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 604994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 605994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 606994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 607994a71a3SChun-Jie Chen #power-domain-cells = <0>; 608994a71a3SChun-Jie Chen }; 609994a71a3SChun-Jie Chen 610994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 611994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 612994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 613994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 614994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 615994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 616994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 617994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 618994a71a3SChun-Jie Chen #address-cells = <1>; 619994a71a3SChun-Jie Chen #size-cells = <0>; 620994a71a3SChun-Jie Chen #power-domain-cells = <1>; 621994a71a3SChun-Jie Chen 622994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 623994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 624994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 625994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 626994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 627994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 628994a71a3SChun-Jie Chen "vdec2-2"; 629994a71a3SChun-Jie Chen #power-domain-cells = <0>; 630994a71a3SChun-Jie Chen }; 631994a71a3SChun-Jie Chen }; 632994a71a3SChun-Jie Chen 633994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 634994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 635994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 636994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 637994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 638994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 639994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 640994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 641994a71a3SChun-Jie Chen "cam-3"; 642994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 643994a71a3SChun-Jie Chen #address-cells = <1>; 644994a71a3SChun-Jie Chen #size-cells = <0>; 645994a71a3SChun-Jie Chen #power-domain-cells = <1>; 646994a71a3SChun-Jie Chen 647994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 648994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 649994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 650994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 651994a71a3SChun-Jie Chen #power-domain-cells = <0>; 652994a71a3SChun-Jie Chen }; 653994a71a3SChun-Jie Chen 654994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 655994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 656994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 657994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 658994a71a3SChun-Jie Chen #power-domain-cells = <0>; 659994a71a3SChun-Jie Chen }; 660994a71a3SChun-Jie Chen 661994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 662994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 663994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 664994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 665994a71a3SChun-Jie Chen #power-domain-cells = <0>; 666994a71a3SChun-Jie Chen }; 667994a71a3SChun-Jie Chen }; 668994a71a3SChun-Jie Chen }; 669994a71a3SChun-Jie Chen }; 670994a71a3SChun-Jie Chen }; 671994a71a3SChun-Jie Chen 672d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 673d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 674d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 675d1986fbdSAllen-KH Cheng #reset-cells = <1>; 676d1986fbdSAllen-KH Cheng }; 677d1986fbdSAllen-KH Cheng 6785d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 6795d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 6805d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 6815d2b897bSChun-Jie Chen #clock-cells = <1>; 6825d2b897bSChun-Jie Chen }; 6835d2b897bSChun-Jie Chen 68448489980SSeiya Wang systimer: timer@10017000 { 68548489980SSeiya Wang compatible = "mediatek,mt8192-timer", 68648489980SSeiya Wang "mediatek,mt6765-timer"; 68748489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 68848489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 689f19f68e5SChen-Yu Tsai clocks = <&clk13m>; 69048489980SSeiya Wang }; 69148489980SSeiya Wang 692261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 693261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 694261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 695261691b4SAllen-KH Cheng reg-names = "pwrap"; 696261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 697261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 698261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 699261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 700261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 701261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 702261691b4SAllen-KH Cheng }; 703261691b4SAllen-KH Cheng 704a8bbcf70SAllen-KH Cheng spmi: spmi@10027000 { 705a8bbcf70SAllen-KH Cheng compatible = "mediatek,mt6873-spmi"; 706a8bbcf70SAllen-KH Cheng reg = <0 0x10027000 0 0x000e00>, 707a8bbcf70SAllen-KH Cheng <0 0x10029000 0 0x000100>; 708a8bbcf70SAllen-KH Cheng reg-names = "pmif", "spmimst"; 709a8bbcf70SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 710a8bbcf70SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>, 711a8bbcf70SAllen-KH Cheng <&topckgen CLK_TOP_SPMI_MST_SEL>; 712a8bbcf70SAllen-KH Cheng clock-names = "pmif_sys_ck", 713a8bbcf70SAllen-KH Cheng "pmif_tmr_ck", 714a8bbcf70SAllen-KH Cheng "spmimst_clk_mux"; 715a8bbcf70SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 716a8bbcf70SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 717a8bbcf70SAllen-KH Cheng }; 718a8bbcf70SAllen-KH Cheng 719b4b75bacSAllen-KH Cheng gce: mailbox@10228000 { 720b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-gce"; 721b4b75bacSAllen-KH Cheng reg = <0 0x10228000 0 0x4000>; 722b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 723b4b75bacSAllen-KH Cheng #mbox-cells = <2>; 724b4b75bacSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_GCE>; 725b4b75bacSAllen-KH Cheng clock-names = "gce"; 726b4b75bacSAllen-KH Cheng }; 727b4b75bacSAllen-KH Cheng 7285d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 7295d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 7305d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 7315d2b897bSChun-Jie Chen #clock-cells = <1>; 732089cd717SChen-Yu Tsai /* power domain dependency not upstreamed */ 733089cd717SChen-Yu Tsai status = "fail"; 7345d2b897bSChun-Jie Chen }; 7355d2b897bSChun-Jie Chen 73648489980SSeiya Wang uart0: serial@11002000 { 73748489980SSeiya Wang compatible = "mediatek,mt8192-uart", 73848489980SSeiya Wang "mediatek,mt6577-uart"; 73948489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 74048489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 74173ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 74248489980SSeiya Wang clock-names = "baud", "bus"; 74348489980SSeiya Wang status = "disabled"; 74448489980SSeiya Wang }; 74548489980SSeiya Wang 74648489980SSeiya Wang uart1: serial@11003000 { 74748489980SSeiya Wang compatible = "mediatek,mt8192-uart", 74848489980SSeiya Wang "mediatek,mt6577-uart"; 74948489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 75048489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 75173ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 75248489980SSeiya Wang clock-names = "baud", "bus"; 75348489980SSeiya Wang status = "disabled"; 75448489980SSeiya Wang }; 75548489980SSeiya Wang 7565d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 7575d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 7585d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 7595d2b897bSChun-Jie Chen #clock-cells = <1>; 7605d2b897bSChun-Jie Chen }; 7615d2b897bSChun-Jie Chen 76248489980SSeiya Wang spi0: spi@1100a000 { 76348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 76448489980SSeiya Wang "mediatek,mt6765-spi"; 76548489980SSeiya Wang #address-cells = <1>; 76648489980SSeiya Wang #size-cells = <0>; 76748489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 76848489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 7697f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7707f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7717f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 77248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 77348489980SSeiya Wang status = "disabled"; 77448489980SSeiya Wang }; 77548489980SSeiya Wang 77618222e05SAllen-KH Cheng pwm0: pwm@1100e000 { 77718222e05SAllen-KH Cheng compatible = "mediatek,mt8183-disp-pwm"; 77818222e05SAllen-KH Cheng reg = <0 0x1100e000 0 0x1000>; 77918222e05SAllen-KH Cheng interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 78018222e05SAllen-KH Cheng #pwm-cells = <2>; 78118222e05SAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 78218222e05SAllen-KH Cheng <&infracfg CLK_INFRA_DISP_PWM>; 78318222e05SAllen-KH Cheng clock-names = "main", "mm"; 78418222e05SAllen-KH Cheng status = "disabled"; 78518222e05SAllen-KH Cheng }; 78618222e05SAllen-KH Cheng 78748489980SSeiya Wang spi1: spi@11010000 { 78848489980SSeiya Wang compatible = "mediatek,mt8192-spi", 78948489980SSeiya Wang "mediatek,mt6765-spi"; 79048489980SSeiya Wang #address-cells = <1>; 79148489980SSeiya Wang #size-cells = <0>; 79248489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 79348489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 7947f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7957f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7967f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 79748489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 79848489980SSeiya Wang status = "disabled"; 79948489980SSeiya Wang }; 80048489980SSeiya Wang 80148489980SSeiya Wang spi2: spi@11012000 { 80248489980SSeiya Wang compatible = "mediatek,mt8192-spi", 80348489980SSeiya Wang "mediatek,mt6765-spi"; 80448489980SSeiya Wang #address-cells = <1>; 80548489980SSeiya Wang #size-cells = <0>; 80648489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 80748489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 8087f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8097f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8107f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 81148489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 81248489980SSeiya Wang status = "disabled"; 81348489980SSeiya Wang }; 81448489980SSeiya Wang 81548489980SSeiya Wang spi3: spi@11013000 { 81648489980SSeiya Wang compatible = "mediatek,mt8192-spi", 81748489980SSeiya Wang "mediatek,mt6765-spi"; 81848489980SSeiya Wang #address-cells = <1>; 81948489980SSeiya Wang #size-cells = <0>; 82048489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 82148489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 8227f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8237f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8247f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 82548489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 82648489980SSeiya Wang status = "disabled"; 82748489980SSeiya Wang }; 82848489980SSeiya Wang 82948489980SSeiya Wang spi4: spi@11018000 { 83048489980SSeiya Wang compatible = "mediatek,mt8192-spi", 83148489980SSeiya Wang "mediatek,mt6765-spi"; 83248489980SSeiya Wang #address-cells = <1>; 83348489980SSeiya Wang #size-cells = <0>; 83448489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 83548489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 8367f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8377f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8387f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 83948489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 84048489980SSeiya Wang status = "disabled"; 84148489980SSeiya Wang }; 84248489980SSeiya Wang 84348489980SSeiya Wang spi5: spi@11019000 { 84448489980SSeiya Wang compatible = "mediatek,mt8192-spi", 84548489980SSeiya Wang "mediatek,mt6765-spi"; 84648489980SSeiya Wang #address-cells = <1>; 84748489980SSeiya Wang #size-cells = <0>; 84848489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 84948489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 8507f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8517f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8527f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 85348489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 85448489980SSeiya Wang status = "disabled"; 85548489980SSeiya Wang }; 85648489980SSeiya Wang 85748489980SSeiya Wang spi6: spi@1101d000 { 85848489980SSeiya Wang compatible = "mediatek,mt8192-spi", 85948489980SSeiya Wang "mediatek,mt6765-spi"; 86048489980SSeiya Wang #address-cells = <1>; 86148489980SSeiya Wang #size-cells = <0>; 86248489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 86348489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 8647f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8657f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8667f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 86748489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 86848489980SSeiya Wang status = "disabled"; 86948489980SSeiya Wang }; 87048489980SSeiya Wang 87148489980SSeiya Wang spi7: spi@1101e000 { 87248489980SSeiya Wang compatible = "mediatek,mt8192-spi", 87348489980SSeiya Wang "mediatek,mt6765-spi"; 87448489980SSeiya Wang #address-cells = <1>; 87548489980SSeiya Wang #size-cells = <0>; 87648489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 87748489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 8787f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8797f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8807f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 88148489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 88248489980SSeiya Wang status = "disabled"; 88348489980SSeiya Wang }; 88448489980SSeiya Wang 885c63556ecSAllen-KH Cheng scp: scp@10500000 { 886c63556ecSAllen-KH Cheng compatible = "mediatek,mt8192-scp"; 887c63556ecSAllen-KH Cheng reg = <0 0x10500000 0 0x100000>, 888c7510476SNícolas F. R. A. Prado <0 0x10720000 0 0xe0000>, 889c7510476SNícolas F. R. A. Prado <0 0x10700000 0 0x8000>; 890c7510476SNícolas F. R. A. Prado reg-names = "sram", "cfg", "l1tcm"; 891c63556ecSAllen-KH Cheng interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 892c63556ecSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SCPSYS>; 893c63556ecSAllen-KH Cheng clock-names = "main"; 894c63556ecSAllen-KH Cheng status = "disabled"; 895c63556ecSAllen-KH Cheng }; 896c63556ecSAllen-KH Cheng 897e5aac225SAllen-KH Cheng xhci: usb@11200000 { 898e5aac225SAllen-KH Cheng compatible = "mediatek,mt8192-xhci", 899e5aac225SAllen-KH Cheng "mediatek,mtk-xhci"; 900e5aac225SAllen-KH Cheng reg = <0 0x11200000 0 0x1000>, 901e5aac225SAllen-KH Cheng <0 0x11203e00 0 0x0100>; 902e5aac225SAllen-KH Cheng reg-names = "mac", "ippc"; 903e5aac225SAllen-KH Cheng interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 904e5aac225SAllen-KH Cheng interrupt-names = "host"; 905e5aac225SAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>, 906e5aac225SAllen-KH Cheng <&u3port0 PHY_TYPE_USB3>; 907e5aac225SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 908e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 909e5aac225SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 910e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 911e5aac225SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SSUSB>, 9126210fc2eSNícolas F. R. A. Prado <&apmixedsys CLK_APMIXED_USBPLL>, 9136210fc2eSNícolas F. R. A. Prado <&clk26m>, 9146210fc2eSNícolas F. R. A. Prado <&clk26m>, 9156210fc2eSNícolas F. R. A. Prado <&infracfg CLK_INFRA_SSUSB_XHCI>; 9166210fc2eSNícolas F. R. A. Prado clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 9176210fc2eSNícolas F. R. A. Prado "xhci_ck"; 918e5aac225SAllen-KH Cheng wakeup-source; 919e5aac225SAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 102>; 920e5aac225SAllen-KH Cheng status = "disabled"; 921e5aac225SAllen-KH Cheng }; 922e5aac225SAllen-KH Cheng 9231afd9b62SAllen-KH Cheng audsys: syscon@11210000 { 9241afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audsys", "syscon"; 9251afd9b62SAllen-KH Cheng reg = <0 0x11210000 0 0x2000>; 9261afd9b62SAllen-KH Cheng #clock-cells = <1>; 9271afd9b62SAllen-KH Cheng 9281afd9b62SAllen-KH Cheng afe: mt8192-afe-pcm { 9291afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audio"; 9301afd9b62SAllen-KH Cheng interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 9311afd9b62SAllen-KH Cheng resets = <&watchdog 17>; 9321afd9b62SAllen-KH Cheng reset-names = "audiosys"; 9331afd9b62SAllen-KH Cheng mediatek,apmixedsys = <&apmixedsys>; 9341afd9b62SAllen-KH Cheng mediatek,infracfg = <&infracfg>; 9351afd9b62SAllen-KH Cheng mediatek,topckgen = <&topckgen>; 9361afd9b62SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 9371afd9b62SAllen-KH Cheng clocks = <&audsys CLK_AUD_AFE>, 9381afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC>, 9391afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_PREDIS>, 9401afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC>, 9411afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC>, 9421afd9b62SAllen-KH Cheng <&audsys CLK_AUD_22M>, 9431afd9b62SAllen-KH Cheng <&audsys CLK_AUD_24M>, 9441afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL_TUNER>, 9451afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL2_TUNER>, 9461afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TDM>, 9471afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TML>, 9481afd9b62SAllen-KH Cheng <&audsys CLK_AUD_NLE>, 9491afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_HIRES>, 9501afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES>, 9511afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES_TML>, 9521afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 9531afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC>, 9541afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_PREDIS>, 9551afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_TML>, 9561afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_HIRES>, 9571afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO>, 9581afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO_26M_B>, 9591afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_SEL>, 9601afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 9611afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D4_D4>, 9621afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_1_SEL>, 9631afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1>, 9641afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_2_SEL>, 9651afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2>, 9661afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 9671afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1_D4>, 9681afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 9691afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2_D4>, 9701afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 9711afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 9721afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 9731afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 9741afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 9751afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 9761afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 9771afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 9781afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 9791afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 9801afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV0>, 9811afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV1>, 9821afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV2>, 9831afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV3>, 9841afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV4>, 9851afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIVB>, 9861afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV5>, 9871afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV6>, 9881afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV7>, 9891afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV8>, 9901afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV9>, 9911afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_H_SEL>, 9921afd9b62SAllen-KH Cheng <&clk26m>; 9931afd9b62SAllen-KH Cheng clock-names = "aud_afe_clk", 9941afd9b62SAllen-KH Cheng "aud_dac_clk", 9951afd9b62SAllen-KH Cheng "aud_dac_predis_clk", 9961afd9b62SAllen-KH Cheng "aud_adc_clk", 9971afd9b62SAllen-KH Cheng "aud_adda6_adc_clk", 9981afd9b62SAllen-KH Cheng "aud_apll22m_clk", 9991afd9b62SAllen-KH Cheng "aud_apll24m_clk", 10001afd9b62SAllen-KH Cheng "aud_apll1_tuner_clk", 10011afd9b62SAllen-KH Cheng "aud_apll2_tuner_clk", 10021afd9b62SAllen-KH Cheng "aud_tdm_clk", 10031afd9b62SAllen-KH Cheng "aud_tml_clk", 10041afd9b62SAllen-KH Cheng "aud_nle", 10051afd9b62SAllen-KH Cheng "aud_dac_hires_clk", 10061afd9b62SAllen-KH Cheng "aud_adc_hires_clk", 10071afd9b62SAllen-KH Cheng "aud_adc_hires_tml", 10081afd9b62SAllen-KH Cheng "aud_adda6_adc_hires_clk", 10091afd9b62SAllen-KH Cheng "aud_3rd_dac_clk", 10101afd9b62SAllen-KH Cheng "aud_3rd_dac_predis_clk", 10111afd9b62SAllen-KH Cheng "aud_3rd_dac_tml", 10121afd9b62SAllen-KH Cheng "aud_3rd_dac_hires_clk", 10131afd9b62SAllen-KH Cheng "aud_infra_clk", 10141afd9b62SAllen-KH Cheng "aud_infra_26m_clk", 10151afd9b62SAllen-KH Cheng "top_mux_audio", 10161afd9b62SAllen-KH Cheng "top_mux_audio_int", 10171afd9b62SAllen-KH Cheng "top_mainpll_d4_d4", 10181afd9b62SAllen-KH Cheng "top_mux_aud_1", 10191afd9b62SAllen-KH Cheng "top_apll1_ck", 10201afd9b62SAllen-KH Cheng "top_mux_aud_2", 10211afd9b62SAllen-KH Cheng "top_apll2_ck", 10221afd9b62SAllen-KH Cheng "top_mux_aud_eng1", 10231afd9b62SAllen-KH Cheng "top_apll1_d4", 10241afd9b62SAllen-KH Cheng "top_mux_aud_eng2", 10251afd9b62SAllen-KH Cheng "top_apll2_d4", 10261afd9b62SAllen-KH Cheng "top_i2s0_m_sel", 10271afd9b62SAllen-KH Cheng "top_i2s1_m_sel", 10281afd9b62SAllen-KH Cheng "top_i2s2_m_sel", 10291afd9b62SAllen-KH Cheng "top_i2s3_m_sel", 10301afd9b62SAllen-KH Cheng "top_i2s4_m_sel", 10311afd9b62SAllen-KH Cheng "top_i2s5_m_sel", 10321afd9b62SAllen-KH Cheng "top_i2s6_m_sel", 10331afd9b62SAllen-KH Cheng "top_i2s7_m_sel", 10341afd9b62SAllen-KH Cheng "top_i2s8_m_sel", 10351afd9b62SAllen-KH Cheng "top_i2s9_m_sel", 10361afd9b62SAllen-KH Cheng "top_apll12_div0", 10371afd9b62SAllen-KH Cheng "top_apll12_div1", 10381afd9b62SAllen-KH Cheng "top_apll12_div2", 10391afd9b62SAllen-KH Cheng "top_apll12_div3", 10401afd9b62SAllen-KH Cheng "top_apll12_div4", 10411afd9b62SAllen-KH Cheng "top_apll12_divb", 10421afd9b62SAllen-KH Cheng "top_apll12_div5", 10431afd9b62SAllen-KH Cheng "top_apll12_div6", 10441afd9b62SAllen-KH Cheng "top_apll12_div7", 10451afd9b62SAllen-KH Cheng "top_apll12_div8", 10461afd9b62SAllen-KH Cheng "top_apll12_div9", 10471afd9b62SAllen-KH Cheng "top_mux_audio_h", 10481afd9b62SAllen-KH Cheng "top_clk26m_clk"; 10491afd9b62SAllen-KH Cheng }; 10501afd9b62SAllen-KH Cheng }; 10511afd9b62SAllen-KH Cheng 1052e530d080SAllen-KH Cheng pcie: pcie@11230000 { 1053e530d080SAllen-KH Cheng compatible = "mediatek,mt8192-pcie"; 1054e530d080SAllen-KH Cheng device_type = "pci"; 1055e530d080SAllen-KH Cheng reg = <0 0x11230000 0 0x2000>; 1056e530d080SAllen-KH Cheng reg-names = "pcie-mac"; 1057e530d080SAllen-KH Cheng #address-cells = <3>; 1058e530d080SAllen-KH Cheng #size-cells = <2>; 1059e530d080SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 1060e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_26M>, 1061e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_96M>, 1062e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_32K>, 1063e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_PERI_26M>, 1064e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 1065e530d080SAllen-KH Cheng clock-names = "pl_250m", "tl_26m", "tl_96m", 1066e530d080SAllen-KH Cheng "tl_32k", "peri_26m", "top_133m"; 1067e530d080SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 1068e530d080SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 1069e530d080SAllen-KH Cheng interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 1070e530d080SAllen-KH Cheng bus-range = <0x00 0xff>; 1071e530d080SAllen-KH Cheng ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 1072e530d080SAllen-KH Cheng <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 1073e530d080SAllen-KH Cheng #interrupt-cells = <1>; 1074e530d080SAllen-KH Cheng interrupt-map-mask = <0 0 0 7>; 1075e530d080SAllen-KH Cheng interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1076e530d080SAllen-KH Cheng <0 0 0 2 &pcie_intc0 1>, 1077e530d080SAllen-KH Cheng <0 0 0 3 &pcie_intc0 2>, 1078e530d080SAllen-KH Cheng <0 0 0 4 &pcie_intc0 3>; 1079e530d080SAllen-KH Cheng 1080e530d080SAllen-KH Cheng pcie_intc0: interrupt-controller { 1081e530d080SAllen-KH Cheng interrupt-controller; 1082e530d080SAllen-KH Cheng #address-cells = <0>; 1083e530d080SAllen-KH Cheng #interrupt-cells = <1>; 1084e530d080SAllen-KH Cheng }; 1085e530d080SAllen-KH Cheng }; 1086e530d080SAllen-KH Cheng 1087d0a197a0Sbayi cheng nor_flash: spi@11234000 { 1088d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 1089d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 1090d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 1091aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 1092aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 1093aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 1094d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 1095aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 1096aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 1097d0a197a0Sbayi cheng #address-cells = <1>; 1098d0a197a0Sbayi cheng #size-cells = <0>; 109927f0eb16SAllen-KH Cheng status = "disabled"; 1100d0a197a0Sbayi cheng }; 1101d0a197a0Sbayi cheng 11024d50a433SAllen-KH Cheng efuse: efuse@11c10000 { 1103fda0541cSChunfeng Yun compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 11044d50a433SAllen-KH Cheng reg = <0 0x11c10000 0 0x1000>; 11054d50a433SAllen-KH Cheng #address-cells = <1>; 11064d50a433SAllen-KH Cheng #size-cells = <1>; 11074d50a433SAllen-KH Cheng 11084d50a433SAllen-KH Cheng lvts_e_data1: data1@1c0 { 11094d50a433SAllen-KH Cheng reg = <0x1c0 0x58>; 11104d50a433SAllen-KH Cheng }; 11114d50a433SAllen-KH Cheng 11124d50a433SAllen-KH Cheng svs_calibration: calib@580 { 11134d50a433SAllen-KH Cheng reg = <0x580 0x68>; 11144d50a433SAllen-KH Cheng }; 11154d50a433SAllen-KH Cheng }; 11164d50a433SAllen-KH Cheng 11177f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 111848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 111948489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 112048489980SSeiya Wang <0 0x10217300 0 0x80>; 112148489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 112222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 112322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 112448489980SSeiya Wang clock-names = "main", "dma"; 112548489980SSeiya Wang clock-div = <1>; 112648489980SSeiya Wang #address-cells = <1>; 112748489980SSeiya Wang #size-cells = <0>; 112848489980SSeiya Wang status = "disabled"; 112948489980SSeiya Wang }; 113048489980SSeiya Wang 11315d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 11325d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 11335d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 11345d2b897bSChun-Jie Chen #clock-cells = <1>; 11355d2b897bSChun-Jie Chen }; 11365d2b897bSChun-Jie Chen 11377f1a9f47SFabien Parent i2c7: i2c@11d00000 { 113848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 113948489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 114048489980SSeiya Wang <0 0x10217600 0 0x180>; 114148489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 114222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 114322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 114448489980SSeiya Wang clock-names = "main", "dma"; 114548489980SSeiya Wang clock-div = <1>; 114648489980SSeiya Wang #address-cells = <1>; 114748489980SSeiya Wang #size-cells = <0>; 114848489980SSeiya Wang status = "disabled"; 114948489980SSeiya Wang }; 115048489980SSeiya Wang 11517f1a9f47SFabien Parent i2c8: i2c@11d01000 { 115248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 115348489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 115448489980SSeiya Wang <0 0x10217780 0 0x180>; 115548489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 115622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 115722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 115848489980SSeiya Wang clock-names = "main", "dma"; 115948489980SSeiya Wang clock-div = <1>; 116048489980SSeiya Wang #address-cells = <1>; 116148489980SSeiya Wang #size-cells = <0>; 116248489980SSeiya Wang status = "disabled"; 116348489980SSeiya Wang }; 116448489980SSeiya Wang 11657f1a9f47SFabien Parent i2c9: i2c@11d02000 { 116648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 116748489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 116848489980SSeiya Wang <0 0x10217900 0 0x180>; 116948489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 117022623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 117122623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 117248489980SSeiya Wang clock-names = "main", "dma"; 117348489980SSeiya Wang clock-div = <1>; 117448489980SSeiya Wang #address-cells = <1>; 117548489980SSeiya Wang #size-cells = <0>; 117648489980SSeiya Wang status = "disabled"; 117748489980SSeiya Wang }; 117848489980SSeiya Wang 11795d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 11805d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 11815d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 11825d2b897bSChun-Jie Chen #clock-cells = <1>; 11835d2b897bSChun-Jie Chen }; 11845d2b897bSChun-Jie Chen 11857f1a9f47SFabien Parent i2c1: i2c@11d20000 { 118648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 118748489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 118848489980SSeiya Wang <0 0x10217100 0 0x80>; 118948489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 119022623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 119122623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 119248489980SSeiya Wang clock-names = "main", "dma"; 119348489980SSeiya Wang clock-div = <1>; 119448489980SSeiya Wang #address-cells = <1>; 119548489980SSeiya Wang #size-cells = <0>; 119648489980SSeiya Wang status = "disabled"; 119748489980SSeiya Wang }; 119848489980SSeiya Wang 11997f1a9f47SFabien Parent i2c2: i2c@11d21000 { 120048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 120148489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 120248489980SSeiya Wang <0 0x10217180 0 0x180>; 120348489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 120422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 120522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 120648489980SSeiya Wang clock-names = "main", "dma"; 120748489980SSeiya Wang clock-div = <1>; 120848489980SSeiya Wang #address-cells = <1>; 120948489980SSeiya Wang #size-cells = <0>; 121048489980SSeiya Wang status = "disabled"; 121148489980SSeiya Wang }; 121248489980SSeiya Wang 12137f1a9f47SFabien Parent i2c4: i2c@11d22000 { 121448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 121548489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 121648489980SSeiya Wang <0 0x10217380 0 0x180>; 121748489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 121822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 121922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 122048489980SSeiya Wang clock-names = "main", "dma"; 122148489980SSeiya Wang clock-div = <1>; 122248489980SSeiya Wang #address-cells = <1>; 122348489980SSeiya Wang #size-cells = <0>; 122448489980SSeiya Wang status = "disabled"; 122548489980SSeiya Wang }; 122648489980SSeiya Wang 12275d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 12285d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 12295d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 12305d2b897bSChun-Jie Chen #clock-cells = <1>; 12315d2b897bSChun-Jie Chen }; 12325d2b897bSChun-Jie Chen 12337f1a9f47SFabien Parent i2c5: i2c@11e00000 { 123448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 123548489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 123648489980SSeiya Wang <0 0x10217500 0 0x80>; 123748489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 123822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 123922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 124048489980SSeiya Wang clock-names = "main", "dma"; 124148489980SSeiya Wang clock-div = <1>; 124248489980SSeiya Wang #address-cells = <1>; 124348489980SSeiya Wang #size-cells = <0>; 124448489980SSeiya Wang status = "disabled"; 124548489980SSeiya Wang }; 124648489980SSeiya Wang 12475d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 12485d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 12495d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 12505d2b897bSChun-Jie Chen #clock-cells = <1>; 12515d2b897bSChun-Jie Chen }; 12525d2b897bSChun-Jie Chen 125340de66b8SAllen-KH Cheng u3phy0: t-phy@11e40000 { 125440de66b8SAllen-KH Cheng compatible = "mediatek,mt8192-tphy", 125540de66b8SAllen-KH Cheng "mediatek,generic-tphy-v2"; 125640de66b8SAllen-KH Cheng #address-cells = <1>; 125740de66b8SAllen-KH Cheng #size-cells = <1>; 125840de66b8SAllen-KH Cheng ranges = <0x0 0x0 0x11e40000 0x1000>; 125940de66b8SAllen-KH Cheng 126040de66b8SAllen-KH Cheng u2port0: usb-phy@0 { 126140de66b8SAllen-KH Cheng reg = <0x0 0x700>; 126240de66b8SAllen-KH Cheng clocks = <&clk26m>; 126340de66b8SAllen-KH Cheng clock-names = "ref"; 126440de66b8SAllen-KH Cheng #phy-cells = <1>; 126540de66b8SAllen-KH Cheng }; 126640de66b8SAllen-KH Cheng 126740de66b8SAllen-KH Cheng u3port0: usb-phy@700 { 126840de66b8SAllen-KH Cheng reg = <0x700 0x900>; 126940de66b8SAllen-KH Cheng clocks = <&clk26m>; 127040de66b8SAllen-KH Cheng clock-names = "ref"; 127140de66b8SAllen-KH Cheng #phy-cells = <1>; 127240de66b8SAllen-KH Cheng }; 127340de66b8SAllen-KH Cheng }; 127440de66b8SAllen-KH Cheng 127585c4ec6fSAllen-KH Cheng mipi_tx0: dsi-phy@11e50000 { 127685c4ec6fSAllen-KH Cheng compatible = "mediatek,mt8183-mipi-tx"; 127785c4ec6fSAllen-KH Cheng reg = <0 0x11e50000 0 0x1000>; 127885c4ec6fSAllen-KH Cheng clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 127985c4ec6fSAllen-KH Cheng #clock-cells = <0>; 128085c4ec6fSAllen-KH Cheng #phy-cells = <0>; 128185c4ec6fSAllen-KH Cheng clock-output-names = "mipi_tx0_pll"; 128285c4ec6fSAllen-KH Cheng status = "disabled"; 128385c4ec6fSAllen-KH Cheng }; 128485c4ec6fSAllen-KH Cheng 12857f1a9f47SFabien Parent i2c0: i2c@11f00000 { 128648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 128748489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 128848489980SSeiya Wang <0 0x10217080 0 0x80>; 128948489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 129022623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 129122623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 129248489980SSeiya Wang clock-names = "main", "dma"; 129348489980SSeiya Wang clock-div = <1>; 129448489980SSeiya Wang #address-cells = <1>; 129548489980SSeiya Wang #size-cells = <0>; 129648489980SSeiya Wang status = "disabled"; 129748489980SSeiya Wang }; 129848489980SSeiya Wang 12997f1a9f47SFabien Parent i2c6: i2c@11f01000 { 130048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 130148489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 130248489980SSeiya Wang <0 0x10217580 0 0x80>; 130348489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 130422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 130522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 130648489980SSeiya Wang clock-names = "main", "dma"; 130748489980SSeiya Wang clock-div = <1>; 130848489980SSeiya Wang #address-cells = <1>; 130948489980SSeiya Wang #size-cells = <0>; 131048489980SSeiya Wang status = "disabled"; 131148489980SSeiya Wang }; 13125d2b897bSChun-Jie Chen 13135d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 13145d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 13155d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 13165d2b897bSChun-Jie Chen #clock-cells = <1>; 13175d2b897bSChun-Jie Chen }; 13185d2b897bSChun-Jie Chen 13195d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 13205d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 13215d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 13225d2b897bSChun-Jie Chen #clock-cells = <1>; 13235d2b897bSChun-Jie Chen }; 13245d2b897bSChun-Jie Chen 1325db61337eSAllen-KH Cheng mmc0: mmc@11f60000 { 1326db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1327db61337eSAllen-KH Cheng reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1328db61337eSAllen-KH Cheng interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1329db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1330db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1331db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1332db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1333db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1334db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1335db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1336db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1337db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1338db61337eSAllen-KH Cheng status = "disabled"; 1339db61337eSAllen-KH Cheng }; 1340db61337eSAllen-KH Cheng 1341db61337eSAllen-KH Cheng mmc1: mmc@11f70000 { 1342db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1343db61337eSAllen-KH Cheng reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1344db61337eSAllen-KH Cheng interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1345db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1346db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1347db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1348db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1349db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1350db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1351db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1352db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1353db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1354db61337eSAllen-KH Cheng status = "disabled"; 13555d2b897bSChun-Jie Chen }; 13565d2b897bSChun-Jie Chen 1357e1233345SAlyssa Rosenzweig gpu: gpu@13000000 { 1358e1233345SAlyssa Rosenzweig compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm"; 1359e1233345SAlyssa Rosenzweig reg = <0 0x13000000 0 0x4000>; 1360e1233345SAlyssa Rosenzweig interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>, 1361e1233345SAlyssa Rosenzweig <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, 1362e1233345SAlyssa Rosenzweig <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1363e1233345SAlyssa Rosenzweig interrupt-names = "job", "mmu", "gpu"; 1364e1233345SAlyssa Rosenzweig 1365e1233345SAlyssa Rosenzweig clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 1366e1233345SAlyssa Rosenzweig 1367e1233345SAlyssa Rosenzweig power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>, 1368e1233345SAlyssa Rosenzweig <&spm MT8192_POWER_DOMAIN_MFG3>, 1369e1233345SAlyssa Rosenzweig <&spm MT8192_POWER_DOMAIN_MFG4>, 1370e1233345SAlyssa Rosenzweig <&spm MT8192_POWER_DOMAIN_MFG5>, 1371e1233345SAlyssa Rosenzweig <&spm MT8192_POWER_DOMAIN_MFG6>; 1372e1233345SAlyssa Rosenzweig power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1373e1233345SAlyssa Rosenzweig 1374e1233345SAlyssa Rosenzweig operating-points-v2 = <&gpu_opp_table>; 1375e1233345SAlyssa Rosenzweig 1376e1233345SAlyssa Rosenzweig status = "disabled"; 1377e1233345SAlyssa Rosenzweig }; 1378e1233345SAlyssa Rosenzweig 13795d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 13805d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 13815d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 13825d2b897bSChun-Jie Chen #clock-cells = <1>; 13835d2b897bSChun-Jie Chen }; 13845d2b897bSChun-Jie Chen 13855d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 13865d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 13875d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 13885d2b897bSChun-Jie Chen #clock-cells = <1>; 13897d355378SAllen-KH Cheng #reset-cells = <1>; 1390b4b75bacSAllen-KH Cheng mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1391b4b75bacSAllen-KH Cheng <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1392b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1393b4b75bacSAllen-KH Cheng }; 1394b4b75bacSAllen-KH Cheng 1395b4b75bacSAllen-KH Cheng mutex: mutex@14001000 { 1396b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-mutex"; 1397b4b75bacSAllen-KH Cheng reg = <0 0x14001000 0 0x1000>; 1398b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1399b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1400b4b75bacSAllen-KH Cheng mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1401b4b75bacSAllen-KH Cheng <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1402b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14035d2b897bSChun-Jie Chen }; 14045d2b897bSChun-Jie Chen 14054a65b0f1SAllen-KH Cheng smi_common: smi@14002000 { 14064a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-common"; 14074a65b0f1SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 14084a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 14094a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 14104a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 14114a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>; 14124a65b0f1SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 14134a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14144a65b0f1SAllen-KH Cheng }; 14154a65b0f1SAllen-KH Cheng 14164a65b0f1SAllen-KH Cheng larb0: larb@14003000 { 14174a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14184a65b0f1SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 14194a65b0f1SAllen-KH Cheng mediatek,larb-id = <0>; 14204a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14214a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 14224a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14234a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14244a65b0f1SAllen-KH Cheng }; 14254a65b0f1SAllen-KH Cheng 14264a65b0f1SAllen-KH Cheng larb1: larb@14004000 { 14274a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14284a65b0f1SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 14294a65b0f1SAllen-KH Cheng mediatek,larb-id = <1>; 14304a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14314a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 14324a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14334a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14344a65b0f1SAllen-KH Cheng }; 14354a65b0f1SAllen-KH Cheng 1436b4b75bacSAllen-KH Cheng ovl0: ovl@14005000 { 1437b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl"; 1438b4b75bacSAllen-KH Cheng reg = <0 0x14005000 0 0x1000>; 1439b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1440b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0>; 1441b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1442b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1443b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1444b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1445b4b75bacSAllen-KH Cheng }; 1446b4b75bacSAllen-KH Cheng 1447b4b75bacSAllen-KH Cheng ovl_2l0: ovl@14006000 { 1448b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1449b4b75bacSAllen-KH Cheng reg = <0 0x14006000 0 0x1000>; 1450b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1451b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1452b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1453b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1454b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1455b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1456b4b75bacSAllen-KH Cheng }; 1457b4b75bacSAllen-KH Cheng 1458b4b75bacSAllen-KH Cheng rdma0: rdma@14007000 { 1459b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1460b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1461b4b75bacSAllen-KH Cheng reg = <0 0x14007000 0 0x1000>; 1462b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1463b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1464b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1465b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <5120>; 1466b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1467b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1468b4b75bacSAllen-KH Cheng }; 1469b4b75bacSAllen-KH Cheng 1470b4b75bacSAllen-KH Cheng color0: color@14009000 { 1471b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-color", 1472b4b75bacSAllen-KH Cheng "mediatek,mt8173-disp-color"; 1473b4b75bacSAllen-KH Cheng reg = <0 0x14009000 0 0x1000>; 1474b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1475b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1476b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1477b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1478b4b75bacSAllen-KH Cheng }; 1479b4b75bacSAllen-KH Cheng 1480b4b75bacSAllen-KH Cheng ccorr0: ccorr@1400a000 { 1481b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ccorr"; 1482b4b75bacSAllen-KH Cheng reg = <0 0x1400a000 0 0x1000>; 1483b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1484b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1485b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1486b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1487b4b75bacSAllen-KH Cheng }; 1488b4b75bacSAllen-KH Cheng 1489b4b75bacSAllen-KH Cheng aal0: aal@1400b000 { 1490b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-aal", 1491b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-aal"; 1492b4b75bacSAllen-KH Cheng reg = <0 0x1400b000 0 0x1000>; 1493b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1494b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1495b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_AAL0>; 1496b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1497b4b75bacSAllen-KH Cheng }; 1498b4b75bacSAllen-KH Cheng 1499b4b75bacSAllen-KH Cheng gamma0: gamma@1400c000 { 1500b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-gamma", 1501b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-gamma"; 1502b4b75bacSAllen-KH Cheng reg = <0 0x1400c000 0 0x1000>; 1503b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1504b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1505b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1506b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1507b4b75bacSAllen-KH Cheng }; 1508b4b75bacSAllen-KH Cheng 1509b4b75bacSAllen-KH Cheng postmask0: postmask@1400d000 { 1510b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-postmask"; 1511b4b75bacSAllen-KH Cheng reg = <0 0x1400d000 0 0x1000>; 1512b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1513b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1514b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1515b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1516b4b75bacSAllen-KH Cheng }; 1517b4b75bacSAllen-KH Cheng 1518b4b75bacSAllen-KH Cheng dither0: dither@1400e000 { 1519b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-dither", 1520b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-dither"; 1521b4b75bacSAllen-KH Cheng reg = <0 0x1400e000 0 0x1000>; 1522b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1523b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1524b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1525b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1526b4b75bacSAllen-KH Cheng }; 1527b4b75bacSAllen-KH Cheng 15280708ed7cSAllen-KH Cheng dsi0: dsi@14010000 { 15290708ed7cSAllen-KH Cheng compatible = "mediatek,mt8183-dsi"; 15300708ed7cSAllen-KH Cheng reg = <0 0x14010000 0 0x1000>; 15310708ed7cSAllen-KH Cheng interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 15320708ed7cSAllen-KH Cheng clocks = <&mmsys CLK_MM_DSI0>, 15330708ed7cSAllen-KH Cheng <&mmsys CLK_MM_DSI_DSI0>, 15340708ed7cSAllen-KH Cheng <&mipi_tx0>; 15350708ed7cSAllen-KH Cheng clock-names = "engine", "digital", "hs"; 15360708ed7cSAllen-KH Cheng phys = <&mipi_tx0>; 15370708ed7cSAllen-KH Cheng phy-names = "dphy"; 15380708ed7cSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 15390708ed7cSAllen-KH Cheng resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 15400708ed7cSAllen-KH Cheng status = "disabled"; 15410708ed7cSAllen-KH Cheng 15420708ed7cSAllen-KH Cheng port { 15430708ed7cSAllen-KH Cheng dsi_out: endpoint { }; 15440708ed7cSAllen-KH Cheng }; 15450708ed7cSAllen-KH Cheng }; 15460708ed7cSAllen-KH Cheng 1547b4b75bacSAllen-KH Cheng ovl_2l2: ovl@14014000 { 1548b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1549b4b75bacSAllen-KH Cheng reg = <0 0x14014000 0 0x1000>; 1550b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1551b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1552b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1553b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1554b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1555b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1556b4b75bacSAllen-KH Cheng }; 1557b4b75bacSAllen-KH Cheng 1558b4b75bacSAllen-KH Cheng rdma4: rdma@14015000 { 1559b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1560b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1561b4b75bacSAllen-KH Cheng reg = <0 0x14015000 0 0x1000>; 1562b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1563b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1564b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1565b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1566b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <2048>; 1567b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1568b4b75bacSAllen-KH Cheng }; 1569b4b75bacSAllen-KH Cheng 1570b2edd519SAllen-KH Cheng dpi0: dpi@14016000 { 1571b2edd519SAllen-KH Cheng compatible = "mediatek,mt8192-dpi"; 1572b2edd519SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1573b2edd519SAllen-KH Cheng interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1574b2edd519SAllen-KH Cheng clocks = <&mmsys CLK_MM_DPI_DPI0>, 1575b2edd519SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI0>, 1576b2edd519SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 1577b2edd519SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 1578b2edd519SAllen-KH Cheng status = "disabled"; 1579b2edd519SAllen-KH Cheng }; 1580b2edd519SAllen-KH Cheng 15814a65b0f1SAllen-KH Cheng iommu0: m4u@1401d000 { 15824a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-m4u"; 15834a65b0f1SAllen-KH Cheng reg = <0 0x1401d000 0 0x1000>; 15844a65b0f1SAllen-KH Cheng mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 15854a65b0f1SAllen-KH Cheng <&larb4>, <&larb5>, <&larb7>, 15864a65b0f1SAllen-KH Cheng <&larb9>, <&larb11>, <&larb13>, 15874a65b0f1SAllen-KH Cheng <&larb14>, <&larb16>, <&larb17>, 15884a65b0f1SAllen-KH Cheng <&larb18>, <&larb19>, <&larb20>; 15894a65b0f1SAllen-KH Cheng interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 15904a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 15914a65b0f1SAllen-KH Cheng clock-names = "bclk"; 15924a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 15934a65b0f1SAllen-KH Cheng #iommu-cells = <1>; 15944a65b0f1SAllen-KH Cheng }; 15954a65b0f1SAllen-KH Cheng 15965d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 15975d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 15985d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 15995d2b897bSChun-Jie Chen #clock-cells = <1>; 16005d2b897bSChun-Jie Chen }; 16015d2b897bSChun-Jie Chen 16024a65b0f1SAllen-KH Cheng larb9: larb@1502e000 { 16034a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16044a65b0f1SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 16054a65b0f1SAllen-KH Cheng mediatek,larb-id = <9>; 16064a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16074a65b0f1SAllen-KH Cheng clocks = <&imgsys CLK_IMG_LARB9>, 16084a65b0f1SAllen-KH Cheng <&imgsys CLK_IMG_LARB9>; 16094a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16104a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 16114a65b0f1SAllen-KH Cheng }; 16124a65b0f1SAllen-KH Cheng 16135d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 16145d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 16155d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 16165d2b897bSChun-Jie Chen #clock-cells = <1>; 16175d2b897bSChun-Jie Chen }; 16185d2b897bSChun-Jie Chen 16194a65b0f1SAllen-KH Cheng larb11: larb@1582e000 { 16204a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16214a65b0f1SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 16224a65b0f1SAllen-KH Cheng mediatek,larb-id = <11>; 16234a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16244a65b0f1SAllen-KH Cheng clocks = <&imgsys2 CLK_IMG2_LARB11>, 16254a65b0f1SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB11>; 16264a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16274a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 16284a65b0f1SAllen-KH Cheng }; 16294a65b0f1SAllen-KH Cheng 16304a65b0f1SAllen-KH Cheng larb5: larb@1600d000 { 16314a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16324a65b0f1SAllen-KH Cheng reg = <0 0x1600d000 0 0x1000>; 16334a65b0f1SAllen-KH Cheng mediatek,larb-id = <5>; 16344a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16354a65b0f1SAllen-KH Cheng clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 16364a65b0f1SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 16374a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16384a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 16394a65b0f1SAllen-KH Cheng }; 16404a65b0f1SAllen-KH Cheng 16415d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 16425d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 16435d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 16445d2b897bSChun-Jie Chen #clock-cells = <1>; 16455d2b897bSChun-Jie Chen }; 16465d2b897bSChun-Jie Chen 16474a65b0f1SAllen-KH Cheng larb4: larb@1602e000 { 16484a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16494a65b0f1SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 16504a65b0f1SAllen-KH Cheng mediatek,larb-id = <4>; 16514a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16524a65b0f1SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 16534a65b0f1SAllen-KH Cheng <&vdecsys CLK_VDEC_SOC_LARB1>; 16544a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16554a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 16564a65b0f1SAllen-KH Cheng }; 16574a65b0f1SAllen-KH Cheng 16585d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 16595d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 16605d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 16615d2b897bSChun-Jie Chen #clock-cells = <1>; 16625d2b897bSChun-Jie Chen }; 16635d2b897bSChun-Jie Chen 16645d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 16655d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 16665d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 16675d2b897bSChun-Jie Chen #clock-cells = <1>; 16685d2b897bSChun-Jie Chen }; 16695d2b897bSChun-Jie Chen 16704a65b0f1SAllen-KH Cheng larb7: larb@17010000 { 16714a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16724a65b0f1SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 16734a65b0f1SAllen-KH Cheng mediatek,larb-id = <7>; 16744a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16754a65b0f1SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET0_LARB>, 16764a65b0f1SAllen-KH Cheng <&vencsys CLK_VENC_SET1_VENC>; 16774a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16784a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 16794a65b0f1SAllen-KH Cheng }; 16804a65b0f1SAllen-KH Cheng 1681aa8f3711SAllen-KH Cheng vcodec_enc: vcodec@17020000 { 1682aa8f3711SAllen-KH Cheng compatible = "mediatek,mt8192-vcodec-enc"; 1683aa8f3711SAllen-KH Cheng reg = <0 0x17020000 0 0x2000>; 1684aa8f3711SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1685aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REC>, 1686aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1687aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1688aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1689aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1690aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1691aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1692aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1693aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1694aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1695aa8f3711SAllen-KH Cheng interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1696aa8f3711SAllen-KH Cheng mediatek,scp = <&scp>; 1697aa8f3711SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1698aa8f3711SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET1_VENC>; 1699aa8f3711SAllen-KH Cheng clock-names = "venc-set1"; 1700aa8f3711SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1701aa8f3711SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1702aa8f3711SAllen-KH Cheng }; 1703aa8f3711SAllen-KH Cheng 17045d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 17055d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 17065d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 17075d2b897bSChun-Jie Chen #clock-cells = <1>; 17085d2b897bSChun-Jie Chen }; 17095d2b897bSChun-Jie Chen 17104a65b0f1SAllen-KH Cheng larb13: larb@1a001000 { 17114a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17124a65b0f1SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 17134a65b0f1SAllen-KH Cheng mediatek,larb-id = <13>; 17144a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17154a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 17164a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB13>; 17174a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17184a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 17194a65b0f1SAllen-KH Cheng }; 17204a65b0f1SAllen-KH Cheng 17214a65b0f1SAllen-KH Cheng larb14: larb@1a002000 { 17224a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17234a65b0f1SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 17244a65b0f1SAllen-KH Cheng mediatek,larb-id = <14>; 17254a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17264a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 17274a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB14>; 17284a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17294a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 17304a65b0f1SAllen-KH Cheng }; 17314a65b0f1SAllen-KH Cheng 17324a65b0f1SAllen-KH Cheng larb16: larb@1a00f000 { 17334a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17344a65b0f1SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 17354a65b0f1SAllen-KH Cheng mediatek,larb-id = <16>; 17364a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17374a65b0f1SAllen-KH Cheng clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 17384a65b0f1SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX>; 17394a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17404a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 17414a65b0f1SAllen-KH Cheng }; 17424a65b0f1SAllen-KH Cheng 17434a65b0f1SAllen-KH Cheng larb17: larb@1a010000 { 17444a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17454a65b0f1SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 17464a65b0f1SAllen-KH Cheng mediatek,larb-id = <17>; 17474a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17484a65b0f1SAllen-KH Cheng clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 17494a65b0f1SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX>; 17504a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17514a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 17524a65b0f1SAllen-KH Cheng }; 17534a65b0f1SAllen-KH Cheng 17544a65b0f1SAllen-KH Cheng larb18: larb@1a011000 { 17554a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17564a65b0f1SAllen-KH Cheng reg = <0 0x1a011000 0 0x1000>; 17574a65b0f1SAllen-KH Cheng mediatek,larb-id = <18>; 17584a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17594a65b0f1SAllen-KH Cheng clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 17604a65b0f1SAllen-KH Cheng <&camsys_rawc CLK_CAM_RAWC_CAM>; 17614a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17624a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 17634a65b0f1SAllen-KH Cheng }; 17644a65b0f1SAllen-KH Cheng 17655d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 17665d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 17675d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 17685d2b897bSChun-Jie Chen #clock-cells = <1>; 17695d2b897bSChun-Jie Chen }; 17705d2b897bSChun-Jie Chen 17715d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 17725d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 17735d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 17745d2b897bSChun-Jie Chen #clock-cells = <1>; 17755d2b897bSChun-Jie Chen }; 17765d2b897bSChun-Jie Chen 17775d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 17785d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 17795d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 17805d2b897bSChun-Jie Chen #clock-cells = <1>; 17815d2b897bSChun-Jie Chen }; 17825d2b897bSChun-Jie Chen 17835d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 17845d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 17855d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 17865d2b897bSChun-Jie Chen #clock-cells = <1>; 17875d2b897bSChun-Jie Chen }; 17885d2b897bSChun-Jie Chen 17894a65b0f1SAllen-KH Cheng larb20: larb@1b00f000 { 17904a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17914a65b0f1SAllen-KH Cheng reg = <0 0x1b00f000 0 0x1000>; 17924a65b0f1SAllen-KH Cheng mediatek,larb-id = <20>; 17934a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17944a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 17954a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB20>; 17964a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17974a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 17984a65b0f1SAllen-KH Cheng }; 17994a65b0f1SAllen-KH Cheng 18004a65b0f1SAllen-KH Cheng larb19: larb@1b10f000 { 18014a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 18024a65b0f1SAllen-KH Cheng reg = <0 0x1b10f000 0 0x1000>; 18034a65b0f1SAllen-KH Cheng mediatek,larb-id = <19>; 18044a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 18054a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 18064a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB19>; 18074a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 18084a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 18094a65b0f1SAllen-KH Cheng }; 18104a65b0f1SAllen-KH Cheng 18115d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 18125d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 18135d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 18145d2b897bSChun-Jie Chen #clock-cells = <1>; 18155d2b897bSChun-Jie Chen }; 18164a65b0f1SAllen-KH Cheng 18174a65b0f1SAllen-KH Cheng larb2: larb@1f002000 { 18184a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 18194a65b0f1SAllen-KH Cheng reg = <0 0x1f002000 0 0x1000>; 18204a65b0f1SAllen-KH Cheng mediatek,larb-id = <2>; 18214a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 18224a65b0f1SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, 18234a65b0f1SAllen-KH Cheng <&mdpsys CLK_MDP_SMI0>; 18244a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 18254a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 18264a65b0f1SAllen-KH Cheng }; 182748489980SSeiya Wang }; 182848489980SSeiya Wang}; 1829