1*48489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*48489980SSeiya Wang/* 3*48489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 4*48489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 5*48489980SSeiya Wang */ 6*48489980SSeiya Wang 7*48489980SSeiya Wang/dts-v1/; 8*48489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 9*48489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 10*48489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 11*48489980SSeiya Wang 12*48489980SSeiya Wang/ { 13*48489980SSeiya Wang compatible = "mediatek,mt8192"; 14*48489980SSeiya Wang interrupt-parent = <&gic>; 15*48489980SSeiya Wang #address-cells = <2>; 16*48489980SSeiya Wang #size-cells = <2>; 17*48489980SSeiya Wang 18*48489980SSeiya Wang clk26m: oscillator0 { 19*48489980SSeiya Wang compatible = "fixed-clock"; 20*48489980SSeiya Wang #clock-cells = <0>; 21*48489980SSeiya Wang clock-frequency = <26000000>; 22*48489980SSeiya Wang clock-output-names = "clk26m"; 23*48489980SSeiya Wang }; 24*48489980SSeiya Wang 25*48489980SSeiya Wang clk32k: oscillator1 { 26*48489980SSeiya Wang compatible = "fixed-clock"; 27*48489980SSeiya Wang #clock-cells = <0>; 28*48489980SSeiya Wang clock-frequency = <32768>; 29*48489980SSeiya Wang clock-output-names = "clk32k"; 30*48489980SSeiya Wang }; 31*48489980SSeiya Wang 32*48489980SSeiya Wang cpus { 33*48489980SSeiya Wang #address-cells = <1>; 34*48489980SSeiya Wang #size-cells = <0>; 35*48489980SSeiya Wang 36*48489980SSeiya Wang cpu0: cpu@0 { 37*48489980SSeiya Wang device_type = "cpu"; 38*48489980SSeiya Wang compatible = "arm,cortex-a55"; 39*48489980SSeiya Wang reg = <0x000>; 40*48489980SSeiya Wang enable-method = "psci"; 41*48489980SSeiya Wang clock-frequency = <1701000000>; 42*48489980SSeiya Wang next-level-cache = <&l2_0>; 43*48489980SSeiya Wang capacity-dmips-mhz = <530>; 44*48489980SSeiya Wang }; 45*48489980SSeiya Wang 46*48489980SSeiya Wang cpu1: cpu@100 { 47*48489980SSeiya Wang device_type = "cpu"; 48*48489980SSeiya Wang compatible = "arm,cortex-a55"; 49*48489980SSeiya Wang reg = <0x100>; 50*48489980SSeiya Wang enable-method = "psci"; 51*48489980SSeiya Wang clock-frequency = <1701000000>; 52*48489980SSeiya Wang next-level-cache = <&l2_0>; 53*48489980SSeiya Wang capacity-dmips-mhz = <530>; 54*48489980SSeiya Wang }; 55*48489980SSeiya Wang 56*48489980SSeiya Wang cpu2: cpu@200 { 57*48489980SSeiya Wang device_type = "cpu"; 58*48489980SSeiya Wang compatible = "arm,cortex-a55"; 59*48489980SSeiya Wang reg = <0x200>; 60*48489980SSeiya Wang enable-method = "psci"; 61*48489980SSeiya Wang clock-frequency = <1701000000>; 62*48489980SSeiya Wang next-level-cache = <&l2_0>; 63*48489980SSeiya Wang capacity-dmips-mhz = <530>; 64*48489980SSeiya Wang }; 65*48489980SSeiya Wang 66*48489980SSeiya Wang cpu3: cpu@300 { 67*48489980SSeiya Wang device_type = "cpu"; 68*48489980SSeiya Wang compatible = "arm,cortex-a55"; 69*48489980SSeiya Wang reg = <0x300>; 70*48489980SSeiya Wang enable-method = "psci"; 71*48489980SSeiya Wang clock-frequency = <1701000000>; 72*48489980SSeiya Wang next-level-cache = <&l2_0>; 73*48489980SSeiya Wang capacity-dmips-mhz = <530>; 74*48489980SSeiya Wang }; 75*48489980SSeiya Wang 76*48489980SSeiya Wang cpu4: cpu@400 { 77*48489980SSeiya Wang device_type = "cpu"; 78*48489980SSeiya Wang compatible = "arm,cortex-a76"; 79*48489980SSeiya Wang reg = <0x400>; 80*48489980SSeiya Wang enable-method = "psci"; 81*48489980SSeiya Wang clock-frequency = <2171000000>; 82*48489980SSeiya Wang next-level-cache = <&l2_1>; 83*48489980SSeiya Wang capacity-dmips-mhz = <1024>; 84*48489980SSeiya Wang }; 85*48489980SSeiya Wang 86*48489980SSeiya Wang cpu5: cpu@500 { 87*48489980SSeiya Wang device_type = "cpu"; 88*48489980SSeiya Wang compatible = "arm,cortex-a76"; 89*48489980SSeiya Wang reg = <0x500>; 90*48489980SSeiya Wang enable-method = "psci"; 91*48489980SSeiya Wang clock-frequency = <2171000000>; 92*48489980SSeiya Wang next-level-cache = <&l2_1>; 93*48489980SSeiya Wang capacity-dmips-mhz = <1024>; 94*48489980SSeiya Wang }; 95*48489980SSeiya Wang 96*48489980SSeiya Wang cpu6: cpu@600 { 97*48489980SSeiya Wang device_type = "cpu"; 98*48489980SSeiya Wang compatible = "arm,cortex-a76"; 99*48489980SSeiya Wang reg = <0x600>; 100*48489980SSeiya Wang enable-method = "psci"; 101*48489980SSeiya Wang clock-frequency = <2171000000>; 102*48489980SSeiya Wang next-level-cache = <&l2_1>; 103*48489980SSeiya Wang capacity-dmips-mhz = <1024>; 104*48489980SSeiya Wang }; 105*48489980SSeiya Wang 106*48489980SSeiya Wang cpu7: cpu@700 { 107*48489980SSeiya Wang device_type = "cpu"; 108*48489980SSeiya Wang compatible = "arm,cortex-a76"; 109*48489980SSeiya Wang reg = <0x700>; 110*48489980SSeiya Wang enable-method = "psci"; 111*48489980SSeiya Wang clock-frequency = <2171000000>; 112*48489980SSeiya Wang next-level-cache = <&l2_1>; 113*48489980SSeiya Wang capacity-dmips-mhz = <1024>; 114*48489980SSeiya Wang }; 115*48489980SSeiya Wang 116*48489980SSeiya Wang cpu-map { 117*48489980SSeiya Wang cluster0 { 118*48489980SSeiya Wang core0 { 119*48489980SSeiya Wang cpu = <&cpu0>; 120*48489980SSeiya Wang }; 121*48489980SSeiya Wang core1 { 122*48489980SSeiya Wang cpu = <&cpu1>; 123*48489980SSeiya Wang }; 124*48489980SSeiya Wang core2 { 125*48489980SSeiya Wang cpu = <&cpu2>; 126*48489980SSeiya Wang }; 127*48489980SSeiya Wang core3 { 128*48489980SSeiya Wang cpu = <&cpu3>; 129*48489980SSeiya Wang }; 130*48489980SSeiya Wang }; 131*48489980SSeiya Wang 132*48489980SSeiya Wang cluster1 { 133*48489980SSeiya Wang core0 { 134*48489980SSeiya Wang cpu = <&cpu4>; 135*48489980SSeiya Wang }; 136*48489980SSeiya Wang core1 { 137*48489980SSeiya Wang cpu = <&cpu5>; 138*48489980SSeiya Wang }; 139*48489980SSeiya Wang core2 { 140*48489980SSeiya Wang cpu = <&cpu6>; 141*48489980SSeiya Wang }; 142*48489980SSeiya Wang core3 { 143*48489980SSeiya Wang cpu = <&cpu7>; 144*48489980SSeiya Wang }; 145*48489980SSeiya Wang }; 146*48489980SSeiya Wang }; 147*48489980SSeiya Wang 148*48489980SSeiya Wang l2_0: l2-cache0 { 149*48489980SSeiya Wang compatible = "cache"; 150*48489980SSeiya Wang next-level-cache = <&l3_0>; 151*48489980SSeiya Wang }; 152*48489980SSeiya Wang 153*48489980SSeiya Wang l2_1: l2-cache1 { 154*48489980SSeiya Wang compatible = "cache"; 155*48489980SSeiya Wang next-level-cache = <&l3_0>; 156*48489980SSeiya Wang }; 157*48489980SSeiya Wang 158*48489980SSeiya Wang l3_0: l3-cache { 159*48489980SSeiya Wang compatible = "cache"; 160*48489980SSeiya Wang }; 161*48489980SSeiya Wang }; 162*48489980SSeiya Wang 163*48489980SSeiya Wang pmu-a55 { 164*48489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 165*48489980SSeiya Wang interrupt-parent = <&gic>; 166*48489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 167*48489980SSeiya Wang }; 168*48489980SSeiya Wang 169*48489980SSeiya Wang pmu-a76 { 170*48489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 171*48489980SSeiya Wang interrupt-parent = <&gic>; 172*48489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 173*48489980SSeiya Wang }; 174*48489980SSeiya Wang 175*48489980SSeiya Wang psci { 176*48489980SSeiya Wang compatible = "arm,psci-1.0"; 177*48489980SSeiya Wang method = "smc"; 178*48489980SSeiya Wang }; 179*48489980SSeiya Wang 180*48489980SSeiya Wang timer: timer { 181*48489980SSeiya Wang compatible = "arm,armv8-timer"; 182*48489980SSeiya Wang interrupt-parent = <&gic>; 183*48489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 184*48489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 185*48489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 186*48489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 187*48489980SSeiya Wang clock-frequency = <13000000>; 188*48489980SSeiya Wang }; 189*48489980SSeiya Wang 190*48489980SSeiya Wang soc { 191*48489980SSeiya Wang #address-cells = <2>; 192*48489980SSeiya Wang #size-cells = <2>; 193*48489980SSeiya Wang compatible = "simple-bus"; 194*48489980SSeiya Wang ranges; 195*48489980SSeiya Wang 196*48489980SSeiya Wang gic: interrupt-controller@c000000 { 197*48489980SSeiya Wang compatible = "arm,gic-v3"; 198*48489980SSeiya Wang #interrupt-cells = <4>; 199*48489980SSeiya Wang #redistributor-regions = <1>; 200*48489980SSeiya Wang interrupt-parent = <&gic>; 201*48489980SSeiya Wang interrupt-controller; 202*48489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 203*48489980SSeiya Wang <0 0x0c040000 0 0x200000>; 204*48489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 205*48489980SSeiya Wang 206*48489980SSeiya Wang ppi-partitions { 207*48489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 208*48489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 209*48489980SSeiya Wang }; 210*48489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 211*48489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 212*48489980SSeiya Wang }; 213*48489980SSeiya Wang }; 214*48489980SSeiya Wang }; 215*48489980SSeiya Wang 216*48489980SSeiya Wang pio: pinctrl@10005000 { 217*48489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 218*48489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 219*48489980SSeiya Wang <0 0x11c20000 0 0x1000>, 220*48489980SSeiya Wang <0 0x11d10000 0 0x1000>, 221*48489980SSeiya Wang <0 0x11d30000 0 0x1000>, 222*48489980SSeiya Wang <0 0x11d40000 0 0x1000>, 223*48489980SSeiya Wang <0 0x11e20000 0 0x1000>, 224*48489980SSeiya Wang <0 0x11e70000 0 0x1000>, 225*48489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 226*48489980SSeiya Wang <0 0x11f20000 0 0x1000>, 227*48489980SSeiya Wang <0 0x11f30000 0 0x1000>, 228*48489980SSeiya Wang <0 0x1000b000 0 0x1000>; 229*48489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 230*48489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 231*48489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 232*48489980SSeiya Wang "iocfg_tl", "eint"; 233*48489980SSeiya Wang gpio-controller; 234*48489980SSeiya Wang #gpio-cells = <2>; 235*48489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 236*48489980SSeiya Wang interrupt-controller; 237*48489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 238*48489980SSeiya Wang #interrupt-cells = <2>; 239*48489980SSeiya Wang }; 240*48489980SSeiya Wang 241*48489980SSeiya Wang systimer: timer@10017000 { 242*48489980SSeiya Wang compatible = "mediatek,mt8192-timer", 243*48489980SSeiya Wang "mediatek,mt6765-timer"; 244*48489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 245*48489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 246*48489980SSeiya Wang clocks = <&clk26m>; 247*48489980SSeiya Wang clock-names = "clk13m"; 248*48489980SSeiya Wang }; 249*48489980SSeiya Wang 250*48489980SSeiya Wang uart0: serial@11002000 { 251*48489980SSeiya Wang compatible = "mediatek,mt8192-uart", 252*48489980SSeiya Wang "mediatek,mt6577-uart"; 253*48489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 254*48489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 255*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 256*48489980SSeiya Wang clock-names = "baud", "bus"; 257*48489980SSeiya Wang status = "disabled"; 258*48489980SSeiya Wang }; 259*48489980SSeiya Wang 260*48489980SSeiya Wang uart1: serial@11003000 { 261*48489980SSeiya Wang compatible = "mediatek,mt8192-uart", 262*48489980SSeiya Wang "mediatek,mt6577-uart"; 263*48489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 264*48489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 265*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 266*48489980SSeiya Wang clock-names = "baud", "bus"; 267*48489980SSeiya Wang status = "disabled"; 268*48489980SSeiya Wang }; 269*48489980SSeiya Wang 270*48489980SSeiya Wang spi0: spi@1100a000 { 271*48489980SSeiya Wang compatible = "mediatek,mt8192-spi", 272*48489980SSeiya Wang "mediatek,mt6765-spi"; 273*48489980SSeiya Wang #address-cells = <1>; 274*48489980SSeiya Wang #size-cells = <0>; 275*48489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 276*48489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 277*48489980SSeiya Wang clocks = <&clk26m>, 278*48489980SSeiya Wang <&clk26m>, 279*48489980SSeiya Wang <&clk26m>; 280*48489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 281*48489980SSeiya Wang status = "disabled"; 282*48489980SSeiya Wang }; 283*48489980SSeiya Wang 284*48489980SSeiya Wang spi1: spi@11010000 { 285*48489980SSeiya Wang compatible = "mediatek,mt8192-spi", 286*48489980SSeiya Wang "mediatek,mt6765-spi"; 287*48489980SSeiya Wang #address-cells = <1>; 288*48489980SSeiya Wang #size-cells = <0>; 289*48489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 290*48489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 291*48489980SSeiya Wang clocks = <&clk26m>, 292*48489980SSeiya Wang <&clk26m>, 293*48489980SSeiya Wang <&clk26m>; 294*48489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 295*48489980SSeiya Wang status = "disabled"; 296*48489980SSeiya Wang }; 297*48489980SSeiya Wang 298*48489980SSeiya Wang spi2: spi@11012000 { 299*48489980SSeiya Wang compatible = "mediatek,mt8192-spi", 300*48489980SSeiya Wang "mediatek,mt6765-spi"; 301*48489980SSeiya Wang #address-cells = <1>; 302*48489980SSeiya Wang #size-cells = <0>; 303*48489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 304*48489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 305*48489980SSeiya Wang clocks = <&clk26m>, 306*48489980SSeiya Wang <&clk26m>, 307*48489980SSeiya Wang <&clk26m>; 308*48489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 309*48489980SSeiya Wang status = "disabled"; 310*48489980SSeiya Wang }; 311*48489980SSeiya Wang 312*48489980SSeiya Wang spi3: spi@11013000 { 313*48489980SSeiya Wang compatible = "mediatek,mt8192-spi", 314*48489980SSeiya Wang "mediatek,mt6765-spi"; 315*48489980SSeiya Wang #address-cells = <1>; 316*48489980SSeiya Wang #size-cells = <0>; 317*48489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 318*48489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 319*48489980SSeiya Wang clocks = <&clk26m>, 320*48489980SSeiya Wang <&clk26m>, 321*48489980SSeiya Wang <&clk26m>; 322*48489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 323*48489980SSeiya Wang status = "disabled"; 324*48489980SSeiya Wang }; 325*48489980SSeiya Wang 326*48489980SSeiya Wang spi4: spi@11018000 { 327*48489980SSeiya Wang compatible = "mediatek,mt8192-spi", 328*48489980SSeiya Wang "mediatek,mt6765-spi"; 329*48489980SSeiya Wang #address-cells = <1>; 330*48489980SSeiya Wang #size-cells = <0>; 331*48489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 332*48489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 333*48489980SSeiya Wang clocks = <&clk26m>, 334*48489980SSeiya Wang <&clk26m>, 335*48489980SSeiya Wang <&clk26m>; 336*48489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 337*48489980SSeiya Wang status = "disabled"; 338*48489980SSeiya Wang }; 339*48489980SSeiya Wang 340*48489980SSeiya Wang spi5: spi@11019000 { 341*48489980SSeiya Wang compatible = "mediatek,mt8192-spi", 342*48489980SSeiya Wang "mediatek,mt6765-spi"; 343*48489980SSeiya Wang #address-cells = <1>; 344*48489980SSeiya Wang #size-cells = <0>; 345*48489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 346*48489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 347*48489980SSeiya Wang clocks = <&clk26m>, 348*48489980SSeiya Wang <&clk26m>, 349*48489980SSeiya Wang <&clk26m>; 350*48489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 351*48489980SSeiya Wang status = "disabled"; 352*48489980SSeiya Wang }; 353*48489980SSeiya Wang 354*48489980SSeiya Wang spi6: spi@1101d000 { 355*48489980SSeiya Wang compatible = "mediatek,mt8192-spi", 356*48489980SSeiya Wang "mediatek,mt6765-spi"; 357*48489980SSeiya Wang #address-cells = <1>; 358*48489980SSeiya Wang #size-cells = <0>; 359*48489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 360*48489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 361*48489980SSeiya Wang clocks = <&clk26m>, 362*48489980SSeiya Wang <&clk26m>, 363*48489980SSeiya Wang <&clk26m>; 364*48489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 365*48489980SSeiya Wang status = "disabled"; 366*48489980SSeiya Wang }; 367*48489980SSeiya Wang 368*48489980SSeiya Wang spi7: spi@1101e000 { 369*48489980SSeiya Wang compatible = "mediatek,mt8192-spi", 370*48489980SSeiya Wang "mediatek,mt6765-spi"; 371*48489980SSeiya Wang #address-cells = <1>; 372*48489980SSeiya Wang #size-cells = <0>; 373*48489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 374*48489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 375*48489980SSeiya Wang clocks = <&clk26m>, 376*48489980SSeiya Wang <&clk26m>, 377*48489980SSeiya Wang <&clk26m>; 378*48489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 379*48489980SSeiya Wang status = "disabled"; 380*48489980SSeiya Wang }; 381*48489980SSeiya Wang 382*48489980SSeiya Wang i2c3: i2c3@11cb0000 { 383*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 384*48489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 385*48489980SSeiya Wang <0 0x10217300 0 0x80>; 386*48489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 387*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 388*48489980SSeiya Wang clock-names = "main", "dma"; 389*48489980SSeiya Wang clock-div = <1>; 390*48489980SSeiya Wang #address-cells = <1>; 391*48489980SSeiya Wang #size-cells = <0>; 392*48489980SSeiya Wang status = "disabled"; 393*48489980SSeiya Wang }; 394*48489980SSeiya Wang 395*48489980SSeiya Wang i2c7: i2c7@11d00000 { 396*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 397*48489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 398*48489980SSeiya Wang <0 0x10217600 0 0x180>; 399*48489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 400*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 401*48489980SSeiya Wang clock-names = "main", "dma"; 402*48489980SSeiya Wang clock-div = <1>; 403*48489980SSeiya Wang #address-cells = <1>; 404*48489980SSeiya Wang #size-cells = <0>; 405*48489980SSeiya Wang status = "disabled"; 406*48489980SSeiya Wang }; 407*48489980SSeiya Wang 408*48489980SSeiya Wang i2c8: i2c8@11d01000 { 409*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 410*48489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 411*48489980SSeiya Wang <0 0x10217780 0 0x180>; 412*48489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 413*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 414*48489980SSeiya Wang clock-names = "main", "dma"; 415*48489980SSeiya Wang clock-div = <1>; 416*48489980SSeiya Wang #address-cells = <1>; 417*48489980SSeiya Wang #size-cells = <0>; 418*48489980SSeiya Wang status = "disabled"; 419*48489980SSeiya Wang }; 420*48489980SSeiya Wang 421*48489980SSeiya Wang i2c9: i2c9@11d02000 { 422*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 423*48489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 424*48489980SSeiya Wang <0 0x10217900 0 0x180>; 425*48489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 426*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 427*48489980SSeiya Wang clock-names = "main", "dma"; 428*48489980SSeiya Wang clock-div = <1>; 429*48489980SSeiya Wang #address-cells = <1>; 430*48489980SSeiya Wang #size-cells = <0>; 431*48489980SSeiya Wang status = "disabled"; 432*48489980SSeiya Wang }; 433*48489980SSeiya Wang 434*48489980SSeiya Wang i2c1: i2c1@11d20000 { 435*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 436*48489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 437*48489980SSeiya Wang <0 0x10217100 0 0x80>; 438*48489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 439*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 440*48489980SSeiya Wang clock-names = "main", "dma"; 441*48489980SSeiya Wang clock-div = <1>; 442*48489980SSeiya Wang #address-cells = <1>; 443*48489980SSeiya Wang #size-cells = <0>; 444*48489980SSeiya Wang status = "disabled"; 445*48489980SSeiya Wang }; 446*48489980SSeiya Wang 447*48489980SSeiya Wang i2c2: i2c2@11d21000 { 448*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 449*48489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 450*48489980SSeiya Wang <0 0x10217180 0 0x180>; 451*48489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 452*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 453*48489980SSeiya Wang clock-names = "main", "dma"; 454*48489980SSeiya Wang clock-div = <1>; 455*48489980SSeiya Wang #address-cells = <1>; 456*48489980SSeiya Wang #size-cells = <0>; 457*48489980SSeiya Wang status = "disabled"; 458*48489980SSeiya Wang }; 459*48489980SSeiya Wang 460*48489980SSeiya Wang i2c4: i2c4@11d22000 { 461*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 462*48489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 463*48489980SSeiya Wang <0 0x10217380 0 0x180>; 464*48489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 465*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 466*48489980SSeiya Wang clock-names = "main", "dma"; 467*48489980SSeiya Wang clock-div = <1>; 468*48489980SSeiya Wang #address-cells = <1>; 469*48489980SSeiya Wang #size-cells = <0>; 470*48489980SSeiya Wang status = "disabled"; 471*48489980SSeiya Wang }; 472*48489980SSeiya Wang 473*48489980SSeiya Wang i2c5: i2c5@11e00000 { 474*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 475*48489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 476*48489980SSeiya Wang <0 0x10217500 0 0x80>; 477*48489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 478*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 479*48489980SSeiya Wang clock-names = "main", "dma"; 480*48489980SSeiya Wang clock-div = <1>; 481*48489980SSeiya Wang #address-cells = <1>; 482*48489980SSeiya Wang #size-cells = <0>; 483*48489980SSeiya Wang status = "disabled"; 484*48489980SSeiya Wang }; 485*48489980SSeiya Wang 486*48489980SSeiya Wang i2c0: i2c0@11f00000 { 487*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 488*48489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 489*48489980SSeiya Wang <0 0x10217080 0 0x80>; 490*48489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 491*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 492*48489980SSeiya Wang clock-names = "main", "dma"; 493*48489980SSeiya Wang clock-div = <1>; 494*48489980SSeiya Wang #address-cells = <1>; 495*48489980SSeiya Wang #size-cells = <0>; 496*48489980SSeiya Wang status = "disabled"; 497*48489980SSeiya Wang }; 498*48489980SSeiya Wang 499*48489980SSeiya Wang i2c6: i2c6@11f01000 { 500*48489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 501*48489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 502*48489980SSeiya Wang <0 0x10217580 0 0x80>; 503*48489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 504*48489980SSeiya Wang clocks = <&clk26m>, <&clk26m>; 505*48489980SSeiya Wang clock-names = "main", "dma"; 506*48489980SSeiya Wang clock-div = <1>; 507*48489980SSeiya Wang #address-cells = <1>; 508*48489980SSeiya Wang #size-cells = <0>; 509*48489980SSeiya Wang status = "disabled"; 510*48489980SSeiya Wang }; 511*48489980SSeiya Wang }; 512*48489980SSeiya Wang}; 513