148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 114a65b0f1SAllen-KH Cheng#include <dt-bindings/memory/mt8192-larb-port.h> 1248489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 13e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h> 14994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 1548489980SSeiya Wang 1648489980SSeiya Wang/ { 1748489980SSeiya Wang compatible = "mediatek,mt8192"; 1848489980SSeiya Wang interrupt-parent = <&gic>; 1948489980SSeiya Wang #address-cells = <2>; 2048489980SSeiya Wang #size-cells = <2>; 2148489980SSeiya Wang 2248489980SSeiya Wang clk26m: oscillator0 { 2348489980SSeiya Wang compatible = "fixed-clock"; 2448489980SSeiya Wang #clock-cells = <0>; 2548489980SSeiya Wang clock-frequency = <26000000>; 2648489980SSeiya Wang clock-output-names = "clk26m"; 2748489980SSeiya Wang }; 2848489980SSeiya Wang 2948489980SSeiya Wang clk32k: oscillator1 { 3048489980SSeiya Wang compatible = "fixed-clock"; 3148489980SSeiya Wang #clock-cells = <0>; 3248489980SSeiya Wang clock-frequency = <32768>; 3348489980SSeiya Wang clock-output-names = "clk32k"; 3448489980SSeiya Wang }; 3548489980SSeiya Wang 3648489980SSeiya Wang cpus { 3748489980SSeiya Wang #address-cells = <1>; 3848489980SSeiya Wang #size-cells = <0>; 3948489980SSeiya Wang 4048489980SSeiya Wang cpu0: cpu@0 { 4148489980SSeiya Wang device_type = "cpu"; 4248489980SSeiya Wang compatible = "arm,cortex-a55"; 4348489980SSeiya Wang reg = <0x000>; 4448489980SSeiya Wang enable-method = "psci"; 4548489980SSeiya Wang clock-frequency = <1701000000>; 46*399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 4748489980SSeiya Wang next-level-cache = <&l2_0>; 4848489980SSeiya Wang capacity-dmips-mhz = <530>; 4948489980SSeiya Wang }; 5048489980SSeiya Wang 5148489980SSeiya Wang cpu1: cpu@100 { 5248489980SSeiya Wang device_type = "cpu"; 5348489980SSeiya Wang compatible = "arm,cortex-a55"; 5448489980SSeiya Wang reg = <0x100>; 5548489980SSeiya Wang enable-method = "psci"; 5648489980SSeiya Wang clock-frequency = <1701000000>; 57*399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 5848489980SSeiya Wang next-level-cache = <&l2_0>; 5948489980SSeiya Wang capacity-dmips-mhz = <530>; 6048489980SSeiya Wang }; 6148489980SSeiya Wang 6248489980SSeiya Wang cpu2: cpu@200 { 6348489980SSeiya Wang device_type = "cpu"; 6448489980SSeiya Wang compatible = "arm,cortex-a55"; 6548489980SSeiya Wang reg = <0x200>; 6648489980SSeiya Wang enable-method = "psci"; 6748489980SSeiya Wang clock-frequency = <1701000000>; 68*399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 6948489980SSeiya Wang next-level-cache = <&l2_0>; 7048489980SSeiya Wang capacity-dmips-mhz = <530>; 7148489980SSeiya Wang }; 7248489980SSeiya Wang 7348489980SSeiya Wang cpu3: cpu@300 { 7448489980SSeiya Wang device_type = "cpu"; 7548489980SSeiya Wang compatible = "arm,cortex-a55"; 7648489980SSeiya Wang reg = <0x300>; 7748489980SSeiya Wang enable-method = "psci"; 7848489980SSeiya Wang clock-frequency = <1701000000>; 79*399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 8048489980SSeiya Wang next-level-cache = <&l2_0>; 8148489980SSeiya Wang capacity-dmips-mhz = <530>; 8248489980SSeiya Wang }; 8348489980SSeiya Wang 8448489980SSeiya Wang cpu4: cpu@400 { 8548489980SSeiya Wang device_type = "cpu"; 8648489980SSeiya Wang compatible = "arm,cortex-a76"; 8748489980SSeiya Wang reg = <0x400>; 8848489980SSeiya Wang enable-method = "psci"; 8948489980SSeiya Wang clock-frequency = <2171000000>; 90*399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 9148489980SSeiya Wang next-level-cache = <&l2_1>; 9248489980SSeiya Wang capacity-dmips-mhz = <1024>; 9348489980SSeiya Wang }; 9448489980SSeiya Wang 9548489980SSeiya Wang cpu5: cpu@500 { 9648489980SSeiya Wang device_type = "cpu"; 9748489980SSeiya Wang compatible = "arm,cortex-a76"; 9848489980SSeiya Wang reg = <0x500>; 9948489980SSeiya Wang enable-method = "psci"; 10048489980SSeiya Wang clock-frequency = <2171000000>; 101*399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 10248489980SSeiya Wang next-level-cache = <&l2_1>; 10348489980SSeiya Wang capacity-dmips-mhz = <1024>; 10448489980SSeiya Wang }; 10548489980SSeiya Wang 10648489980SSeiya Wang cpu6: cpu@600 { 10748489980SSeiya Wang device_type = "cpu"; 10848489980SSeiya Wang compatible = "arm,cortex-a76"; 10948489980SSeiya Wang reg = <0x600>; 11048489980SSeiya Wang enable-method = "psci"; 11148489980SSeiya Wang clock-frequency = <2171000000>; 112*399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 11348489980SSeiya Wang next-level-cache = <&l2_1>; 11448489980SSeiya Wang capacity-dmips-mhz = <1024>; 11548489980SSeiya Wang }; 11648489980SSeiya Wang 11748489980SSeiya Wang cpu7: cpu@700 { 11848489980SSeiya Wang device_type = "cpu"; 11948489980SSeiya Wang compatible = "arm,cortex-a76"; 12048489980SSeiya Wang reg = <0x700>; 12148489980SSeiya Wang enable-method = "psci"; 12248489980SSeiya Wang clock-frequency = <2171000000>; 123*399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 12448489980SSeiya Wang next-level-cache = <&l2_1>; 12548489980SSeiya Wang capacity-dmips-mhz = <1024>; 12648489980SSeiya Wang }; 12748489980SSeiya Wang 12848489980SSeiya Wang cpu-map { 12948489980SSeiya Wang cluster0 { 13048489980SSeiya Wang core0 { 13148489980SSeiya Wang cpu = <&cpu0>; 13248489980SSeiya Wang }; 13348489980SSeiya Wang core1 { 13448489980SSeiya Wang cpu = <&cpu1>; 13548489980SSeiya Wang }; 13648489980SSeiya Wang core2 { 13748489980SSeiya Wang cpu = <&cpu2>; 13848489980SSeiya Wang }; 13948489980SSeiya Wang core3 { 14048489980SSeiya Wang cpu = <&cpu3>; 14148489980SSeiya Wang }; 14248489980SSeiya Wang }; 14348489980SSeiya Wang 14448489980SSeiya Wang cluster1 { 14548489980SSeiya Wang core0 { 14648489980SSeiya Wang cpu = <&cpu4>; 14748489980SSeiya Wang }; 14848489980SSeiya Wang core1 { 14948489980SSeiya Wang cpu = <&cpu5>; 15048489980SSeiya Wang }; 15148489980SSeiya Wang core2 { 15248489980SSeiya Wang cpu = <&cpu6>; 15348489980SSeiya Wang }; 15448489980SSeiya Wang core3 { 15548489980SSeiya Wang cpu = <&cpu7>; 15648489980SSeiya Wang }; 15748489980SSeiya Wang }; 15848489980SSeiya Wang }; 15948489980SSeiya Wang 16048489980SSeiya Wang l2_0: l2-cache0 { 16148489980SSeiya Wang compatible = "cache"; 16248489980SSeiya Wang next-level-cache = <&l3_0>; 16348489980SSeiya Wang }; 16448489980SSeiya Wang 16548489980SSeiya Wang l2_1: l2-cache1 { 16648489980SSeiya Wang compatible = "cache"; 16748489980SSeiya Wang next-level-cache = <&l3_0>; 16848489980SSeiya Wang }; 16948489980SSeiya Wang 17048489980SSeiya Wang l3_0: l3-cache { 17148489980SSeiya Wang compatible = "cache"; 17248489980SSeiya Wang }; 1739260918dSJames Liao 1749260918dSJames Liao idle-states { 1759260918dSJames Liao entry-method = "arm,psci"; 176*399e23adSNícolas F. R. A. Prado cpu_sleep_l: cpu-sleep-l { 1779260918dSJames Liao compatible = "arm,idle-state"; 1789260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1799260918dSJames Liao local-timer-stop; 1809260918dSJames Liao entry-latency-us = <55>; 1819260918dSJames Liao exit-latency-us = <140>; 1829260918dSJames Liao min-residency-us = <780>; 1839260918dSJames Liao }; 184*399e23adSNícolas F. R. A. Prado cpu_sleep_b: cpu-sleep-b { 1859260918dSJames Liao compatible = "arm,idle-state"; 1869260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1879260918dSJames Liao local-timer-stop; 1889260918dSJames Liao entry-latency-us = <35>; 1899260918dSJames Liao exit-latency-us = <145>; 1909260918dSJames Liao min-residency-us = <720>; 1919260918dSJames Liao }; 192*399e23adSNícolas F. R. A. Prado cluster_sleep_l: cluster-sleep-l { 1939260918dSJames Liao compatible = "arm,idle-state"; 1949260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 1959260918dSJames Liao local-timer-stop; 1969260918dSJames Liao entry-latency-us = <60>; 1979260918dSJames Liao exit-latency-us = <155>; 1989260918dSJames Liao min-residency-us = <860>; 1999260918dSJames Liao }; 200*399e23adSNícolas F. R. A. Prado cluster_sleep_b: cluster-sleep-b { 2019260918dSJames Liao compatible = "arm,idle-state"; 2029260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2039260918dSJames Liao local-timer-stop; 2049260918dSJames Liao entry-latency-us = <40>; 2059260918dSJames Liao exit-latency-us = <155>; 2069260918dSJames Liao min-residency-us = <780>; 2079260918dSJames Liao }; 2089260918dSJames Liao }; 20948489980SSeiya Wang }; 21048489980SSeiya Wang 21148489980SSeiya Wang pmu-a55 { 21248489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 21348489980SSeiya Wang interrupt-parent = <&gic>; 21448489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 21548489980SSeiya Wang }; 21648489980SSeiya Wang 21748489980SSeiya Wang pmu-a76 { 21848489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 21948489980SSeiya Wang interrupt-parent = <&gic>; 22048489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 22148489980SSeiya Wang }; 22248489980SSeiya Wang 22348489980SSeiya Wang psci { 22448489980SSeiya Wang compatible = "arm,psci-1.0"; 22548489980SSeiya Wang method = "smc"; 22648489980SSeiya Wang }; 22748489980SSeiya Wang 22848489980SSeiya Wang timer: timer { 22948489980SSeiya Wang compatible = "arm,armv8-timer"; 23048489980SSeiya Wang interrupt-parent = <&gic>; 23148489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 23248489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 23348489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 23448489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 23548489980SSeiya Wang clock-frequency = <13000000>; 23648489980SSeiya Wang }; 23748489980SSeiya Wang 23848489980SSeiya Wang soc { 23948489980SSeiya Wang #address-cells = <2>; 24048489980SSeiya Wang #size-cells = <2>; 24148489980SSeiya Wang compatible = "simple-bus"; 24248489980SSeiya Wang ranges; 24348489980SSeiya Wang 24448489980SSeiya Wang gic: interrupt-controller@c000000 { 24548489980SSeiya Wang compatible = "arm,gic-v3"; 24648489980SSeiya Wang #interrupt-cells = <4>; 24748489980SSeiya Wang #redistributor-regions = <1>; 24848489980SSeiya Wang interrupt-parent = <&gic>; 24948489980SSeiya Wang interrupt-controller; 25048489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 25148489980SSeiya Wang <0 0x0c040000 0 0x200000>; 25248489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 25348489980SSeiya Wang 25448489980SSeiya Wang ppi-partitions { 25548489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 25648489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 25748489980SSeiya Wang }; 25848489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 25948489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 26048489980SSeiya Wang }; 26148489980SSeiya Wang }; 26248489980SSeiya Wang }; 26348489980SSeiya Wang 2645d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 2655d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 2665d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 2675d2b897bSChun-Jie Chen #clock-cells = <1>; 2685d2b897bSChun-Jie Chen }; 2695d2b897bSChun-Jie Chen 2705d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 2715d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 2725d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 2735d2b897bSChun-Jie Chen #clock-cells = <1>; 274a30cc07fSRex-BC Chen #reset-cells = <1>; 2755d2b897bSChun-Jie Chen }; 2765d2b897bSChun-Jie Chen 2775d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 2785d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 2795d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 2805d2b897bSChun-Jie Chen #clock-cells = <1>; 2815d2b897bSChun-Jie Chen }; 2825d2b897bSChun-Jie Chen 28348489980SSeiya Wang pio: pinctrl@10005000 { 28448489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 28548489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 28648489980SSeiya Wang <0 0x11c20000 0 0x1000>, 28748489980SSeiya Wang <0 0x11d10000 0 0x1000>, 28848489980SSeiya Wang <0 0x11d30000 0 0x1000>, 28948489980SSeiya Wang <0 0x11d40000 0 0x1000>, 29048489980SSeiya Wang <0 0x11e20000 0 0x1000>, 29148489980SSeiya Wang <0 0x11e70000 0 0x1000>, 29248489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 29348489980SSeiya Wang <0 0x11f20000 0 0x1000>, 29448489980SSeiya Wang <0 0x11f30000 0 0x1000>, 29548489980SSeiya Wang <0 0x1000b000 0 0x1000>; 29648489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 29748489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 29848489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 29948489980SSeiya Wang "iocfg_tl", "eint"; 30048489980SSeiya Wang gpio-controller; 30148489980SSeiya Wang #gpio-cells = <2>; 30248489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 30348489980SSeiya Wang interrupt-controller; 30448489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 30548489980SSeiya Wang #interrupt-cells = <2>; 30648489980SSeiya Wang }; 30748489980SSeiya Wang 308994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 309994a71a3SChun-Jie Chen compatible = "syscon", "simple-mfd"; 310994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 311994a71a3SChun-Jie Chen #power-domain-cells = <1>; 312994a71a3SChun-Jie Chen 313994a71a3SChun-Jie Chen /* System Power Manager */ 314994a71a3SChun-Jie Chen spm: power-controller { 315994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 316994a71a3SChun-Jie Chen #address-cells = <1>; 317994a71a3SChun-Jie Chen #size-cells = <0>; 318994a71a3SChun-Jie Chen #power-domain-cells = <1>; 319994a71a3SChun-Jie Chen 320994a71a3SChun-Jie Chen /* power domain of the SoC */ 321994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 322994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 323994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 324994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 325994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 326994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 327994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 328994a71a3SChun-Jie Chen #power-domain-cells = <0>; 329994a71a3SChun-Jie Chen }; 330994a71a3SChun-Jie Chen 331994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 332994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 333994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 334994a71a3SChun-Jie Chen clock-names = "conn"; 335994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 336994a71a3SChun-Jie Chen #power-domain-cells = <0>; 337994a71a3SChun-Jie Chen }; 338994a71a3SChun-Jie Chen 339994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG0 { 340994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 341994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 342994a71a3SChun-Jie Chen clock-names = "mfg"; 343994a71a3SChun-Jie Chen #address-cells = <1>; 344994a71a3SChun-Jie Chen #size-cells = <0>; 345994a71a3SChun-Jie Chen #power-domain-cells = <1>; 346994a71a3SChun-Jie Chen 347994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG1 { 348994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 349994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 350994a71a3SChun-Jie Chen #address-cells = <1>; 351994a71a3SChun-Jie Chen #size-cells = <0>; 352994a71a3SChun-Jie Chen #power-domain-cells = <1>; 353994a71a3SChun-Jie Chen 354994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 355994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 356994a71a3SChun-Jie Chen #power-domain-cells = <0>; 357994a71a3SChun-Jie Chen }; 358994a71a3SChun-Jie Chen 359994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 360994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 361994a71a3SChun-Jie Chen #power-domain-cells = <0>; 362994a71a3SChun-Jie Chen }; 363994a71a3SChun-Jie Chen 364994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 365994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 366994a71a3SChun-Jie Chen #power-domain-cells = <0>; 367994a71a3SChun-Jie Chen }; 368994a71a3SChun-Jie Chen 369994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 370994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 371994a71a3SChun-Jie Chen #power-domain-cells = <0>; 372994a71a3SChun-Jie Chen }; 373994a71a3SChun-Jie Chen 374994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 375994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 376994a71a3SChun-Jie Chen #power-domain-cells = <0>; 377994a71a3SChun-Jie Chen }; 378994a71a3SChun-Jie Chen }; 379994a71a3SChun-Jie Chen }; 380994a71a3SChun-Jie Chen 381994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 382994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 383994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 384994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 385994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 386994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 387994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 388994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 389994a71a3SChun-Jie Chen "disp-3"; 390994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 391994a71a3SChun-Jie Chen #address-cells = <1>; 392994a71a3SChun-Jie Chen #size-cells = <0>; 393994a71a3SChun-Jie Chen #power-domain-cells = <1>; 394994a71a3SChun-Jie Chen 395994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 396994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 397994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 398994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 399994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 400994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 401994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 402994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 403994a71a3SChun-Jie Chen "ipe-3"; 404994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 405994a71a3SChun-Jie Chen #power-domain-cells = <0>; 406994a71a3SChun-Jie Chen }; 407994a71a3SChun-Jie Chen 408994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 409994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 410994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 411994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 412994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 413994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 414994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 415994a71a3SChun-Jie Chen #power-domain-cells = <0>; 416994a71a3SChun-Jie Chen }; 417994a71a3SChun-Jie Chen 418994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 419994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 420994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 421994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 422994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 423994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 424994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 425994a71a3SChun-Jie Chen #power-domain-cells = <0>; 426994a71a3SChun-Jie Chen }; 427994a71a3SChun-Jie Chen 428994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 429994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 430994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 431994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 432994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 433994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 434994a71a3SChun-Jie Chen #power-domain-cells = <0>; 435994a71a3SChun-Jie Chen }; 436994a71a3SChun-Jie Chen 437994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 438994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 439994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 440994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 441994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 442994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 443994a71a3SChun-Jie Chen #power-domain-cells = <0>; 444994a71a3SChun-Jie Chen }; 445994a71a3SChun-Jie Chen 446994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 447994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 448994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 449994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 450994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 451994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 452994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 453994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 454994a71a3SChun-Jie Chen #address-cells = <1>; 455994a71a3SChun-Jie Chen #size-cells = <0>; 456994a71a3SChun-Jie Chen #power-domain-cells = <1>; 457994a71a3SChun-Jie Chen 458994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 459994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 460994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 461994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 462994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 463994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 464994a71a3SChun-Jie Chen "vdec2-2"; 465994a71a3SChun-Jie Chen #power-domain-cells = <0>; 466994a71a3SChun-Jie Chen }; 467994a71a3SChun-Jie Chen }; 468994a71a3SChun-Jie Chen 469994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 470994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 471994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 472994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 473994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 474994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 475994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 476994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 477994a71a3SChun-Jie Chen "cam-3"; 478994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 479994a71a3SChun-Jie Chen #address-cells = <1>; 480994a71a3SChun-Jie Chen #size-cells = <0>; 481994a71a3SChun-Jie Chen #power-domain-cells = <1>; 482994a71a3SChun-Jie Chen 483994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 484994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 485994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 486994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 487994a71a3SChun-Jie Chen #power-domain-cells = <0>; 488994a71a3SChun-Jie Chen }; 489994a71a3SChun-Jie Chen 490994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 491994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 492994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 493994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 494994a71a3SChun-Jie Chen #power-domain-cells = <0>; 495994a71a3SChun-Jie Chen }; 496994a71a3SChun-Jie Chen 497994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 498994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 499994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 500994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 501994a71a3SChun-Jie Chen #power-domain-cells = <0>; 502994a71a3SChun-Jie Chen }; 503994a71a3SChun-Jie Chen }; 504994a71a3SChun-Jie Chen }; 505994a71a3SChun-Jie Chen }; 506994a71a3SChun-Jie Chen }; 507994a71a3SChun-Jie Chen 508d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 509d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 510d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 511d1986fbdSAllen-KH Cheng #reset-cells = <1>; 512d1986fbdSAllen-KH Cheng }; 513d1986fbdSAllen-KH Cheng 5145d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 5155d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 5165d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 5175d2b897bSChun-Jie Chen #clock-cells = <1>; 5185d2b897bSChun-Jie Chen }; 5195d2b897bSChun-Jie Chen 52048489980SSeiya Wang systimer: timer@10017000 { 52148489980SSeiya Wang compatible = "mediatek,mt8192-timer", 52248489980SSeiya Wang "mediatek,mt6765-timer"; 52348489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 52448489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 525dde3c175SAllen-KH Cheng clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 52648489980SSeiya Wang clock-names = "clk13m"; 52748489980SSeiya Wang }; 52848489980SSeiya Wang 529261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 530261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 531261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 532261691b4SAllen-KH Cheng reg-names = "pwrap"; 533261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 534261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 535261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 536261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 537261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 538261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 539261691b4SAllen-KH Cheng }; 540261691b4SAllen-KH Cheng 541a8bbcf70SAllen-KH Cheng spmi: spmi@10027000 { 542a8bbcf70SAllen-KH Cheng compatible = "mediatek,mt6873-spmi"; 543a8bbcf70SAllen-KH Cheng reg = <0 0x10027000 0 0x000e00>, 544a8bbcf70SAllen-KH Cheng <0 0x10029000 0 0x000100>; 545a8bbcf70SAllen-KH Cheng reg-names = "pmif", "spmimst"; 546a8bbcf70SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 547a8bbcf70SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>, 548a8bbcf70SAllen-KH Cheng <&topckgen CLK_TOP_SPMI_MST_SEL>; 549a8bbcf70SAllen-KH Cheng clock-names = "pmif_sys_ck", 550a8bbcf70SAllen-KH Cheng "pmif_tmr_ck", 551a8bbcf70SAllen-KH Cheng "spmimst_clk_mux"; 552a8bbcf70SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 553a8bbcf70SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 554a8bbcf70SAllen-KH Cheng }; 555a8bbcf70SAllen-KH Cheng 5565d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 5575d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 5585d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 5595d2b897bSChun-Jie Chen #clock-cells = <1>; 5605d2b897bSChun-Jie Chen }; 5615d2b897bSChun-Jie Chen 56248489980SSeiya Wang uart0: serial@11002000 { 56348489980SSeiya Wang compatible = "mediatek,mt8192-uart", 56448489980SSeiya Wang "mediatek,mt6577-uart"; 56548489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 56648489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 56773ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 56848489980SSeiya Wang clock-names = "baud", "bus"; 56948489980SSeiya Wang status = "disabled"; 57048489980SSeiya Wang }; 57148489980SSeiya Wang 57248489980SSeiya Wang uart1: serial@11003000 { 57348489980SSeiya Wang compatible = "mediatek,mt8192-uart", 57448489980SSeiya Wang "mediatek,mt6577-uart"; 57548489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 57648489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 57773ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 57848489980SSeiya Wang clock-names = "baud", "bus"; 57948489980SSeiya Wang status = "disabled"; 58048489980SSeiya Wang }; 58148489980SSeiya Wang 5825d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 5835d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 5845d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 5855d2b897bSChun-Jie Chen #clock-cells = <1>; 5865d2b897bSChun-Jie Chen }; 5875d2b897bSChun-Jie Chen 58848489980SSeiya Wang spi0: spi@1100a000 { 58948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 59048489980SSeiya Wang "mediatek,mt6765-spi"; 59148489980SSeiya Wang #address-cells = <1>; 59248489980SSeiya Wang #size-cells = <0>; 59348489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 59448489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 5957f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5967f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5977f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 59848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 59948489980SSeiya Wang status = "disabled"; 60048489980SSeiya Wang }; 60148489980SSeiya Wang 60248489980SSeiya Wang spi1: spi@11010000 { 60348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 60448489980SSeiya Wang "mediatek,mt6765-spi"; 60548489980SSeiya Wang #address-cells = <1>; 60648489980SSeiya Wang #size-cells = <0>; 60748489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 60848489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 6097f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6107f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6117f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 61248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 61348489980SSeiya Wang status = "disabled"; 61448489980SSeiya Wang }; 61548489980SSeiya Wang 61648489980SSeiya Wang spi2: spi@11012000 { 61748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 61848489980SSeiya Wang "mediatek,mt6765-spi"; 61948489980SSeiya Wang #address-cells = <1>; 62048489980SSeiya Wang #size-cells = <0>; 62148489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 62248489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 6237f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6247f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6257f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 62648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 62748489980SSeiya Wang status = "disabled"; 62848489980SSeiya Wang }; 62948489980SSeiya Wang 63048489980SSeiya Wang spi3: spi@11013000 { 63148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 63248489980SSeiya Wang "mediatek,mt6765-spi"; 63348489980SSeiya Wang #address-cells = <1>; 63448489980SSeiya Wang #size-cells = <0>; 63548489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 63648489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 6377f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6387f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6397f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 64048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 64148489980SSeiya Wang status = "disabled"; 64248489980SSeiya Wang }; 64348489980SSeiya Wang 64448489980SSeiya Wang spi4: spi@11018000 { 64548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 64648489980SSeiya Wang "mediatek,mt6765-spi"; 64748489980SSeiya Wang #address-cells = <1>; 64848489980SSeiya Wang #size-cells = <0>; 64948489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 65048489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 6517f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6527f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6537f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 65448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 65548489980SSeiya Wang status = "disabled"; 65648489980SSeiya Wang }; 65748489980SSeiya Wang 65848489980SSeiya Wang spi5: spi@11019000 { 65948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 66048489980SSeiya Wang "mediatek,mt6765-spi"; 66148489980SSeiya Wang #address-cells = <1>; 66248489980SSeiya Wang #size-cells = <0>; 66348489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 66448489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 6657f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6667f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6677f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 66848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 66948489980SSeiya Wang status = "disabled"; 67048489980SSeiya Wang }; 67148489980SSeiya Wang 67248489980SSeiya Wang spi6: spi@1101d000 { 67348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 67448489980SSeiya Wang "mediatek,mt6765-spi"; 67548489980SSeiya Wang #address-cells = <1>; 67648489980SSeiya Wang #size-cells = <0>; 67748489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 67848489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 6797f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6807f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6817f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 68248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 68348489980SSeiya Wang status = "disabled"; 68448489980SSeiya Wang }; 68548489980SSeiya Wang 68648489980SSeiya Wang spi7: spi@1101e000 { 68748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 68848489980SSeiya Wang "mediatek,mt6765-spi"; 68948489980SSeiya Wang #address-cells = <1>; 69048489980SSeiya Wang #size-cells = <0>; 69148489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 69248489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 6937f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6947f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6957f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 69648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 69748489980SSeiya Wang status = "disabled"; 69848489980SSeiya Wang }; 69948489980SSeiya Wang 700c63556ecSAllen-KH Cheng scp: scp@10500000 { 701c63556ecSAllen-KH Cheng compatible = "mediatek,mt8192-scp"; 702c63556ecSAllen-KH Cheng reg = <0 0x10500000 0 0x100000>, 703c7510476SNícolas F. R. A. Prado <0 0x10720000 0 0xe0000>, 704c7510476SNícolas F. R. A. Prado <0 0x10700000 0 0x8000>; 705c7510476SNícolas F. R. A. Prado reg-names = "sram", "cfg", "l1tcm"; 706c63556ecSAllen-KH Cheng interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 707c63556ecSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SCPSYS>; 708c63556ecSAllen-KH Cheng clock-names = "main"; 709c63556ecSAllen-KH Cheng status = "disabled"; 710c63556ecSAllen-KH Cheng }; 711c63556ecSAllen-KH Cheng 712e5aac225SAllen-KH Cheng xhci: usb@11200000 { 713e5aac225SAllen-KH Cheng compatible = "mediatek,mt8192-xhci", 714e5aac225SAllen-KH Cheng "mediatek,mtk-xhci"; 715e5aac225SAllen-KH Cheng reg = <0 0x11200000 0 0x1000>, 716e5aac225SAllen-KH Cheng <0 0x11203e00 0 0x0100>; 717e5aac225SAllen-KH Cheng reg-names = "mac", "ippc"; 718e5aac225SAllen-KH Cheng interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 719e5aac225SAllen-KH Cheng interrupt-names = "host"; 720e5aac225SAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>, 721e5aac225SAllen-KH Cheng <&u3port0 PHY_TYPE_USB3>; 722e5aac225SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 723e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 724e5aac225SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 725e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 726e5aac225SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SSUSB>, 727e5aac225SAllen-KH Cheng <&infracfg CLK_INFRA_SSUSB_XHCI>, 728e5aac225SAllen-KH Cheng <&apmixedsys CLK_APMIXED_USBPLL>; 729e5aac225SAllen-KH Cheng clock-names = "sys_ck", "xhci_ck", "ref_ck"; 730e5aac225SAllen-KH Cheng wakeup-source; 731e5aac225SAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 102>; 732e5aac225SAllen-KH Cheng status = "disabled"; 733e5aac225SAllen-KH Cheng }; 734e5aac225SAllen-KH Cheng 7351afd9b62SAllen-KH Cheng audsys: syscon@11210000 { 7361afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audsys", "syscon"; 7371afd9b62SAllen-KH Cheng reg = <0 0x11210000 0 0x2000>; 7381afd9b62SAllen-KH Cheng #clock-cells = <1>; 7391afd9b62SAllen-KH Cheng 7401afd9b62SAllen-KH Cheng afe: mt8192-afe-pcm { 7411afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audio"; 7421afd9b62SAllen-KH Cheng interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 7431afd9b62SAllen-KH Cheng resets = <&watchdog 17>; 7441afd9b62SAllen-KH Cheng reset-names = "audiosys"; 7451afd9b62SAllen-KH Cheng mediatek,apmixedsys = <&apmixedsys>; 7461afd9b62SAllen-KH Cheng mediatek,infracfg = <&infracfg>; 7471afd9b62SAllen-KH Cheng mediatek,topckgen = <&topckgen>; 7481afd9b62SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 7491afd9b62SAllen-KH Cheng clocks = <&audsys CLK_AUD_AFE>, 7501afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC>, 7511afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_PREDIS>, 7521afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC>, 7531afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC>, 7541afd9b62SAllen-KH Cheng <&audsys CLK_AUD_22M>, 7551afd9b62SAllen-KH Cheng <&audsys CLK_AUD_24M>, 7561afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL_TUNER>, 7571afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL2_TUNER>, 7581afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TDM>, 7591afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TML>, 7601afd9b62SAllen-KH Cheng <&audsys CLK_AUD_NLE>, 7611afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_HIRES>, 7621afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES>, 7631afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES_TML>, 7641afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 7651afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC>, 7661afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_PREDIS>, 7671afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_TML>, 7681afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_HIRES>, 7691afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO>, 7701afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO_26M_B>, 7711afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_SEL>, 7721afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 7731afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D4_D4>, 7741afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_1_SEL>, 7751afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1>, 7761afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_2_SEL>, 7771afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2>, 7781afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 7791afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1_D4>, 7801afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 7811afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2_D4>, 7821afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 7831afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 7841afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 7851afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 7861afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 7871afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 7881afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 7891afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 7901afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 7911afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 7921afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV0>, 7931afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV1>, 7941afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV2>, 7951afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV3>, 7961afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV4>, 7971afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIVB>, 7981afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV5>, 7991afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV6>, 8001afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV7>, 8011afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV8>, 8021afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV9>, 8031afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_H_SEL>, 8041afd9b62SAllen-KH Cheng <&clk26m>; 8051afd9b62SAllen-KH Cheng clock-names = "aud_afe_clk", 8061afd9b62SAllen-KH Cheng "aud_dac_clk", 8071afd9b62SAllen-KH Cheng "aud_dac_predis_clk", 8081afd9b62SAllen-KH Cheng "aud_adc_clk", 8091afd9b62SAllen-KH Cheng "aud_adda6_adc_clk", 8101afd9b62SAllen-KH Cheng "aud_apll22m_clk", 8111afd9b62SAllen-KH Cheng "aud_apll24m_clk", 8121afd9b62SAllen-KH Cheng "aud_apll1_tuner_clk", 8131afd9b62SAllen-KH Cheng "aud_apll2_tuner_clk", 8141afd9b62SAllen-KH Cheng "aud_tdm_clk", 8151afd9b62SAllen-KH Cheng "aud_tml_clk", 8161afd9b62SAllen-KH Cheng "aud_nle", 8171afd9b62SAllen-KH Cheng "aud_dac_hires_clk", 8181afd9b62SAllen-KH Cheng "aud_adc_hires_clk", 8191afd9b62SAllen-KH Cheng "aud_adc_hires_tml", 8201afd9b62SAllen-KH Cheng "aud_adda6_adc_hires_clk", 8211afd9b62SAllen-KH Cheng "aud_3rd_dac_clk", 8221afd9b62SAllen-KH Cheng "aud_3rd_dac_predis_clk", 8231afd9b62SAllen-KH Cheng "aud_3rd_dac_tml", 8241afd9b62SAllen-KH Cheng "aud_3rd_dac_hires_clk", 8251afd9b62SAllen-KH Cheng "aud_infra_clk", 8261afd9b62SAllen-KH Cheng "aud_infra_26m_clk", 8271afd9b62SAllen-KH Cheng "top_mux_audio", 8281afd9b62SAllen-KH Cheng "top_mux_audio_int", 8291afd9b62SAllen-KH Cheng "top_mainpll_d4_d4", 8301afd9b62SAllen-KH Cheng "top_mux_aud_1", 8311afd9b62SAllen-KH Cheng "top_apll1_ck", 8321afd9b62SAllen-KH Cheng "top_mux_aud_2", 8331afd9b62SAllen-KH Cheng "top_apll2_ck", 8341afd9b62SAllen-KH Cheng "top_mux_aud_eng1", 8351afd9b62SAllen-KH Cheng "top_apll1_d4", 8361afd9b62SAllen-KH Cheng "top_mux_aud_eng2", 8371afd9b62SAllen-KH Cheng "top_apll2_d4", 8381afd9b62SAllen-KH Cheng "top_i2s0_m_sel", 8391afd9b62SAllen-KH Cheng "top_i2s1_m_sel", 8401afd9b62SAllen-KH Cheng "top_i2s2_m_sel", 8411afd9b62SAllen-KH Cheng "top_i2s3_m_sel", 8421afd9b62SAllen-KH Cheng "top_i2s4_m_sel", 8431afd9b62SAllen-KH Cheng "top_i2s5_m_sel", 8441afd9b62SAllen-KH Cheng "top_i2s6_m_sel", 8451afd9b62SAllen-KH Cheng "top_i2s7_m_sel", 8461afd9b62SAllen-KH Cheng "top_i2s8_m_sel", 8471afd9b62SAllen-KH Cheng "top_i2s9_m_sel", 8481afd9b62SAllen-KH Cheng "top_apll12_div0", 8491afd9b62SAllen-KH Cheng "top_apll12_div1", 8501afd9b62SAllen-KH Cheng "top_apll12_div2", 8511afd9b62SAllen-KH Cheng "top_apll12_div3", 8521afd9b62SAllen-KH Cheng "top_apll12_div4", 8531afd9b62SAllen-KH Cheng "top_apll12_divb", 8541afd9b62SAllen-KH Cheng "top_apll12_div5", 8551afd9b62SAllen-KH Cheng "top_apll12_div6", 8561afd9b62SAllen-KH Cheng "top_apll12_div7", 8571afd9b62SAllen-KH Cheng "top_apll12_div8", 8581afd9b62SAllen-KH Cheng "top_apll12_div9", 8591afd9b62SAllen-KH Cheng "top_mux_audio_h", 8601afd9b62SAllen-KH Cheng "top_clk26m_clk"; 8611afd9b62SAllen-KH Cheng }; 8621afd9b62SAllen-KH Cheng }; 8631afd9b62SAllen-KH Cheng 864e530d080SAllen-KH Cheng pcie: pcie@11230000 { 865e530d080SAllen-KH Cheng compatible = "mediatek,mt8192-pcie"; 866e530d080SAllen-KH Cheng device_type = "pci"; 867e530d080SAllen-KH Cheng reg = <0 0x11230000 0 0x2000>; 868e530d080SAllen-KH Cheng reg-names = "pcie-mac"; 869e530d080SAllen-KH Cheng #address-cells = <3>; 870e530d080SAllen-KH Cheng #size-cells = <2>; 871e530d080SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 872e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_26M>, 873e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_96M>, 874e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_32K>, 875e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_PERI_26M>, 876e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 877e530d080SAllen-KH Cheng clock-names = "pl_250m", "tl_26m", "tl_96m", 878e530d080SAllen-KH Cheng "tl_32k", "peri_26m", "top_133m"; 879e530d080SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 880e530d080SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 881e530d080SAllen-KH Cheng interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 882e530d080SAllen-KH Cheng bus-range = <0x00 0xff>; 883e530d080SAllen-KH Cheng ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 884e530d080SAllen-KH Cheng <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 885e530d080SAllen-KH Cheng #interrupt-cells = <1>; 886e530d080SAllen-KH Cheng interrupt-map-mask = <0 0 0 7>; 887e530d080SAllen-KH Cheng interrupt-map = <0 0 0 1 &pcie_intc0 0>, 888e530d080SAllen-KH Cheng <0 0 0 2 &pcie_intc0 1>, 889e530d080SAllen-KH Cheng <0 0 0 3 &pcie_intc0 2>, 890e530d080SAllen-KH Cheng <0 0 0 4 &pcie_intc0 3>; 891e530d080SAllen-KH Cheng 892e530d080SAllen-KH Cheng pcie_intc0: interrupt-controller { 893e530d080SAllen-KH Cheng interrupt-controller; 894e530d080SAllen-KH Cheng #address-cells = <0>; 895e530d080SAllen-KH Cheng #interrupt-cells = <1>; 896e530d080SAllen-KH Cheng }; 897e530d080SAllen-KH Cheng }; 898e530d080SAllen-KH Cheng 899d0a197a0Sbayi cheng nor_flash: spi@11234000 { 900d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 901d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 902d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 903aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 904aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 905aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 906d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 907aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 908aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 909d0a197a0Sbayi cheng #address-cells = <1>; 910d0a197a0Sbayi cheng #size-cells = <0>; 91127f0eb16SAllen-KH Cheng status = "disabled"; 912d0a197a0Sbayi cheng }; 913d0a197a0Sbayi cheng 9144d50a433SAllen-KH Cheng efuse: efuse@11c10000 { 9154d50a433SAllen-KH Cheng compatible = "mediatek,efuse"; 9164d50a433SAllen-KH Cheng reg = <0 0x11c10000 0 0x1000>; 9174d50a433SAllen-KH Cheng #address-cells = <1>; 9184d50a433SAllen-KH Cheng #size-cells = <1>; 9194d50a433SAllen-KH Cheng 9204d50a433SAllen-KH Cheng lvts_e_data1: data1@1c0 { 9214d50a433SAllen-KH Cheng reg = <0x1c0 0x58>; 9224d50a433SAllen-KH Cheng }; 9234d50a433SAllen-KH Cheng 9244d50a433SAllen-KH Cheng svs_calibration: calib@580 { 9254d50a433SAllen-KH Cheng reg = <0x580 0x68>; 9264d50a433SAllen-KH Cheng }; 9274d50a433SAllen-KH Cheng }; 9284d50a433SAllen-KH Cheng 9297f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 93048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 93148489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 93248489980SSeiya Wang <0 0x10217300 0 0x80>; 93348489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 93422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 93522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 93648489980SSeiya Wang clock-names = "main", "dma"; 93748489980SSeiya Wang clock-div = <1>; 93848489980SSeiya Wang #address-cells = <1>; 93948489980SSeiya Wang #size-cells = <0>; 94048489980SSeiya Wang status = "disabled"; 94148489980SSeiya Wang }; 94248489980SSeiya Wang 9435d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 9445d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 9455d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 9465d2b897bSChun-Jie Chen #clock-cells = <1>; 9475d2b897bSChun-Jie Chen }; 9485d2b897bSChun-Jie Chen 9497f1a9f47SFabien Parent i2c7: i2c@11d00000 { 95048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 95148489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 95248489980SSeiya Wang <0 0x10217600 0 0x180>; 95348489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 95422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 95522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 95648489980SSeiya Wang clock-names = "main", "dma"; 95748489980SSeiya Wang clock-div = <1>; 95848489980SSeiya Wang #address-cells = <1>; 95948489980SSeiya Wang #size-cells = <0>; 96048489980SSeiya Wang status = "disabled"; 96148489980SSeiya Wang }; 96248489980SSeiya Wang 9637f1a9f47SFabien Parent i2c8: i2c@11d01000 { 96448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 96548489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 96648489980SSeiya Wang <0 0x10217780 0 0x180>; 96748489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 96822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 96922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 97048489980SSeiya Wang clock-names = "main", "dma"; 97148489980SSeiya Wang clock-div = <1>; 97248489980SSeiya Wang #address-cells = <1>; 97348489980SSeiya Wang #size-cells = <0>; 97448489980SSeiya Wang status = "disabled"; 97548489980SSeiya Wang }; 97648489980SSeiya Wang 9777f1a9f47SFabien Parent i2c9: i2c@11d02000 { 97848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 97948489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 98048489980SSeiya Wang <0 0x10217900 0 0x180>; 98148489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 98222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 98322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 98448489980SSeiya Wang clock-names = "main", "dma"; 98548489980SSeiya Wang clock-div = <1>; 98648489980SSeiya Wang #address-cells = <1>; 98748489980SSeiya Wang #size-cells = <0>; 98848489980SSeiya Wang status = "disabled"; 98948489980SSeiya Wang }; 99048489980SSeiya Wang 9915d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 9925d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 9935d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 9945d2b897bSChun-Jie Chen #clock-cells = <1>; 9955d2b897bSChun-Jie Chen }; 9965d2b897bSChun-Jie Chen 9977f1a9f47SFabien Parent i2c1: i2c@11d20000 { 99848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 99948489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 100048489980SSeiya Wang <0 0x10217100 0 0x80>; 100148489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 100222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 100322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 100448489980SSeiya Wang clock-names = "main", "dma"; 100548489980SSeiya Wang clock-div = <1>; 100648489980SSeiya Wang #address-cells = <1>; 100748489980SSeiya Wang #size-cells = <0>; 100848489980SSeiya Wang status = "disabled"; 100948489980SSeiya Wang }; 101048489980SSeiya Wang 10117f1a9f47SFabien Parent i2c2: i2c@11d21000 { 101248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 101348489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 101448489980SSeiya Wang <0 0x10217180 0 0x180>; 101548489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 101622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 101722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 101848489980SSeiya Wang clock-names = "main", "dma"; 101948489980SSeiya Wang clock-div = <1>; 102048489980SSeiya Wang #address-cells = <1>; 102148489980SSeiya Wang #size-cells = <0>; 102248489980SSeiya Wang status = "disabled"; 102348489980SSeiya Wang }; 102448489980SSeiya Wang 10257f1a9f47SFabien Parent i2c4: i2c@11d22000 { 102648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 102748489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 102848489980SSeiya Wang <0 0x10217380 0 0x180>; 102948489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 103022623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 103122623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 103248489980SSeiya Wang clock-names = "main", "dma"; 103348489980SSeiya Wang clock-div = <1>; 103448489980SSeiya Wang #address-cells = <1>; 103548489980SSeiya Wang #size-cells = <0>; 103648489980SSeiya Wang status = "disabled"; 103748489980SSeiya Wang }; 103848489980SSeiya Wang 10395d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 10405d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 10415d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 10425d2b897bSChun-Jie Chen #clock-cells = <1>; 10435d2b897bSChun-Jie Chen }; 10445d2b897bSChun-Jie Chen 10457f1a9f47SFabien Parent i2c5: i2c@11e00000 { 104648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 104748489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 104848489980SSeiya Wang <0 0x10217500 0 0x80>; 104948489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 105022623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 105122623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 105248489980SSeiya Wang clock-names = "main", "dma"; 105348489980SSeiya Wang clock-div = <1>; 105448489980SSeiya Wang #address-cells = <1>; 105548489980SSeiya Wang #size-cells = <0>; 105648489980SSeiya Wang status = "disabled"; 105748489980SSeiya Wang }; 105848489980SSeiya Wang 10595d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 10605d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 10615d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 10625d2b897bSChun-Jie Chen #clock-cells = <1>; 10635d2b897bSChun-Jie Chen }; 10645d2b897bSChun-Jie Chen 106540de66b8SAllen-KH Cheng u3phy0: t-phy@11e40000 { 106640de66b8SAllen-KH Cheng compatible = "mediatek,mt8192-tphy", 106740de66b8SAllen-KH Cheng "mediatek,generic-tphy-v2"; 106840de66b8SAllen-KH Cheng #address-cells = <1>; 106940de66b8SAllen-KH Cheng #size-cells = <1>; 107040de66b8SAllen-KH Cheng ranges = <0x0 0x0 0x11e40000 0x1000>; 107140de66b8SAllen-KH Cheng 107240de66b8SAllen-KH Cheng u2port0: usb-phy@0 { 107340de66b8SAllen-KH Cheng reg = <0x0 0x700>; 107440de66b8SAllen-KH Cheng clocks = <&clk26m>; 107540de66b8SAllen-KH Cheng clock-names = "ref"; 107640de66b8SAllen-KH Cheng #phy-cells = <1>; 107740de66b8SAllen-KH Cheng }; 107840de66b8SAllen-KH Cheng 107940de66b8SAllen-KH Cheng u3port0: usb-phy@700 { 108040de66b8SAllen-KH Cheng reg = <0x700 0x900>; 108140de66b8SAllen-KH Cheng clocks = <&clk26m>; 108240de66b8SAllen-KH Cheng clock-names = "ref"; 108340de66b8SAllen-KH Cheng #phy-cells = <1>; 108440de66b8SAllen-KH Cheng }; 108540de66b8SAllen-KH Cheng }; 108640de66b8SAllen-KH Cheng 10877f1a9f47SFabien Parent i2c0: i2c@11f00000 { 108848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 108948489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 109048489980SSeiya Wang <0 0x10217080 0 0x80>; 109148489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 109222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 109322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 109448489980SSeiya Wang clock-names = "main", "dma"; 109548489980SSeiya Wang clock-div = <1>; 109648489980SSeiya Wang #address-cells = <1>; 109748489980SSeiya Wang #size-cells = <0>; 109848489980SSeiya Wang status = "disabled"; 109948489980SSeiya Wang }; 110048489980SSeiya Wang 11017f1a9f47SFabien Parent i2c6: i2c@11f01000 { 110248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 110348489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 110448489980SSeiya Wang <0 0x10217580 0 0x80>; 110548489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 110622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 110722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 110848489980SSeiya Wang clock-names = "main", "dma"; 110948489980SSeiya Wang clock-div = <1>; 111048489980SSeiya Wang #address-cells = <1>; 111148489980SSeiya Wang #size-cells = <0>; 111248489980SSeiya Wang status = "disabled"; 111348489980SSeiya Wang }; 11145d2b897bSChun-Jie Chen 11155d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 11165d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 11175d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 11185d2b897bSChun-Jie Chen #clock-cells = <1>; 11195d2b897bSChun-Jie Chen }; 11205d2b897bSChun-Jie Chen 11215d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 11225d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 11235d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 11245d2b897bSChun-Jie Chen #clock-cells = <1>; 11255d2b897bSChun-Jie Chen }; 11265d2b897bSChun-Jie Chen 1127db61337eSAllen-KH Cheng mmc0: mmc@11f60000 { 1128db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1129db61337eSAllen-KH Cheng reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1130db61337eSAllen-KH Cheng interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1131db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1132db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1133db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1134db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1135db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1136db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1137db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1138db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1139db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1140db61337eSAllen-KH Cheng status = "disabled"; 1141db61337eSAllen-KH Cheng }; 1142db61337eSAllen-KH Cheng 1143db61337eSAllen-KH Cheng mmc1: mmc@11f70000 { 1144db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1145db61337eSAllen-KH Cheng reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1146db61337eSAllen-KH Cheng interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1147db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1148db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1149db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1150db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1151db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1152db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1153db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1154db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1155db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1156db61337eSAllen-KH Cheng status = "disabled"; 11575d2b897bSChun-Jie Chen }; 11585d2b897bSChun-Jie Chen 11595d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 11605d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 11615d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 11625d2b897bSChun-Jie Chen #clock-cells = <1>; 11635d2b897bSChun-Jie Chen }; 11645d2b897bSChun-Jie Chen 11655d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 11665d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 11675d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 11685d2b897bSChun-Jie Chen #clock-cells = <1>; 11695d2b897bSChun-Jie Chen }; 11705d2b897bSChun-Jie Chen 11714a65b0f1SAllen-KH Cheng smi_common: smi@14002000 { 11724a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-common"; 11734a65b0f1SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 11744a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 11754a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 11764a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 11774a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>; 11784a65b0f1SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 11794a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 11804a65b0f1SAllen-KH Cheng }; 11814a65b0f1SAllen-KH Cheng 11824a65b0f1SAllen-KH Cheng larb0: larb@14003000 { 11834a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 11844a65b0f1SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 11854a65b0f1SAllen-KH Cheng mediatek,larb-id = <0>; 11864a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 11874a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 11884a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 11894a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 11904a65b0f1SAllen-KH Cheng }; 11914a65b0f1SAllen-KH Cheng 11924a65b0f1SAllen-KH Cheng larb1: larb@14004000 { 11934a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 11944a65b0f1SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 11954a65b0f1SAllen-KH Cheng mediatek,larb-id = <1>; 11964a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 11974a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 11984a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 11994a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12004a65b0f1SAllen-KH Cheng }; 12014a65b0f1SAllen-KH Cheng 1202b2edd519SAllen-KH Cheng dpi0: dpi@14016000 { 1203b2edd519SAllen-KH Cheng compatible = "mediatek,mt8192-dpi"; 1204b2edd519SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1205b2edd519SAllen-KH Cheng interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1206b2edd519SAllen-KH Cheng clocks = <&mmsys CLK_MM_DPI_DPI0>, 1207b2edd519SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI0>, 1208b2edd519SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 1209b2edd519SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 1210b2edd519SAllen-KH Cheng status = "disabled"; 1211b2edd519SAllen-KH Cheng }; 1212b2edd519SAllen-KH Cheng 12134a65b0f1SAllen-KH Cheng iommu0: m4u@1401d000 { 12144a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-m4u"; 12154a65b0f1SAllen-KH Cheng reg = <0 0x1401d000 0 0x1000>; 12164a65b0f1SAllen-KH Cheng mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 12174a65b0f1SAllen-KH Cheng <&larb4>, <&larb5>, <&larb7>, 12184a65b0f1SAllen-KH Cheng <&larb9>, <&larb11>, <&larb13>, 12194a65b0f1SAllen-KH Cheng <&larb14>, <&larb16>, <&larb17>, 12204a65b0f1SAllen-KH Cheng <&larb18>, <&larb19>, <&larb20>; 12214a65b0f1SAllen-KH Cheng interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 12224a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 12234a65b0f1SAllen-KH Cheng clock-names = "bclk"; 12244a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12254a65b0f1SAllen-KH Cheng #iommu-cells = <1>; 12264a65b0f1SAllen-KH Cheng }; 12274a65b0f1SAllen-KH Cheng 12285d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 12295d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 12305d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 12315d2b897bSChun-Jie Chen #clock-cells = <1>; 12325d2b897bSChun-Jie Chen }; 12335d2b897bSChun-Jie Chen 12344a65b0f1SAllen-KH Cheng larb9: larb@1502e000 { 12354a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12364a65b0f1SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 12374a65b0f1SAllen-KH Cheng mediatek,larb-id = <9>; 12384a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12394a65b0f1SAllen-KH Cheng clocks = <&imgsys CLK_IMG_LARB9>, 12404a65b0f1SAllen-KH Cheng <&imgsys CLK_IMG_LARB9>; 12414a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12424a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 12434a65b0f1SAllen-KH Cheng }; 12444a65b0f1SAllen-KH Cheng 12455d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 12465d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 12475d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 12485d2b897bSChun-Jie Chen #clock-cells = <1>; 12495d2b897bSChun-Jie Chen }; 12505d2b897bSChun-Jie Chen 12514a65b0f1SAllen-KH Cheng larb11: larb@1582e000 { 12524a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12534a65b0f1SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 12544a65b0f1SAllen-KH Cheng mediatek,larb-id = <11>; 12554a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12564a65b0f1SAllen-KH Cheng clocks = <&imgsys2 CLK_IMG2_LARB11>, 12574a65b0f1SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB11>; 12584a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12594a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 12604a65b0f1SAllen-KH Cheng }; 12614a65b0f1SAllen-KH Cheng 12624a65b0f1SAllen-KH Cheng larb5: larb@1600d000 { 12634a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12644a65b0f1SAllen-KH Cheng reg = <0 0x1600d000 0 0x1000>; 12654a65b0f1SAllen-KH Cheng mediatek,larb-id = <5>; 12664a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12674a65b0f1SAllen-KH Cheng clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 12684a65b0f1SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 12694a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12704a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 12714a65b0f1SAllen-KH Cheng }; 12724a65b0f1SAllen-KH Cheng 12735d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 12745d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 12755d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 12765d2b897bSChun-Jie Chen #clock-cells = <1>; 12775d2b897bSChun-Jie Chen }; 12785d2b897bSChun-Jie Chen 12794a65b0f1SAllen-KH Cheng larb4: larb@1602e000 { 12804a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 12814a65b0f1SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 12824a65b0f1SAllen-KH Cheng mediatek,larb-id = <4>; 12834a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 12844a65b0f1SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 12854a65b0f1SAllen-KH Cheng <&vdecsys CLK_VDEC_SOC_LARB1>; 12864a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 12874a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 12884a65b0f1SAllen-KH Cheng }; 12894a65b0f1SAllen-KH Cheng 12905d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 12915d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 12925d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 12935d2b897bSChun-Jie Chen #clock-cells = <1>; 12945d2b897bSChun-Jie Chen }; 12955d2b897bSChun-Jie Chen 12965d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 12975d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 12985d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 12995d2b897bSChun-Jie Chen #clock-cells = <1>; 13005d2b897bSChun-Jie Chen }; 13015d2b897bSChun-Jie Chen 13024a65b0f1SAllen-KH Cheng larb7: larb@17010000 { 13034a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13044a65b0f1SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 13054a65b0f1SAllen-KH Cheng mediatek,larb-id = <7>; 13064a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13074a65b0f1SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET0_LARB>, 13084a65b0f1SAllen-KH Cheng <&vencsys CLK_VENC_SET1_VENC>; 13094a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13104a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 13114a65b0f1SAllen-KH Cheng }; 13124a65b0f1SAllen-KH Cheng 1313aa8f3711SAllen-KH Cheng vcodec_enc: vcodec@17020000 { 1314aa8f3711SAllen-KH Cheng compatible = "mediatek,mt8192-vcodec-enc"; 1315aa8f3711SAllen-KH Cheng reg = <0 0x17020000 0 0x2000>; 1316aa8f3711SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1317aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REC>, 1318aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1319aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1320aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1321aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1322aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1323aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1324aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1325aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1326aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1327aa8f3711SAllen-KH Cheng interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1328aa8f3711SAllen-KH Cheng mediatek,scp = <&scp>; 1329aa8f3711SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1330aa8f3711SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET1_VENC>; 1331aa8f3711SAllen-KH Cheng clock-names = "venc-set1"; 1332aa8f3711SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1333aa8f3711SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1334aa8f3711SAllen-KH Cheng }; 1335aa8f3711SAllen-KH Cheng 13365d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 13375d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 13385d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 13395d2b897bSChun-Jie Chen #clock-cells = <1>; 13405d2b897bSChun-Jie Chen }; 13415d2b897bSChun-Jie Chen 13424a65b0f1SAllen-KH Cheng larb13: larb@1a001000 { 13434a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13444a65b0f1SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 13454a65b0f1SAllen-KH Cheng mediatek,larb-id = <13>; 13464a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13474a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 13484a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB13>; 13494a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13504a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 13514a65b0f1SAllen-KH Cheng }; 13524a65b0f1SAllen-KH Cheng 13534a65b0f1SAllen-KH Cheng larb14: larb@1a002000 { 13544a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13554a65b0f1SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 13564a65b0f1SAllen-KH Cheng mediatek,larb-id = <14>; 13574a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13584a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 13594a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB14>; 13604a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13614a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 13624a65b0f1SAllen-KH Cheng }; 13634a65b0f1SAllen-KH Cheng 13644a65b0f1SAllen-KH Cheng larb16: larb@1a00f000 { 13654a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13664a65b0f1SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 13674a65b0f1SAllen-KH Cheng mediatek,larb-id = <16>; 13684a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13694a65b0f1SAllen-KH Cheng clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 13704a65b0f1SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX>; 13714a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13724a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 13734a65b0f1SAllen-KH Cheng }; 13744a65b0f1SAllen-KH Cheng 13754a65b0f1SAllen-KH Cheng larb17: larb@1a010000 { 13764a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13774a65b0f1SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 13784a65b0f1SAllen-KH Cheng mediatek,larb-id = <17>; 13794a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13804a65b0f1SAllen-KH Cheng clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 13814a65b0f1SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX>; 13824a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13834a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 13844a65b0f1SAllen-KH Cheng }; 13854a65b0f1SAllen-KH Cheng 13864a65b0f1SAllen-KH Cheng larb18: larb@1a011000 { 13874a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13884a65b0f1SAllen-KH Cheng reg = <0 0x1a011000 0 0x1000>; 13894a65b0f1SAllen-KH Cheng mediatek,larb-id = <18>; 13904a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13914a65b0f1SAllen-KH Cheng clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 13924a65b0f1SAllen-KH Cheng <&camsys_rawc CLK_CAM_RAWC_CAM>; 13934a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13944a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 13954a65b0f1SAllen-KH Cheng }; 13964a65b0f1SAllen-KH Cheng 13975d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 13985d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 13995d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 14005d2b897bSChun-Jie Chen #clock-cells = <1>; 14015d2b897bSChun-Jie Chen }; 14025d2b897bSChun-Jie Chen 14035d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 14045d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 14055d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 14065d2b897bSChun-Jie Chen #clock-cells = <1>; 14075d2b897bSChun-Jie Chen }; 14085d2b897bSChun-Jie Chen 14095d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 14105d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 14115d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 14125d2b897bSChun-Jie Chen #clock-cells = <1>; 14135d2b897bSChun-Jie Chen }; 14145d2b897bSChun-Jie Chen 14155d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 14165d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 14175d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 14185d2b897bSChun-Jie Chen #clock-cells = <1>; 14195d2b897bSChun-Jie Chen }; 14205d2b897bSChun-Jie Chen 14214a65b0f1SAllen-KH Cheng larb20: larb@1b00f000 { 14224a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14234a65b0f1SAllen-KH Cheng reg = <0 0x1b00f000 0 0x1000>; 14244a65b0f1SAllen-KH Cheng mediatek,larb-id = <20>; 14254a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14264a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 14274a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB20>; 14284a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14294a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 14304a65b0f1SAllen-KH Cheng }; 14314a65b0f1SAllen-KH Cheng 14324a65b0f1SAllen-KH Cheng larb19: larb@1b10f000 { 14334a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14344a65b0f1SAllen-KH Cheng reg = <0 0x1b10f000 0 0x1000>; 14354a65b0f1SAllen-KH Cheng mediatek,larb-id = <19>; 14364a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14374a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 14384a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB19>; 14394a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14404a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 14414a65b0f1SAllen-KH Cheng }; 14424a65b0f1SAllen-KH Cheng 14435d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 14445d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 14455d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 14465d2b897bSChun-Jie Chen #clock-cells = <1>; 14475d2b897bSChun-Jie Chen }; 14484a65b0f1SAllen-KH Cheng 14494a65b0f1SAllen-KH Cheng larb2: larb@1f002000 { 14504a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14514a65b0f1SAllen-KH Cheng reg = <0 0x1f002000 0 0x1000>; 14524a65b0f1SAllen-KH Cheng mediatek,larb-id = <2>; 14534a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14544a65b0f1SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, 14554a65b0f1SAllen-KH Cheng <&mdpsys CLK_MDP_SMI0>; 14564a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14574a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 14584a65b0f1SAllen-KH Cheng }; 145948489980SSeiya Wang }; 146048489980SSeiya Wang}; 1461