148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 9b4b75bacSAllen-KH Cheng#include <dt-bindings/gce/mt8192-gce.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1148489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 124a65b0f1SAllen-KH Cheng#include <dt-bindings/memory/mt8192-larb-port.h> 1348489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h> 15994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 167d355378SAllen-KH Cheng#include <dt-bindings/reset/mt8192-resets.h> 1748489980SSeiya Wang 1848489980SSeiya Wang/ { 1948489980SSeiya Wang compatible = "mediatek,mt8192"; 2048489980SSeiya Wang interrupt-parent = <&gic>; 2148489980SSeiya Wang #address-cells = <2>; 2248489980SSeiya Wang #size-cells = <2>; 2348489980SSeiya Wang 24b4b75bacSAllen-KH Cheng aliases { 25b4b75bacSAllen-KH Cheng ovl0 = &ovl0; 26b4b75bacSAllen-KH Cheng ovl-2l0 = &ovl_2l0; 27b4b75bacSAllen-KH Cheng ovl-2l2 = &ovl_2l2; 28b4b75bacSAllen-KH Cheng rdma0 = &rdma0; 29b4b75bacSAllen-KH Cheng rdma4 = &rdma4; 30b4b75bacSAllen-KH Cheng }; 31b4b75bacSAllen-KH Cheng 32f19f68e5SChen-Yu Tsai clk13m: fixed-factor-clock-13m { 33f19f68e5SChen-Yu Tsai compatible = "fixed-factor-clock"; 34f19f68e5SChen-Yu Tsai #clock-cells = <0>; 35f19f68e5SChen-Yu Tsai clocks = <&clk26m>; 36f19f68e5SChen-Yu Tsai clock-div = <2>; 37f19f68e5SChen-Yu Tsai clock-mult = <1>; 38f19f68e5SChen-Yu Tsai clock-output-names = "clk13m"; 39f19f68e5SChen-Yu Tsai }; 40f19f68e5SChen-Yu Tsai 4148489980SSeiya Wang clk26m: oscillator0 { 4248489980SSeiya Wang compatible = "fixed-clock"; 4348489980SSeiya Wang #clock-cells = <0>; 4448489980SSeiya Wang clock-frequency = <26000000>; 4548489980SSeiya Wang clock-output-names = "clk26m"; 4648489980SSeiya Wang }; 4748489980SSeiya Wang 4848489980SSeiya Wang clk32k: oscillator1 { 4948489980SSeiya Wang compatible = "fixed-clock"; 5048489980SSeiya Wang #clock-cells = <0>; 5148489980SSeiya Wang clock-frequency = <32768>; 5248489980SSeiya Wang clock-output-names = "clk32k"; 5348489980SSeiya Wang }; 5448489980SSeiya Wang 5548489980SSeiya Wang cpus { 5648489980SSeiya Wang #address-cells = <1>; 5748489980SSeiya Wang #size-cells = <0>; 5848489980SSeiya Wang 5948489980SSeiya Wang cpu0: cpu@0 { 6048489980SSeiya Wang device_type = "cpu"; 6148489980SSeiya Wang compatible = "arm,cortex-a55"; 6248489980SSeiya Wang reg = <0x000>; 6348489980SSeiya Wang enable-method = "psci"; 6448489980SSeiya Wang clock-frequency = <1701000000>; 65399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 66*29288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 67*29288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 68*29288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 69*29288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 70*29288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 71*29288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 7248489980SSeiya Wang next-level-cache = <&l2_0>; 7348489980SSeiya Wang capacity-dmips-mhz = <530>; 7448489980SSeiya Wang }; 7548489980SSeiya Wang 7648489980SSeiya Wang cpu1: cpu@100 { 7748489980SSeiya Wang device_type = "cpu"; 7848489980SSeiya Wang compatible = "arm,cortex-a55"; 7948489980SSeiya Wang reg = <0x100>; 8048489980SSeiya Wang enable-method = "psci"; 8148489980SSeiya Wang clock-frequency = <1701000000>; 82399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 83*29288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 84*29288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 85*29288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 86*29288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 87*29288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 88*29288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 8948489980SSeiya Wang next-level-cache = <&l2_0>; 9048489980SSeiya Wang capacity-dmips-mhz = <530>; 9148489980SSeiya Wang }; 9248489980SSeiya Wang 9348489980SSeiya Wang cpu2: cpu@200 { 9448489980SSeiya Wang device_type = "cpu"; 9548489980SSeiya Wang compatible = "arm,cortex-a55"; 9648489980SSeiya Wang reg = <0x200>; 9748489980SSeiya Wang enable-method = "psci"; 9848489980SSeiya Wang clock-frequency = <1701000000>; 99399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 100*29288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 101*29288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 102*29288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 103*29288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 104*29288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 105*29288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 10648489980SSeiya Wang next-level-cache = <&l2_0>; 10748489980SSeiya Wang capacity-dmips-mhz = <530>; 10848489980SSeiya Wang }; 10948489980SSeiya Wang 11048489980SSeiya Wang cpu3: cpu@300 { 11148489980SSeiya Wang device_type = "cpu"; 11248489980SSeiya Wang compatible = "arm,cortex-a55"; 11348489980SSeiya Wang reg = <0x300>; 11448489980SSeiya Wang enable-method = "psci"; 11548489980SSeiya Wang clock-frequency = <1701000000>; 116399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 117*29288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 118*29288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 119*29288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 120*29288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 121*29288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 122*29288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 12348489980SSeiya Wang next-level-cache = <&l2_0>; 12448489980SSeiya Wang capacity-dmips-mhz = <530>; 12548489980SSeiya Wang }; 12648489980SSeiya Wang 12748489980SSeiya Wang cpu4: cpu@400 { 12848489980SSeiya Wang device_type = "cpu"; 12948489980SSeiya Wang compatible = "arm,cortex-a76"; 13048489980SSeiya Wang reg = <0x400>; 13148489980SSeiya Wang enable-method = "psci"; 13248489980SSeiya Wang clock-frequency = <2171000000>; 133399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 134*29288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 135*29288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 136*29288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 137*29288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 138*29288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 139*29288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 14048489980SSeiya Wang next-level-cache = <&l2_1>; 14148489980SSeiya Wang capacity-dmips-mhz = <1024>; 14248489980SSeiya Wang }; 14348489980SSeiya Wang 14448489980SSeiya Wang cpu5: cpu@500 { 14548489980SSeiya Wang device_type = "cpu"; 14648489980SSeiya Wang compatible = "arm,cortex-a76"; 14748489980SSeiya Wang reg = <0x500>; 14848489980SSeiya Wang enable-method = "psci"; 14948489980SSeiya Wang clock-frequency = <2171000000>; 150399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 151*29288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 152*29288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 153*29288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 154*29288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 155*29288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 156*29288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 15748489980SSeiya Wang next-level-cache = <&l2_1>; 15848489980SSeiya Wang capacity-dmips-mhz = <1024>; 15948489980SSeiya Wang }; 16048489980SSeiya Wang 16148489980SSeiya Wang cpu6: cpu@600 { 16248489980SSeiya Wang device_type = "cpu"; 16348489980SSeiya Wang compatible = "arm,cortex-a76"; 16448489980SSeiya Wang reg = <0x600>; 16548489980SSeiya Wang enable-method = "psci"; 16648489980SSeiya Wang clock-frequency = <2171000000>; 167399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 168*29288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 169*29288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 170*29288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 171*29288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 172*29288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 173*29288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 17448489980SSeiya Wang next-level-cache = <&l2_1>; 17548489980SSeiya Wang capacity-dmips-mhz = <1024>; 17648489980SSeiya Wang }; 17748489980SSeiya Wang 17848489980SSeiya Wang cpu7: cpu@700 { 17948489980SSeiya Wang device_type = "cpu"; 18048489980SSeiya Wang compatible = "arm,cortex-a76"; 18148489980SSeiya Wang reg = <0x700>; 18248489980SSeiya Wang enable-method = "psci"; 18348489980SSeiya Wang clock-frequency = <2171000000>; 184399e23adSNícolas F. R. A. Prado cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 185*29288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 186*29288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 187*29288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 188*29288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 189*29288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 190*29288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 19148489980SSeiya Wang next-level-cache = <&l2_1>; 19248489980SSeiya Wang capacity-dmips-mhz = <1024>; 19348489980SSeiya Wang }; 19448489980SSeiya Wang 19548489980SSeiya Wang cpu-map { 19648489980SSeiya Wang cluster0 { 19748489980SSeiya Wang core0 { 19848489980SSeiya Wang cpu = <&cpu0>; 19948489980SSeiya Wang }; 20048489980SSeiya Wang core1 { 20148489980SSeiya Wang cpu = <&cpu1>; 20248489980SSeiya Wang }; 20348489980SSeiya Wang core2 { 20448489980SSeiya Wang cpu = <&cpu2>; 20548489980SSeiya Wang }; 20648489980SSeiya Wang core3 { 20748489980SSeiya Wang cpu = <&cpu3>; 20848489980SSeiya Wang }; 20948489980SSeiya Wang }; 21048489980SSeiya Wang 21148489980SSeiya Wang cluster1 { 21248489980SSeiya Wang core0 { 21348489980SSeiya Wang cpu = <&cpu4>; 21448489980SSeiya Wang }; 21548489980SSeiya Wang core1 { 21648489980SSeiya Wang cpu = <&cpu5>; 21748489980SSeiya Wang }; 21848489980SSeiya Wang core2 { 21948489980SSeiya Wang cpu = <&cpu6>; 22048489980SSeiya Wang }; 22148489980SSeiya Wang core3 { 22248489980SSeiya Wang cpu = <&cpu7>; 22348489980SSeiya Wang }; 22448489980SSeiya Wang }; 22548489980SSeiya Wang }; 22648489980SSeiya Wang 22748489980SSeiya Wang l2_0: l2-cache0 { 22848489980SSeiya Wang compatible = "cache"; 229ce459b1dSPierre Gondois cache-level = <2>; 230*29288babSAngeloGioacchino Del Regno cache-size = <131072>; 231*29288babSAngeloGioacchino Del Regno cache-line-size = <64>; 232*29288babSAngeloGioacchino Del Regno cache-sets = <512>; 23348489980SSeiya Wang next-level-cache = <&l3_0>; 23448489980SSeiya Wang }; 23548489980SSeiya Wang 23648489980SSeiya Wang l2_1: l2-cache1 { 23748489980SSeiya Wang compatible = "cache"; 238ce459b1dSPierre Gondois cache-level = <2>; 239*29288babSAngeloGioacchino Del Regno cache-size = <262144>; 240*29288babSAngeloGioacchino Del Regno cache-line-size = <64>; 241*29288babSAngeloGioacchino Del Regno cache-sets = <512>; 24248489980SSeiya Wang next-level-cache = <&l3_0>; 24348489980SSeiya Wang }; 24448489980SSeiya Wang 24548489980SSeiya Wang l3_0: l3-cache { 24648489980SSeiya Wang compatible = "cache"; 247ce459b1dSPierre Gondois cache-level = <3>; 248*29288babSAngeloGioacchino Del Regno cache-size = <2097152>; 249*29288babSAngeloGioacchino Del Regno cache-line-size = <64>; 250*29288babSAngeloGioacchino Del Regno cache-sets = <2048>; 251*29288babSAngeloGioacchino Del Regno cache-unified; 25248489980SSeiya Wang }; 2539260918dSJames Liao 2549260918dSJames Liao idle-states { 2552e599740SNícolas F. R. A. Prado entry-method = "psci"; 256399e23adSNícolas F. R. A. Prado cpu_sleep_l: cpu-sleep-l { 2579260918dSJames Liao compatible = "arm,idle-state"; 2589260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 2599260918dSJames Liao local-timer-stop; 2609260918dSJames Liao entry-latency-us = <55>; 2619260918dSJames Liao exit-latency-us = <140>; 2629260918dSJames Liao min-residency-us = <780>; 2639260918dSJames Liao }; 264399e23adSNícolas F. R. A. Prado cpu_sleep_b: cpu-sleep-b { 2659260918dSJames Liao compatible = "arm,idle-state"; 2669260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 2679260918dSJames Liao local-timer-stop; 2689260918dSJames Liao entry-latency-us = <35>; 2699260918dSJames Liao exit-latency-us = <145>; 2709260918dSJames Liao min-residency-us = <720>; 2719260918dSJames Liao }; 272399e23adSNícolas F. R. A. Prado cluster_sleep_l: cluster-sleep-l { 2739260918dSJames Liao compatible = "arm,idle-state"; 2749260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2759260918dSJames Liao local-timer-stop; 2769260918dSJames Liao entry-latency-us = <60>; 2779260918dSJames Liao exit-latency-us = <155>; 2789260918dSJames Liao min-residency-us = <860>; 2799260918dSJames Liao }; 280399e23adSNícolas F. R. A. Prado cluster_sleep_b: cluster-sleep-b { 2819260918dSJames Liao compatible = "arm,idle-state"; 2829260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2839260918dSJames Liao local-timer-stop; 2849260918dSJames Liao entry-latency-us = <40>; 2859260918dSJames Liao exit-latency-us = <155>; 2869260918dSJames Liao min-residency-us = <780>; 2879260918dSJames Liao }; 2889260918dSJames Liao }; 28948489980SSeiya Wang }; 29048489980SSeiya Wang 29148489980SSeiya Wang pmu-a55 { 29248489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 29348489980SSeiya Wang interrupt-parent = <&gic>; 29448489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 29548489980SSeiya Wang }; 29648489980SSeiya Wang 29748489980SSeiya Wang pmu-a76 { 29848489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 29948489980SSeiya Wang interrupt-parent = <&gic>; 30048489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 30148489980SSeiya Wang }; 30248489980SSeiya Wang 30348489980SSeiya Wang psci { 30448489980SSeiya Wang compatible = "arm,psci-1.0"; 30548489980SSeiya Wang method = "smc"; 30648489980SSeiya Wang }; 30748489980SSeiya Wang 30848489980SSeiya Wang timer: timer { 30948489980SSeiya Wang compatible = "arm,armv8-timer"; 31048489980SSeiya Wang interrupt-parent = <&gic>; 31148489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 31248489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 31348489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 31448489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 31548489980SSeiya Wang clock-frequency = <13000000>; 31648489980SSeiya Wang }; 31748489980SSeiya Wang 31848489980SSeiya Wang soc { 31948489980SSeiya Wang #address-cells = <2>; 32048489980SSeiya Wang #size-cells = <2>; 32148489980SSeiya Wang compatible = "simple-bus"; 32248489980SSeiya Wang ranges; 32348489980SSeiya Wang 32448489980SSeiya Wang gic: interrupt-controller@c000000 { 32548489980SSeiya Wang compatible = "arm,gic-v3"; 32648489980SSeiya Wang #interrupt-cells = <4>; 32748489980SSeiya Wang #redistributor-regions = <1>; 32848489980SSeiya Wang interrupt-parent = <&gic>; 32948489980SSeiya Wang interrupt-controller; 33048489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 33148489980SSeiya Wang <0 0x0c040000 0 0x200000>; 33248489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 33348489980SSeiya Wang 33448489980SSeiya Wang ppi-partitions { 33548489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 33648489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 33748489980SSeiya Wang }; 33848489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 33948489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 34048489980SSeiya Wang }; 34148489980SSeiya Wang }; 34248489980SSeiya Wang }; 34348489980SSeiya Wang 3445d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 3455d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 3465d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 3475d2b897bSChun-Jie Chen #clock-cells = <1>; 3485d2b897bSChun-Jie Chen }; 3495d2b897bSChun-Jie Chen 3505d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 3515d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 3525d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 3535d2b897bSChun-Jie Chen #clock-cells = <1>; 354a30cc07fSRex-BC Chen #reset-cells = <1>; 3555d2b897bSChun-Jie Chen }; 3565d2b897bSChun-Jie Chen 3575d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 3585d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 3595d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 3605d2b897bSChun-Jie Chen #clock-cells = <1>; 3615d2b897bSChun-Jie Chen }; 3625d2b897bSChun-Jie Chen 36348489980SSeiya Wang pio: pinctrl@10005000 { 36448489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 36548489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 36648489980SSeiya Wang <0 0x11c20000 0 0x1000>, 36748489980SSeiya Wang <0 0x11d10000 0 0x1000>, 36848489980SSeiya Wang <0 0x11d30000 0 0x1000>, 36948489980SSeiya Wang <0 0x11d40000 0 0x1000>, 37048489980SSeiya Wang <0 0x11e20000 0 0x1000>, 37148489980SSeiya Wang <0 0x11e70000 0 0x1000>, 37248489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 37348489980SSeiya Wang <0 0x11f20000 0 0x1000>, 37448489980SSeiya Wang <0 0x11f30000 0 0x1000>, 37548489980SSeiya Wang <0 0x1000b000 0 0x1000>; 37648489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 37748489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 37848489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 37948489980SSeiya Wang "iocfg_tl", "eint"; 38048489980SSeiya Wang gpio-controller; 38148489980SSeiya Wang #gpio-cells = <2>; 38248489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 38348489980SSeiya Wang interrupt-controller; 38448489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 38548489980SSeiya Wang #interrupt-cells = <2>; 38648489980SSeiya Wang }; 38748489980SSeiya Wang 388994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 389d3dfd468STinghan Shen compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 390994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 391994a71a3SChun-Jie Chen 392994a71a3SChun-Jie Chen /* System Power Manager */ 393994a71a3SChun-Jie Chen spm: power-controller { 394994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 395994a71a3SChun-Jie Chen #address-cells = <1>; 396994a71a3SChun-Jie Chen #size-cells = <0>; 397994a71a3SChun-Jie Chen #power-domain-cells = <1>; 398994a71a3SChun-Jie Chen 399994a71a3SChun-Jie Chen /* power domain of the SoC */ 400994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 401994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 402994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 403994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 404994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 405994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 406994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 407994a71a3SChun-Jie Chen #power-domain-cells = <0>; 408994a71a3SChun-Jie Chen }; 409994a71a3SChun-Jie Chen 410994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 411994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 412994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 413994a71a3SChun-Jie Chen clock-names = "conn"; 414994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 415994a71a3SChun-Jie Chen #power-domain-cells = <0>; 416994a71a3SChun-Jie Chen }; 417994a71a3SChun-Jie Chen 418994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG0 { 419994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 420994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 421994a71a3SChun-Jie Chen clock-names = "mfg"; 422994a71a3SChun-Jie Chen #address-cells = <1>; 423994a71a3SChun-Jie Chen #size-cells = <0>; 424994a71a3SChun-Jie Chen #power-domain-cells = <1>; 425994a71a3SChun-Jie Chen 426994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG1 { 427994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 428994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 429994a71a3SChun-Jie Chen #address-cells = <1>; 430994a71a3SChun-Jie Chen #size-cells = <0>; 431994a71a3SChun-Jie Chen #power-domain-cells = <1>; 432994a71a3SChun-Jie Chen 433994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 434994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 435994a71a3SChun-Jie Chen #power-domain-cells = <0>; 436994a71a3SChun-Jie Chen }; 437994a71a3SChun-Jie Chen 438994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 439994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 440994a71a3SChun-Jie Chen #power-domain-cells = <0>; 441994a71a3SChun-Jie Chen }; 442994a71a3SChun-Jie Chen 443994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 444994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 445994a71a3SChun-Jie Chen #power-domain-cells = <0>; 446994a71a3SChun-Jie Chen }; 447994a71a3SChun-Jie Chen 448994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 449994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 450994a71a3SChun-Jie Chen #power-domain-cells = <0>; 451994a71a3SChun-Jie Chen }; 452994a71a3SChun-Jie Chen 453994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 454994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 455994a71a3SChun-Jie Chen #power-domain-cells = <0>; 456994a71a3SChun-Jie Chen }; 457994a71a3SChun-Jie Chen }; 458994a71a3SChun-Jie Chen }; 459994a71a3SChun-Jie Chen 460994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 461994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 462994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 463994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 464994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 465994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 466994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 467994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 468994a71a3SChun-Jie Chen "disp-3"; 469994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 470994a71a3SChun-Jie Chen #address-cells = <1>; 471994a71a3SChun-Jie Chen #size-cells = <0>; 472994a71a3SChun-Jie Chen #power-domain-cells = <1>; 473994a71a3SChun-Jie Chen 474994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 475994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 476994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 477994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 478994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 479994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 480994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 481994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 482994a71a3SChun-Jie Chen "ipe-3"; 483994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 484994a71a3SChun-Jie Chen #power-domain-cells = <0>; 485994a71a3SChun-Jie Chen }; 486994a71a3SChun-Jie Chen 487994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 488994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 489994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 490994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 491994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 492994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 493994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 494994a71a3SChun-Jie Chen #power-domain-cells = <0>; 495994a71a3SChun-Jie Chen }; 496994a71a3SChun-Jie Chen 497994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 498994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 499994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 500994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 501994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 502994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 503994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 504994a71a3SChun-Jie Chen #power-domain-cells = <0>; 505994a71a3SChun-Jie Chen }; 506994a71a3SChun-Jie Chen 507994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 508994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 509994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 510994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 511994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 512994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 513994a71a3SChun-Jie Chen #power-domain-cells = <0>; 514994a71a3SChun-Jie Chen }; 515994a71a3SChun-Jie Chen 516994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 517994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 518994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 519994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 520994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 521994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 522994a71a3SChun-Jie Chen #power-domain-cells = <0>; 523994a71a3SChun-Jie Chen }; 524994a71a3SChun-Jie Chen 525994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 526994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 527994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 528994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 529994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 530994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 531994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 532994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 533994a71a3SChun-Jie Chen #address-cells = <1>; 534994a71a3SChun-Jie Chen #size-cells = <0>; 535994a71a3SChun-Jie Chen #power-domain-cells = <1>; 536994a71a3SChun-Jie Chen 537994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 538994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 539994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 540994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 541994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 542994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 543994a71a3SChun-Jie Chen "vdec2-2"; 544994a71a3SChun-Jie Chen #power-domain-cells = <0>; 545994a71a3SChun-Jie Chen }; 546994a71a3SChun-Jie Chen }; 547994a71a3SChun-Jie Chen 548994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 549994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 550994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 551994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 552994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 553994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 554994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 555994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 556994a71a3SChun-Jie Chen "cam-3"; 557994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 558994a71a3SChun-Jie Chen #address-cells = <1>; 559994a71a3SChun-Jie Chen #size-cells = <0>; 560994a71a3SChun-Jie Chen #power-domain-cells = <1>; 561994a71a3SChun-Jie Chen 562994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 563994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 564994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 565994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 566994a71a3SChun-Jie Chen #power-domain-cells = <0>; 567994a71a3SChun-Jie Chen }; 568994a71a3SChun-Jie Chen 569994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 570994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 571994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 572994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 573994a71a3SChun-Jie Chen #power-domain-cells = <0>; 574994a71a3SChun-Jie Chen }; 575994a71a3SChun-Jie Chen 576994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 577994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 578994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 579994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 580994a71a3SChun-Jie Chen #power-domain-cells = <0>; 581994a71a3SChun-Jie Chen }; 582994a71a3SChun-Jie Chen }; 583994a71a3SChun-Jie Chen }; 584994a71a3SChun-Jie Chen }; 585994a71a3SChun-Jie Chen }; 586994a71a3SChun-Jie Chen 587d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 588d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 589d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 590d1986fbdSAllen-KH Cheng #reset-cells = <1>; 591d1986fbdSAllen-KH Cheng }; 592d1986fbdSAllen-KH Cheng 5935d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 5945d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 5955d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 5965d2b897bSChun-Jie Chen #clock-cells = <1>; 5975d2b897bSChun-Jie Chen }; 5985d2b897bSChun-Jie Chen 59948489980SSeiya Wang systimer: timer@10017000 { 60048489980SSeiya Wang compatible = "mediatek,mt8192-timer", 60148489980SSeiya Wang "mediatek,mt6765-timer"; 60248489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 60348489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 604f19f68e5SChen-Yu Tsai clocks = <&clk13m>; 60548489980SSeiya Wang }; 60648489980SSeiya Wang 607261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 608261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 609261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 610261691b4SAllen-KH Cheng reg-names = "pwrap"; 611261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 612261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 613261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 614261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 615261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 616261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 617261691b4SAllen-KH Cheng }; 618261691b4SAllen-KH Cheng 619a8bbcf70SAllen-KH Cheng spmi: spmi@10027000 { 620a8bbcf70SAllen-KH Cheng compatible = "mediatek,mt6873-spmi"; 621a8bbcf70SAllen-KH Cheng reg = <0 0x10027000 0 0x000e00>, 622a8bbcf70SAllen-KH Cheng <0 0x10029000 0 0x000100>; 623a8bbcf70SAllen-KH Cheng reg-names = "pmif", "spmimst"; 624a8bbcf70SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 625a8bbcf70SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>, 626a8bbcf70SAllen-KH Cheng <&topckgen CLK_TOP_SPMI_MST_SEL>; 627a8bbcf70SAllen-KH Cheng clock-names = "pmif_sys_ck", 628a8bbcf70SAllen-KH Cheng "pmif_tmr_ck", 629a8bbcf70SAllen-KH Cheng "spmimst_clk_mux"; 630a8bbcf70SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 631a8bbcf70SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 632a8bbcf70SAllen-KH Cheng }; 633a8bbcf70SAllen-KH Cheng 634b4b75bacSAllen-KH Cheng gce: mailbox@10228000 { 635b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-gce"; 636b4b75bacSAllen-KH Cheng reg = <0 0x10228000 0 0x4000>; 637b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 638b4b75bacSAllen-KH Cheng #mbox-cells = <2>; 639b4b75bacSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_GCE>; 640b4b75bacSAllen-KH Cheng clock-names = "gce"; 641b4b75bacSAllen-KH Cheng }; 642b4b75bacSAllen-KH Cheng 6435d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 6445d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 6455d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 6465d2b897bSChun-Jie Chen #clock-cells = <1>; 6475d2b897bSChun-Jie Chen }; 6485d2b897bSChun-Jie Chen 64948489980SSeiya Wang uart0: serial@11002000 { 65048489980SSeiya Wang compatible = "mediatek,mt8192-uart", 65148489980SSeiya Wang "mediatek,mt6577-uart"; 65248489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 65348489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 65473ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 65548489980SSeiya Wang clock-names = "baud", "bus"; 65648489980SSeiya Wang status = "disabled"; 65748489980SSeiya Wang }; 65848489980SSeiya Wang 65948489980SSeiya Wang uart1: serial@11003000 { 66048489980SSeiya Wang compatible = "mediatek,mt8192-uart", 66148489980SSeiya Wang "mediatek,mt6577-uart"; 66248489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 66348489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 66473ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 66548489980SSeiya Wang clock-names = "baud", "bus"; 66648489980SSeiya Wang status = "disabled"; 66748489980SSeiya Wang }; 66848489980SSeiya Wang 6695d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 6705d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 6715d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 6725d2b897bSChun-Jie Chen #clock-cells = <1>; 6735d2b897bSChun-Jie Chen }; 6745d2b897bSChun-Jie Chen 67548489980SSeiya Wang spi0: spi@1100a000 { 67648489980SSeiya Wang compatible = "mediatek,mt8192-spi", 67748489980SSeiya Wang "mediatek,mt6765-spi"; 67848489980SSeiya Wang #address-cells = <1>; 67948489980SSeiya Wang #size-cells = <0>; 68048489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 68148489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 6827f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6837f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6847f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 68548489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 68648489980SSeiya Wang status = "disabled"; 68748489980SSeiya Wang }; 68848489980SSeiya Wang 68918222e05SAllen-KH Cheng pwm0: pwm@1100e000 { 69018222e05SAllen-KH Cheng compatible = "mediatek,mt8183-disp-pwm"; 69118222e05SAllen-KH Cheng reg = <0 0x1100e000 0 0x1000>; 69218222e05SAllen-KH Cheng interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 69318222e05SAllen-KH Cheng #pwm-cells = <2>; 69418222e05SAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 69518222e05SAllen-KH Cheng <&infracfg CLK_INFRA_DISP_PWM>; 69618222e05SAllen-KH Cheng clock-names = "main", "mm"; 69718222e05SAllen-KH Cheng status = "disabled"; 69818222e05SAllen-KH Cheng }; 69918222e05SAllen-KH Cheng 70048489980SSeiya Wang spi1: spi@11010000 { 70148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 70248489980SSeiya Wang "mediatek,mt6765-spi"; 70348489980SSeiya Wang #address-cells = <1>; 70448489980SSeiya Wang #size-cells = <0>; 70548489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 70648489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 7077f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7087f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7097f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 71048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 71148489980SSeiya Wang status = "disabled"; 71248489980SSeiya Wang }; 71348489980SSeiya Wang 71448489980SSeiya Wang spi2: spi@11012000 { 71548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 71648489980SSeiya Wang "mediatek,mt6765-spi"; 71748489980SSeiya Wang #address-cells = <1>; 71848489980SSeiya Wang #size-cells = <0>; 71948489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 72048489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 7217f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7227f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7237f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 72448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 72548489980SSeiya Wang status = "disabled"; 72648489980SSeiya Wang }; 72748489980SSeiya Wang 72848489980SSeiya Wang spi3: spi@11013000 { 72948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 73048489980SSeiya Wang "mediatek,mt6765-spi"; 73148489980SSeiya Wang #address-cells = <1>; 73248489980SSeiya Wang #size-cells = <0>; 73348489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 73448489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 7357f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7367f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7377f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 73848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 73948489980SSeiya Wang status = "disabled"; 74048489980SSeiya Wang }; 74148489980SSeiya Wang 74248489980SSeiya Wang spi4: spi@11018000 { 74348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 74448489980SSeiya Wang "mediatek,mt6765-spi"; 74548489980SSeiya Wang #address-cells = <1>; 74648489980SSeiya Wang #size-cells = <0>; 74748489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 74848489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 7497f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7507f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7517f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 75248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 75348489980SSeiya Wang status = "disabled"; 75448489980SSeiya Wang }; 75548489980SSeiya Wang 75648489980SSeiya Wang spi5: spi@11019000 { 75748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 75848489980SSeiya Wang "mediatek,mt6765-spi"; 75948489980SSeiya Wang #address-cells = <1>; 76048489980SSeiya Wang #size-cells = <0>; 76148489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 76248489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 7637f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7647f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7657f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 76648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 76748489980SSeiya Wang status = "disabled"; 76848489980SSeiya Wang }; 76948489980SSeiya Wang 77048489980SSeiya Wang spi6: spi@1101d000 { 77148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 77248489980SSeiya Wang "mediatek,mt6765-spi"; 77348489980SSeiya Wang #address-cells = <1>; 77448489980SSeiya Wang #size-cells = <0>; 77548489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 77648489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 7777f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7787f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7797f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 78048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 78148489980SSeiya Wang status = "disabled"; 78248489980SSeiya Wang }; 78348489980SSeiya Wang 78448489980SSeiya Wang spi7: spi@1101e000 { 78548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 78648489980SSeiya Wang "mediatek,mt6765-spi"; 78748489980SSeiya Wang #address-cells = <1>; 78848489980SSeiya Wang #size-cells = <0>; 78948489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 79048489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 7917f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7927f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7937f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 79448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 79548489980SSeiya Wang status = "disabled"; 79648489980SSeiya Wang }; 79748489980SSeiya Wang 798c63556ecSAllen-KH Cheng scp: scp@10500000 { 799c63556ecSAllen-KH Cheng compatible = "mediatek,mt8192-scp"; 800c63556ecSAllen-KH Cheng reg = <0 0x10500000 0 0x100000>, 801c7510476SNícolas F. R. A. Prado <0 0x10720000 0 0xe0000>, 802c7510476SNícolas F. R. A. Prado <0 0x10700000 0 0x8000>; 803c7510476SNícolas F. R. A. Prado reg-names = "sram", "cfg", "l1tcm"; 804c63556ecSAllen-KH Cheng interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 805c63556ecSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SCPSYS>; 806c63556ecSAllen-KH Cheng clock-names = "main"; 807c63556ecSAllen-KH Cheng status = "disabled"; 808c63556ecSAllen-KH Cheng }; 809c63556ecSAllen-KH Cheng 810e5aac225SAllen-KH Cheng xhci: usb@11200000 { 811e5aac225SAllen-KH Cheng compatible = "mediatek,mt8192-xhci", 812e5aac225SAllen-KH Cheng "mediatek,mtk-xhci"; 813e5aac225SAllen-KH Cheng reg = <0 0x11200000 0 0x1000>, 814e5aac225SAllen-KH Cheng <0 0x11203e00 0 0x0100>; 815e5aac225SAllen-KH Cheng reg-names = "mac", "ippc"; 816e5aac225SAllen-KH Cheng interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 817e5aac225SAllen-KH Cheng interrupt-names = "host"; 818e5aac225SAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>, 819e5aac225SAllen-KH Cheng <&u3port0 PHY_TYPE_USB3>; 820e5aac225SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 821e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 822e5aac225SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 823e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 824e5aac225SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SSUSB>, 8256210fc2eSNícolas F. R. A. Prado <&apmixedsys CLK_APMIXED_USBPLL>, 8266210fc2eSNícolas F. R. A. Prado <&clk26m>, 8276210fc2eSNícolas F. R. A. Prado <&clk26m>, 8286210fc2eSNícolas F. R. A. Prado <&infracfg CLK_INFRA_SSUSB_XHCI>; 8296210fc2eSNícolas F. R. A. Prado clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 8306210fc2eSNícolas F. R. A. Prado "xhci_ck"; 831e5aac225SAllen-KH Cheng wakeup-source; 832e5aac225SAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 102>; 833e5aac225SAllen-KH Cheng status = "disabled"; 834e5aac225SAllen-KH Cheng }; 835e5aac225SAllen-KH Cheng 8361afd9b62SAllen-KH Cheng audsys: syscon@11210000 { 8371afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audsys", "syscon"; 8381afd9b62SAllen-KH Cheng reg = <0 0x11210000 0 0x2000>; 8391afd9b62SAllen-KH Cheng #clock-cells = <1>; 8401afd9b62SAllen-KH Cheng 8411afd9b62SAllen-KH Cheng afe: mt8192-afe-pcm { 8421afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audio"; 8431afd9b62SAllen-KH Cheng interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 8441afd9b62SAllen-KH Cheng resets = <&watchdog 17>; 8451afd9b62SAllen-KH Cheng reset-names = "audiosys"; 8461afd9b62SAllen-KH Cheng mediatek,apmixedsys = <&apmixedsys>; 8471afd9b62SAllen-KH Cheng mediatek,infracfg = <&infracfg>; 8481afd9b62SAllen-KH Cheng mediatek,topckgen = <&topckgen>; 8491afd9b62SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 8501afd9b62SAllen-KH Cheng clocks = <&audsys CLK_AUD_AFE>, 8511afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC>, 8521afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_PREDIS>, 8531afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC>, 8541afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC>, 8551afd9b62SAllen-KH Cheng <&audsys CLK_AUD_22M>, 8561afd9b62SAllen-KH Cheng <&audsys CLK_AUD_24M>, 8571afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL_TUNER>, 8581afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL2_TUNER>, 8591afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TDM>, 8601afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TML>, 8611afd9b62SAllen-KH Cheng <&audsys CLK_AUD_NLE>, 8621afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_HIRES>, 8631afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES>, 8641afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES_TML>, 8651afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 8661afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC>, 8671afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_PREDIS>, 8681afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_TML>, 8691afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_HIRES>, 8701afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO>, 8711afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO_26M_B>, 8721afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_SEL>, 8731afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 8741afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D4_D4>, 8751afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_1_SEL>, 8761afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1>, 8771afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_2_SEL>, 8781afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2>, 8791afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 8801afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1_D4>, 8811afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 8821afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2_D4>, 8831afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 8841afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 8851afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 8861afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 8871afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 8881afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 8891afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 8901afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 8911afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 8921afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 8931afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV0>, 8941afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV1>, 8951afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV2>, 8961afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV3>, 8971afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV4>, 8981afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIVB>, 8991afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV5>, 9001afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV6>, 9011afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV7>, 9021afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV8>, 9031afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV9>, 9041afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_H_SEL>, 9051afd9b62SAllen-KH Cheng <&clk26m>; 9061afd9b62SAllen-KH Cheng clock-names = "aud_afe_clk", 9071afd9b62SAllen-KH Cheng "aud_dac_clk", 9081afd9b62SAllen-KH Cheng "aud_dac_predis_clk", 9091afd9b62SAllen-KH Cheng "aud_adc_clk", 9101afd9b62SAllen-KH Cheng "aud_adda6_adc_clk", 9111afd9b62SAllen-KH Cheng "aud_apll22m_clk", 9121afd9b62SAllen-KH Cheng "aud_apll24m_clk", 9131afd9b62SAllen-KH Cheng "aud_apll1_tuner_clk", 9141afd9b62SAllen-KH Cheng "aud_apll2_tuner_clk", 9151afd9b62SAllen-KH Cheng "aud_tdm_clk", 9161afd9b62SAllen-KH Cheng "aud_tml_clk", 9171afd9b62SAllen-KH Cheng "aud_nle", 9181afd9b62SAllen-KH Cheng "aud_dac_hires_clk", 9191afd9b62SAllen-KH Cheng "aud_adc_hires_clk", 9201afd9b62SAllen-KH Cheng "aud_adc_hires_tml", 9211afd9b62SAllen-KH Cheng "aud_adda6_adc_hires_clk", 9221afd9b62SAllen-KH Cheng "aud_3rd_dac_clk", 9231afd9b62SAllen-KH Cheng "aud_3rd_dac_predis_clk", 9241afd9b62SAllen-KH Cheng "aud_3rd_dac_tml", 9251afd9b62SAllen-KH Cheng "aud_3rd_dac_hires_clk", 9261afd9b62SAllen-KH Cheng "aud_infra_clk", 9271afd9b62SAllen-KH Cheng "aud_infra_26m_clk", 9281afd9b62SAllen-KH Cheng "top_mux_audio", 9291afd9b62SAllen-KH Cheng "top_mux_audio_int", 9301afd9b62SAllen-KH Cheng "top_mainpll_d4_d4", 9311afd9b62SAllen-KH Cheng "top_mux_aud_1", 9321afd9b62SAllen-KH Cheng "top_apll1_ck", 9331afd9b62SAllen-KH Cheng "top_mux_aud_2", 9341afd9b62SAllen-KH Cheng "top_apll2_ck", 9351afd9b62SAllen-KH Cheng "top_mux_aud_eng1", 9361afd9b62SAllen-KH Cheng "top_apll1_d4", 9371afd9b62SAllen-KH Cheng "top_mux_aud_eng2", 9381afd9b62SAllen-KH Cheng "top_apll2_d4", 9391afd9b62SAllen-KH Cheng "top_i2s0_m_sel", 9401afd9b62SAllen-KH Cheng "top_i2s1_m_sel", 9411afd9b62SAllen-KH Cheng "top_i2s2_m_sel", 9421afd9b62SAllen-KH Cheng "top_i2s3_m_sel", 9431afd9b62SAllen-KH Cheng "top_i2s4_m_sel", 9441afd9b62SAllen-KH Cheng "top_i2s5_m_sel", 9451afd9b62SAllen-KH Cheng "top_i2s6_m_sel", 9461afd9b62SAllen-KH Cheng "top_i2s7_m_sel", 9471afd9b62SAllen-KH Cheng "top_i2s8_m_sel", 9481afd9b62SAllen-KH Cheng "top_i2s9_m_sel", 9491afd9b62SAllen-KH Cheng "top_apll12_div0", 9501afd9b62SAllen-KH Cheng "top_apll12_div1", 9511afd9b62SAllen-KH Cheng "top_apll12_div2", 9521afd9b62SAllen-KH Cheng "top_apll12_div3", 9531afd9b62SAllen-KH Cheng "top_apll12_div4", 9541afd9b62SAllen-KH Cheng "top_apll12_divb", 9551afd9b62SAllen-KH Cheng "top_apll12_div5", 9561afd9b62SAllen-KH Cheng "top_apll12_div6", 9571afd9b62SAllen-KH Cheng "top_apll12_div7", 9581afd9b62SAllen-KH Cheng "top_apll12_div8", 9591afd9b62SAllen-KH Cheng "top_apll12_div9", 9601afd9b62SAllen-KH Cheng "top_mux_audio_h", 9611afd9b62SAllen-KH Cheng "top_clk26m_clk"; 9621afd9b62SAllen-KH Cheng }; 9631afd9b62SAllen-KH Cheng }; 9641afd9b62SAllen-KH Cheng 965e530d080SAllen-KH Cheng pcie: pcie@11230000 { 966e530d080SAllen-KH Cheng compatible = "mediatek,mt8192-pcie"; 967e530d080SAllen-KH Cheng device_type = "pci"; 968e530d080SAllen-KH Cheng reg = <0 0x11230000 0 0x2000>; 969e530d080SAllen-KH Cheng reg-names = "pcie-mac"; 970e530d080SAllen-KH Cheng #address-cells = <3>; 971e530d080SAllen-KH Cheng #size-cells = <2>; 972e530d080SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 973e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_26M>, 974e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_96M>, 975e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_32K>, 976e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_PERI_26M>, 977e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 978e530d080SAllen-KH Cheng clock-names = "pl_250m", "tl_26m", "tl_96m", 979e530d080SAllen-KH Cheng "tl_32k", "peri_26m", "top_133m"; 980e530d080SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 981e530d080SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 982e530d080SAllen-KH Cheng interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 983e530d080SAllen-KH Cheng bus-range = <0x00 0xff>; 984e530d080SAllen-KH Cheng ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 985e530d080SAllen-KH Cheng <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 986e530d080SAllen-KH Cheng #interrupt-cells = <1>; 987e530d080SAllen-KH Cheng interrupt-map-mask = <0 0 0 7>; 988e530d080SAllen-KH Cheng interrupt-map = <0 0 0 1 &pcie_intc0 0>, 989e530d080SAllen-KH Cheng <0 0 0 2 &pcie_intc0 1>, 990e530d080SAllen-KH Cheng <0 0 0 3 &pcie_intc0 2>, 991e530d080SAllen-KH Cheng <0 0 0 4 &pcie_intc0 3>; 992e530d080SAllen-KH Cheng 993e530d080SAllen-KH Cheng pcie_intc0: interrupt-controller { 994e530d080SAllen-KH Cheng interrupt-controller; 995e530d080SAllen-KH Cheng #address-cells = <0>; 996e530d080SAllen-KH Cheng #interrupt-cells = <1>; 997e530d080SAllen-KH Cheng }; 998e530d080SAllen-KH Cheng }; 999e530d080SAllen-KH Cheng 1000d0a197a0Sbayi cheng nor_flash: spi@11234000 { 1001d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 1002d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 1003d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 1004aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 1005aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 1006aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 1007d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 1008aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 1009aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 1010d0a197a0Sbayi cheng #address-cells = <1>; 1011d0a197a0Sbayi cheng #size-cells = <0>; 101227f0eb16SAllen-KH Cheng status = "disabled"; 1013d0a197a0Sbayi cheng }; 1014d0a197a0Sbayi cheng 10154d50a433SAllen-KH Cheng efuse: efuse@11c10000 { 1016fda0541cSChunfeng Yun compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 10174d50a433SAllen-KH Cheng reg = <0 0x11c10000 0 0x1000>; 10184d50a433SAllen-KH Cheng #address-cells = <1>; 10194d50a433SAllen-KH Cheng #size-cells = <1>; 10204d50a433SAllen-KH Cheng 10214d50a433SAllen-KH Cheng lvts_e_data1: data1@1c0 { 10224d50a433SAllen-KH Cheng reg = <0x1c0 0x58>; 10234d50a433SAllen-KH Cheng }; 10244d50a433SAllen-KH Cheng 10254d50a433SAllen-KH Cheng svs_calibration: calib@580 { 10264d50a433SAllen-KH Cheng reg = <0x580 0x68>; 10274d50a433SAllen-KH Cheng }; 10284d50a433SAllen-KH Cheng }; 10294d50a433SAllen-KH Cheng 10307f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 103148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 103248489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 103348489980SSeiya Wang <0 0x10217300 0 0x80>; 103448489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 103522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 103622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 103748489980SSeiya Wang clock-names = "main", "dma"; 103848489980SSeiya Wang clock-div = <1>; 103948489980SSeiya Wang #address-cells = <1>; 104048489980SSeiya Wang #size-cells = <0>; 104148489980SSeiya Wang status = "disabled"; 104248489980SSeiya Wang }; 104348489980SSeiya Wang 10445d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 10455d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 10465d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 10475d2b897bSChun-Jie Chen #clock-cells = <1>; 10485d2b897bSChun-Jie Chen }; 10495d2b897bSChun-Jie Chen 10507f1a9f47SFabien Parent i2c7: i2c@11d00000 { 105148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 105248489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 105348489980SSeiya Wang <0 0x10217600 0 0x180>; 105448489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 105522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 105622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 105748489980SSeiya Wang clock-names = "main", "dma"; 105848489980SSeiya Wang clock-div = <1>; 105948489980SSeiya Wang #address-cells = <1>; 106048489980SSeiya Wang #size-cells = <0>; 106148489980SSeiya Wang status = "disabled"; 106248489980SSeiya Wang }; 106348489980SSeiya Wang 10647f1a9f47SFabien Parent i2c8: i2c@11d01000 { 106548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 106648489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 106748489980SSeiya Wang <0 0x10217780 0 0x180>; 106848489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 106922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 107022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 107148489980SSeiya Wang clock-names = "main", "dma"; 107248489980SSeiya Wang clock-div = <1>; 107348489980SSeiya Wang #address-cells = <1>; 107448489980SSeiya Wang #size-cells = <0>; 107548489980SSeiya Wang status = "disabled"; 107648489980SSeiya Wang }; 107748489980SSeiya Wang 10787f1a9f47SFabien Parent i2c9: i2c@11d02000 { 107948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 108048489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 108148489980SSeiya Wang <0 0x10217900 0 0x180>; 108248489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 108322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 108422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 108548489980SSeiya Wang clock-names = "main", "dma"; 108648489980SSeiya Wang clock-div = <1>; 108748489980SSeiya Wang #address-cells = <1>; 108848489980SSeiya Wang #size-cells = <0>; 108948489980SSeiya Wang status = "disabled"; 109048489980SSeiya Wang }; 109148489980SSeiya Wang 10925d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 10935d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 10945d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 10955d2b897bSChun-Jie Chen #clock-cells = <1>; 10965d2b897bSChun-Jie Chen }; 10975d2b897bSChun-Jie Chen 10987f1a9f47SFabien Parent i2c1: i2c@11d20000 { 109948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 110048489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 110148489980SSeiya Wang <0 0x10217100 0 0x80>; 110248489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 110322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 110422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 110548489980SSeiya Wang clock-names = "main", "dma"; 110648489980SSeiya Wang clock-div = <1>; 110748489980SSeiya Wang #address-cells = <1>; 110848489980SSeiya Wang #size-cells = <0>; 110948489980SSeiya Wang status = "disabled"; 111048489980SSeiya Wang }; 111148489980SSeiya Wang 11127f1a9f47SFabien Parent i2c2: i2c@11d21000 { 111348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 111448489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 111548489980SSeiya Wang <0 0x10217180 0 0x180>; 111648489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 111722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 111822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 111948489980SSeiya Wang clock-names = "main", "dma"; 112048489980SSeiya Wang clock-div = <1>; 112148489980SSeiya Wang #address-cells = <1>; 112248489980SSeiya Wang #size-cells = <0>; 112348489980SSeiya Wang status = "disabled"; 112448489980SSeiya Wang }; 112548489980SSeiya Wang 11267f1a9f47SFabien Parent i2c4: i2c@11d22000 { 112748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 112848489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 112948489980SSeiya Wang <0 0x10217380 0 0x180>; 113048489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 113122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 113222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 113348489980SSeiya Wang clock-names = "main", "dma"; 113448489980SSeiya Wang clock-div = <1>; 113548489980SSeiya Wang #address-cells = <1>; 113648489980SSeiya Wang #size-cells = <0>; 113748489980SSeiya Wang status = "disabled"; 113848489980SSeiya Wang }; 113948489980SSeiya Wang 11405d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 11415d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 11425d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 11435d2b897bSChun-Jie Chen #clock-cells = <1>; 11445d2b897bSChun-Jie Chen }; 11455d2b897bSChun-Jie Chen 11467f1a9f47SFabien Parent i2c5: i2c@11e00000 { 114748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 114848489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 114948489980SSeiya Wang <0 0x10217500 0 0x80>; 115048489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 115122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 115222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 115348489980SSeiya Wang clock-names = "main", "dma"; 115448489980SSeiya Wang clock-div = <1>; 115548489980SSeiya Wang #address-cells = <1>; 115648489980SSeiya Wang #size-cells = <0>; 115748489980SSeiya Wang status = "disabled"; 115848489980SSeiya Wang }; 115948489980SSeiya Wang 11605d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 11615d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 11625d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 11635d2b897bSChun-Jie Chen #clock-cells = <1>; 11645d2b897bSChun-Jie Chen }; 11655d2b897bSChun-Jie Chen 116640de66b8SAllen-KH Cheng u3phy0: t-phy@11e40000 { 116740de66b8SAllen-KH Cheng compatible = "mediatek,mt8192-tphy", 116840de66b8SAllen-KH Cheng "mediatek,generic-tphy-v2"; 116940de66b8SAllen-KH Cheng #address-cells = <1>; 117040de66b8SAllen-KH Cheng #size-cells = <1>; 117140de66b8SAllen-KH Cheng ranges = <0x0 0x0 0x11e40000 0x1000>; 117240de66b8SAllen-KH Cheng 117340de66b8SAllen-KH Cheng u2port0: usb-phy@0 { 117440de66b8SAllen-KH Cheng reg = <0x0 0x700>; 117540de66b8SAllen-KH Cheng clocks = <&clk26m>; 117640de66b8SAllen-KH Cheng clock-names = "ref"; 117740de66b8SAllen-KH Cheng #phy-cells = <1>; 117840de66b8SAllen-KH Cheng }; 117940de66b8SAllen-KH Cheng 118040de66b8SAllen-KH Cheng u3port0: usb-phy@700 { 118140de66b8SAllen-KH Cheng reg = <0x700 0x900>; 118240de66b8SAllen-KH Cheng clocks = <&clk26m>; 118340de66b8SAllen-KH Cheng clock-names = "ref"; 118440de66b8SAllen-KH Cheng #phy-cells = <1>; 118540de66b8SAllen-KH Cheng }; 118640de66b8SAllen-KH Cheng }; 118740de66b8SAllen-KH Cheng 118885c4ec6fSAllen-KH Cheng mipi_tx0: dsi-phy@11e50000 { 118985c4ec6fSAllen-KH Cheng compatible = "mediatek,mt8183-mipi-tx"; 119085c4ec6fSAllen-KH Cheng reg = <0 0x11e50000 0 0x1000>; 119185c4ec6fSAllen-KH Cheng clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 119285c4ec6fSAllen-KH Cheng #clock-cells = <0>; 119385c4ec6fSAllen-KH Cheng #phy-cells = <0>; 119485c4ec6fSAllen-KH Cheng clock-output-names = "mipi_tx0_pll"; 119585c4ec6fSAllen-KH Cheng status = "disabled"; 119685c4ec6fSAllen-KH Cheng }; 119785c4ec6fSAllen-KH Cheng 11987f1a9f47SFabien Parent i2c0: i2c@11f00000 { 119948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 120048489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 120148489980SSeiya Wang <0 0x10217080 0 0x80>; 120248489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 120322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 120422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 120548489980SSeiya Wang clock-names = "main", "dma"; 120648489980SSeiya Wang clock-div = <1>; 120748489980SSeiya Wang #address-cells = <1>; 120848489980SSeiya Wang #size-cells = <0>; 120948489980SSeiya Wang status = "disabled"; 121048489980SSeiya Wang }; 121148489980SSeiya Wang 12127f1a9f47SFabien Parent i2c6: i2c@11f01000 { 121348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 121448489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 121548489980SSeiya Wang <0 0x10217580 0 0x80>; 121648489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 121722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 121822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 121948489980SSeiya Wang clock-names = "main", "dma"; 122048489980SSeiya Wang clock-div = <1>; 122148489980SSeiya Wang #address-cells = <1>; 122248489980SSeiya Wang #size-cells = <0>; 122348489980SSeiya Wang status = "disabled"; 122448489980SSeiya Wang }; 12255d2b897bSChun-Jie Chen 12265d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 12275d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 12285d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 12295d2b897bSChun-Jie Chen #clock-cells = <1>; 12305d2b897bSChun-Jie Chen }; 12315d2b897bSChun-Jie Chen 12325d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 12335d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 12345d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 12355d2b897bSChun-Jie Chen #clock-cells = <1>; 12365d2b897bSChun-Jie Chen }; 12375d2b897bSChun-Jie Chen 1238db61337eSAllen-KH Cheng mmc0: mmc@11f60000 { 1239db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1240db61337eSAllen-KH Cheng reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1241db61337eSAllen-KH Cheng interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1242db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1243db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1244db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1245db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1246db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1247db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1248db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1249db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1250db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1251db61337eSAllen-KH Cheng status = "disabled"; 1252db61337eSAllen-KH Cheng }; 1253db61337eSAllen-KH Cheng 1254db61337eSAllen-KH Cheng mmc1: mmc@11f70000 { 1255db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1256db61337eSAllen-KH Cheng reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1257db61337eSAllen-KH Cheng interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1258db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1259db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1260db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1261db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1262db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1263db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1264db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1265db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1266db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1267db61337eSAllen-KH Cheng status = "disabled"; 12685d2b897bSChun-Jie Chen }; 12695d2b897bSChun-Jie Chen 12705d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 12715d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 12725d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 12735d2b897bSChun-Jie Chen #clock-cells = <1>; 12745d2b897bSChun-Jie Chen }; 12755d2b897bSChun-Jie Chen 12765d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 12775d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 12785d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 12795d2b897bSChun-Jie Chen #clock-cells = <1>; 12807d355378SAllen-KH Cheng #reset-cells = <1>; 1281b4b75bacSAllen-KH Cheng mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1282b4b75bacSAllen-KH Cheng <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1283b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1284b4b75bacSAllen-KH Cheng }; 1285b4b75bacSAllen-KH Cheng 1286b4b75bacSAllen-KH Cheng mutex: mutex@14001000 { 1287b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-mutex"; 1288b4b75bacSAllen-KH Cheng reg = <0 0x14001000 0 0x1000>; 1289b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1290b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1291b4b75bacSAllen-KH Cheng mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1292b4b75bacSAllen-KH Cheng <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1293b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 12945d2b897bSChun-Jie Chen }; 12955d2b897bSChun-Jie Chen 12964a65b0f1SAllen-KH Cheng smi_common: smi@14002000 { 12974a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-common"; 12984a65b0f1SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 12994a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 13004a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 13014a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 13024a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>; 13034a65b0f1SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 13044a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 13054a65b0f1SAllen-KH Cheng }; 13064a65b0f1SAllen-KH Cheng 13074a65b0f1SAllen-KH Cheng larb0: larb@14003000 { 13084a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13094a65b0f1SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 13104a65b0f1SAllen-KH Cheng mediatek,larb-id = <0>; 13114a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13124a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 13134a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13144a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 13154a65b0f1SAllen-KH Cheng }; 13164a65b0f1SAllen-KH Cheng 13174a65b0f1SAllen-KH Cheng larb1: larb@14004000 { 13184a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 13194a65b0f1SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 13204a65b0f1SAllen-KH Cheng mediatek,larb-id = <1>; 13214a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 13224a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 13234a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 13244a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 13254a65b0f1SAllen-KH Cheng }; 13264a65b0f1SAllen-KH Cheng 1327b4b75bacSAllen-KH Cheng ovl0: ovl@14005000 { 1328b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl"; 1329b4b75bacSAllen-KH Cheng reg = <0 0x14005000 0 0x1000>; 1330b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1331b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0>; 1332b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1333b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1334b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1335b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1336b4b75bacSAllen-KH Cheng }; 1337b4b75bacSAllen-KH Cheng 1338b4b75bacSAllen-KH Cheng ovl_2l0: ovl@14006000 { 1339b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1340b4b75bacSAllen-KH Cheng reg = <0 0x14006000 0 0x1000>; 1341b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1342b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1343b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1344b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1345b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1346b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1347b4b75bacSAllen-KH Cheng }; 1348b4b75bacSAllen-KH Cheng 1349b4b75bacSAllen-KH Cheng rdma0: rdma@14007000 { 1350b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1351b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1352b4b75bacSAllen-KH Cheng reg = <0 0x14007000 0 0x1000>; 1353b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1354b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1355b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1356b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <5120>; 1357b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1358b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1359b4b75bacSAllen-KH Cheng }; 1360b4b75bacSAllen-KH Cheng 1361b4b75bacSAllen-KH Cheng color0: color@14009000 { 1362b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-color", 1363b4b75bacSAllen-KH Cheng "mediatek,mt8173-disp-color"; 1364b4b75bacSAllen-KH Cheng reg = <0 0x14009000 0 0x1000>; 1365b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1366b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1367b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1368b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1369b4b75bacSAllen-KH Cheng }; 1370b4b75bacSAllen-KH Cheng 1371b4b75bacSAllen-KH Cheng ccorr0: ccorr@1400a000 { 1372b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ccorr"; 1373b4b75bacSAllen-KH Cheng reg = <0 0x1400a000 0 0x1000>; 1374b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1375b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1376b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1377b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1378b4b75bacSAllen-KH Cheng }; 1379b4b75bacSAllen-KH Cheng 1380b4b75bacSAllen-KH Cheng aal0: aal@1400b000 { 1381b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-aal", 1382b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-aal"; 1383b4b75bacSAllen-KH Cheng reg = <0 0x1400b000 0 0x1000>; 1384b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1385b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1386b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_AAL0>; 1387b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1388b4b75bacSAllen-KH Cheng }; 1389b4b75bacSAllen-KH Cheng 1390b4b75bacSAllen-KH Cheng gamma0: gamma@1400c000 { 1391b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-gamma", 1392b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-gamma"; 1393b4b75bacSAllen-KH Cheng reg = <0 0x1400c000 0 0x1000>; 1394b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1395b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1396b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1397b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1398b4b75bacSAllen-KH Cheng }; 1399b4b75bacSAllen-KH Cheng 1400b4b75bacSAllen-KH Cheng postmask0: postmask@1400d000 { 1401b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-postmask"; 1402b4b75bacSAllen-KH Cheng reg = <0 0x1400d000 0 0x1000>; 1403b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1404b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1405b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1406b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1407b4b75bacSAllen-KH Cheng }; 1408b4b75bacSAllen-KH Cheng 1409b4b75bacSAllen-KH Cheng dither0: dither@1400e000 { 1410b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-dither", 1411b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-dither"; 1412b4b75bacSAllen-KH Cheng reg = <0 0x1400e000 0 0x1000>; 1413b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1414b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1415b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1416b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1417b4b75bacSAllen-KH Cheng }; 1418b4b75bacSAllen-KH Cheng 14190708ed7cSAllen-KH Cheng dsi0: dsi@14010000 { 14200708ed7cSAllen-KH Cheng compatible = "mediatek,mt8183-dsi"; 14210708ed7cSAllen-KH Cheng reg = <0 0x14010000 0 0x1000>; 14220708ed7cSAllen-KH Cheng interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 14230708ed7cSAllen-KH Cheng clocks = <&mmsys CLK_MM_DSI0>, 14240708ed7cSAllen-KH Cheng <&mmsys CLK_MM_DSI_DSI0>, 14250708ed7cSAllen-KH Cheng <&mipi_tx0>; 14260708ed7cSAllen-KH Cheng clock-names = "engine", "digital", "hs"; 14270708ed7cSAllen-KH Cheng phys = <&mipi_tx0>; 14280708ed7cSAllen-KH Cheng phy-names = "dphy"; 14290708ed7cSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14300708ed7cSAllen-KH Cheng resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 14310708ed7cSAllen-KH Cheng status = "disabled"; 14320708ed7cSAllen-KH Cheng 14330708ed7cSAllen-KH Cheng port { 14340708ed7cSAllen-KH Cheng dsi_out: endpoint { }; 14350708ed7cSAllen-KH Cheng }; 14360708ed7cSAllen-KH Cheng }; 14370708ed7cSAllen-KH Cheng 1438b4b75bacSAllen-KH Cheng ovl_2l2: ovl@14014000 { 1439b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1440b4b75bacSAllen-KH Cheng reg = <0 0x14014000 0 0x1000>; 1441b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1442b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1443b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1444b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1445b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1446b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1447b4b75bacSAllen-KH Cheng }; 1448b4b75bacSAllen-KH Cheng 1449b4b75bacSAllen-KH Cheng rdma4: rdma@14015000 { 1450b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1451b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1452b4b75bacSAllen-KH Cheng reg = <0 0x14015000 0 0x1000>; 1453b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1454b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1455b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1456b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1457b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <2048>; 1458b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1459b4b75bacSAllen-KH Cheng }; 1460b4b75bacSAllen-KH Cheng 1461b2edd519SAllen-KH Cheng dpi0: dpi@14016000 { 1462b2edd519SAllen-KH Cheng compatible = "mediatek,mt8192-dpi"; 1463b2edd519SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1464b2edd519SAllen-KH Cheng interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1465b2edd519SAllen-KH Cheng clocks = <&mmsys CLK_MM_DPI_DPI0>, 1466b2edd519SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI0>, 1467b2edd519SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 1468b2edd519SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 1469b2edd519SAllen-KH Cheng status = "disabled"; 1470b2edd519SAllen-KH Cheng }; 1471b2edd519SAllen-KH Cheng 14724a65b0f1SAllen-KH Cheng iommu0: m4u@1401d000 { 14734a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-m4u"; 14744a65b0f1SAllen-KH Cheng reg = <0 0x1401d000 0 0x1000>; 14754a65b0f1SAllen-KH Cheng mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 14764a65b0f1SAllen-KH Cheng <&larb4>, <&larb5>, <&larb7>, 14774a65b0f1SAllen-KH Cheng <&larb9>, <&larb11>, <&larb13>, 14784a65b0f1SAllen-KH Cheng <&larb14>, <&larb16>, <&larb17>, 14794a65b0f1SAllen-KH Cheng <&larb18>, <&larb19>, <&larb20>; 14804a65b0f1SAllen-KH Cheng interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 14814a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 14824a65b0f1SAllen-KH Cheng clock-names = "bclk"; 14834a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14844a65b0f1SAllen-KH Cheng #iommu-cells = <1>; 14854a65b0f1SAllen-KH Cheng }; 14864a65b0f1SAllen-KH Cheng 14875d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 14885d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 14895d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 14905d2b897bSChun-Jie Chen #clock-cells = <1>; 14915d2b897bSChun-Jie Chen }; 14925d2b897bSChun-Jie Chen 14934a65b0f1SAllen-KH Cheng larb9: larb@1502e000 { 14944a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14954a65b0f1SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 14964a65b0f1SAllen-KH Cheng mediatek,larb-id = <9>; 14974a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14984a65b0f1SAllen-KH Cheng clocks = <&imgsys CLK_IMG_LARB9>, 14994a65b0f1SAllen-KH Cheng <&imgsys CLK_IMG_LARB9>; 15004a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15014a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 15024a65b0f1SAllen-KH Cheng }; 15034a65b0f1SAllen-KH Cheng 15045d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 15055d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 15065d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 15075d2b897bSChun-Jie Chen #clock-cells = <1>; 15085d2b897bSChun-Jie Chen }; 15095d2b897bSChun-Jie Chen 15104a65b0f1SAllen-KH Cheng larb11: larb@1582e000 { 15114a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15124a65b0f1SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 15134a65b0f1SAllen-KH Cheng mediatek,larb-id = <11>; 15144a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15154a65b0f1SAllen-KH Cheng clocks = <&imgsys2 CLK_IMG2_LARB11>, 15164a65b0f1SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB11>; 15174a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15184a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 15194a65b0f1SAllen-KH Cheng }; 15204a65b0f1SAllen-KH Cheng 15214a65b0f1SAllen-KH Cheng larb5: larb@1600d000 { 15224a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15234a65b0f1SAllen-KH Cheng reg = <0 0x1600d000 0 0x1000>; 15244a65b0f1SAllen-KH Cheng mediatek,larb-id = <5>; 15254a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15264a65b0f1SAllen-KH Cheng clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 15274a65b0f1SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 15284a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15294a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 15304a65b0f1SAllen-KH Cheng }; 15314a65b0f1SAllen-KH Cheng 15325d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 15335d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 15345d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 15355d2b897bSChun-Jie Chen #clock-cells = <1>; 15365d2b897bSChun-Jie Chen }; 15375d2b897bSChun-Jie Chen 15384a65b0f1SAllen-KH Cheng larb4: larb@1602e000 { 15394a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15404a65b0f1SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 15414a65b0f1SAllen-KH Cheng mediatek,larb-id = <4>; 15424a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15434a65b0f1SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 15444a65b0f1SAllen-KH Cheng <&vdecsys CLK_VDEC_SOC_LARB1>; 15454a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15464a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 15474a65b0f1SAllen-KH Cheng }; 15484a65b0f1SAllen-KH Cheng 15495d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 15505d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 15515d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 15525d2b897bSChun-Jie Chen #clock-cells = <1>; 15535d2b897bSChun-Jie Chen }; 15545d2b897bSChun-Jie Chen 15555d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 15565d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 15575d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 15585d2b897bSChun-Jie Chen #clock-cells = <1>; 15595d2b897bSChun-Jie Chen }; 15605d2b897bSChun-Jie Chen 15614a65b0f1SAllen-KH Cheng larb7: larb@17010000 { 15624a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 15634a65b0f1SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 15644a65b0f1SAllen-KH Cheng mediatek,larb-id = <7>; 15654a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 15664a65b0f1SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET0_LARB>, 15674a65b0f1SAllen-KH Cheng <&vencsys CLK_VENC_SET1_VENC>; 15684a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 15694a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 15704a65b0f1SAllen-KH Cheng }; 15714a65b0f1SAllen-KH Cheng 1572aa8f3711SAllen-KH Cheng vcodec_enc: vcodec@17020000 { 1573aa8f3711SAllen-KH Cheng compatible = "mediatek,mt8192-vcodec-enc"; 1574aa8f3711SAllen-KH Cheng reg = <0 0x17020000 0 0x2000>; 1575aa8f3711SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1576aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REC>, 1577aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1578aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1579aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1580aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1581aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1582aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1583aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1584aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1585aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1586aa8f3711SAllen-KH Cheng interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1587aa8f3711SAllen-KH Cheng mediatek,scp = <&scp>; 1588aa8f3711SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1589aa8f3711SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET1_VENC>; 1590aa8f3711SAllen-KH Cheng clock-names = "venc-set1"; 1591aa8f3711SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1592aa8f3711SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1593aa8f3711SAllen-KH Cheng }; 1594aa8f3711SAllen-KH Cheng 15955d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 15965d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 15975d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 15985d2b897bSChun-Jie Chen #clock-cells = <1>; 15995d2b897bSChun-Jie Chen }; 16005d2b897bSChun-Jie Chen 16014a65b0f1SAllen-KH Cheng larb13: larb@1a001000 { 16024a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16034a65b0f1SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 16044a65b0f1SAllen-KH Cheng mediatek,larb-id = <13>; 16054a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16064a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 16074a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB13>; 16084a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16094a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 16104a65b0f1SAllen-KH Cheng }; 16114a65b0f1SAllen-KH Cheng 16124a65b0f1SAllen-KH Cheng larb14: larb@1a002000 { 16134a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16144a65b0f1SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 16154a65b0f1SAllen-KH Cheng mediatek,larb-id = <14>; 16164a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16174a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 16184a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB14>; 16194a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16204a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 16214a65b0f1SAllen-KH Cheng }; 16224a65b0f1SAllen-KH Cheng 16234a65b0f1SAllen-KH Cheng larb16: larb@1a00f000 { 16244a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16254a65b0f1SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 16264a65b0f1SAllen-KH Cheng mediatek,larb-id = <16>; 16274a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16284a65b0f1SAllen-KH Cheng clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 16294a65b0f1SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX>; 16304a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16314a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 16324a65b0f1SAllen-KH Cheng }; 16334a65b0f1SAllen-KH Cheng 16344a65b0f1SAllen-KH Cheng larb17: larb@1a010000 { 16354a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16364a65b0f1SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 16374a65b0f1SAllen-KH Cheng mediatek,larb-id = <17>; 16384a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16394a65b0f1SAllen-KH Cheng clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 16404a65b0f1SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX>; 16414a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16424a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 16434a65b0f1SAllen-KH Cheng }; 16444a65b0f1SAllen-KH Cheng 16454a65b0f1SAllen-KH Cheng larb18: larb@1a011000 { 16464a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16474a65b0f1SAllen-KH Cheng reg = <0 0x1a011000 0 0x1000>; 16484a65b0f1SAllen-KH Cheng mediatek,larb-id = <18>; 16494a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16504a65b0f1SAllen-KH Cheng clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 16514a65b0f1SAllen-KH Cheng <&camsys_rawc CLK_CAM_RAWC_CAM>; 16524a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16534a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 16544a65b0f1SAllen-KH Cheng }; 16554a65b0f1SAllen-KH Cheng 16565d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 16575d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 16585d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 16595d2b897bSChun-Jie Chen #clock-cells = <1>; 16605d2b897bSChun-Jie Chen }; 16615d2b897bSChun-Jie Chen 16625d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 16635d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 16645d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 16655d2b897bSChun-Jie Chen #clock-cells = <1>; 16665d2b897bSChun-Jie Chen }; 16675d2b897bSChun-Jie Chen 16685d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 16695d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 16705d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 16715d2b897bSChun-Jie Chen #clock-cells = <1>; 16725d2b897bSChun-Jie Chen }; 16735d2b897bSChun-Jie Chen 16745d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 16755d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 16765d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 16775d2b897bSChun-Jie Chen #clock-cells = <1>; 16785d2b897bSChun-Jie Chen }; 16795d2b897bSChun-Jie Chen 16804a65b0f1SAllen-KH Cheng larb20: larb@1b00f000 { 16814a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16824a65b0f1SAllen-KH Cheng reg = <0 0x1b00f000 0 0x1000>; 16834a65b0f1SAllen-KH Cheng mediatek,larb-id = <20>; 16844a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16854a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 16864a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB20>; 16874a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16884a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 16894a65b0f1SAllen-KH Cheng }; 16904a65b0f1SAllen-KH Cheng 16914a65b0f1SAllen-KH Cheng larb19: larb@1b10f000 { 16924a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16934a65b0f1SAllen-KH Cheng reg = <0 0x1b10f000 0 0x1000>; 16944a65b0f1SAllen-KH Cheng mediatek,larb-id = <19>; 16954a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16964a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 16974a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB19>; 16984a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16994a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 17004a65b0f1SAllen-KH Cheng }; 17014a65b0f1SAllen-KH Cheng 17025d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 17035d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 17045d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 17055d2b897bSChun-Jie Chen #clock-cells = <1>; 17065d2b897bSChun-Jie Chen }; 17074a65b0f1SAllen-KH Cheng 17084a65b0f1SAllen-KH Cheng larb2: larb@1f002000 { 17094a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17104a65b0f1SAllen-KH Cheng reg = <0 0x1f002000 0 0x1000>; 17114a65b0f1SAllen-KH Cheng mediatek,larb-id = <2>; 17124a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17134a65b0f1SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, 17144a65b0f1SAllen-KH Cheng <&mdpsys CLK_MDP_SMI0>; 17154a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17164a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 17174a65b0f1SAllen-KH Cheng }; 171848489980SSeiya Wang }; 171948489980SSeiya Wang}; 1720