148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 948489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 1148489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 12994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 1348489980SSeiya Wang 1448489980SSeiya Wang/ { 1548489980SSeiya Wang compatible = "mediatek,mt8192"; 1648489980SSeiya Wang interrupt-parent = <&gic>; 1748489980SSeiya Wang #address-cells = <2>; 1848489980SSeiya Wang #size-cells = <2>; 1948489980SSeiya Wang 2048489980SSeiya Wang clk26m: oscillator0 { 2148489980SSeiya Wang compatible = "fixed-clock"; 2248489980SSeiya Wang #clock-cells = <0>; 2348489980SSeiya Wang clock-frequency = <26000000>; 2448489980SSeiya Wang clock-output-names = "clk26m"; 2548489980SSeiya Wang }; 2648489980SSeiya Wang 2748489980SSeiya Wang clk32k: oscillator1 { 2848489980SSeiya Wang compatible = "fixed-clock"; 2948489980SSeiya Wang #clock-cells = <0>; 3048489980SSeiya Wang clock-frequency = <32768>; 3148489980SSeiya Wang clock-output-names = "clk32k"; 3248489980SSeiya Wang }; 3348489980SSeiya Wang 3448489980SSeiya Wang cpus { 3548489980SSeiya Wang #address-cells = <1>; 3648489980SSeiya Wang #size-cells = <0>; 3748489980SSeiya Wang 3848489980SSeiya Wang cpu0: cpu@0 { 3948489980SSeiya Wang device_type = "cpu"; 4048489980SSeiya Wang compatible = "arm,cortex-a55"; 4148489980SSeiya Wang reg = <0x000>; 4248489980SSeiya Wang enable-method = "psci"; 4348489980SSeiya Wang clock-frequency = <1701000000>; 449260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 4548489980SSeiya Wang next-level-cache = <&l2_0>; 4648489980SSeiya Wang capacity-dmips-mhz = <530>; 4748489980SSeiya Wang }; 4848489980SSeiya Wang 4948489980SSeiya Wang cpu1: cpu@100 { 5048489980SSeiya Wang device_type = "cpu"; 5148489980SSeiya Wang compatible = "arm,cortex-a55"; 5248489980SSeiya Wang reg = <0x100>; 5348489980SSeiya Wang enable-method = "psci"; 5448489980SSeiya Wang clock-frequency = <1701000000>; 559260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 5648489980SSeiya Wang next-level-cache = <&l2_0>; 5748489980SSeiya Wang capacity-dmips-mhz = <530>; 5848489980SSeiya Wang }; 5948489980SSeiya Wang 6048489980SSeiya Wang cpu2: cpu@200 { 6148489980SSeiya Wang device_type = "cpu"; 6248489980SSeiya Wang compatible = "arm,cortex-a55"; 6348489980SSeiya Wang reg = <0x200>; 6448489980SSeiya Wang enable-method = "psci"; 6548489980SSeiya Wang clock-frequency = <1701000000>; 669260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 6748489980SSeiya Wang next-level-cache = <&l2_0>; 6848489980SSeiya Wang capacity-dmips-mhz = <530>; 6948489980SSeiya Wang }; 7048489980SSeiya Wang 7148489980SSeiya Wang cpu3: cpu@300 { 7248489980SSeiya Wang device_type = "cpu"; 7348489980SSeiya Wang compatible = "arm,cortex-a55"; 7448489980SSeiya Wang reg = <0x300>; 7548489980SSeiya Wang enable-method = "psci"; 7648489980SSeiya Wang clock-frequency = <1701000000>; 779260918dSJames Liao cpu-idle-states = <&cpuoff_l &clusteroff_l>; 7848489980SSeiya Wang next-level-cache = <&l2_0>; 7948489980SSeiya Wang capacity-dmips-mhz = <530>; 8048489980SSeiya Wang }; 8148489980SSeiya Wang 8248489980SSeiya Wang cpu4: cpu@400 { 8348489980SSeiya Wang device_type = "cpu"; 8448489980SSeiya Wang compatible = "arm,cortex-a76"; 8548489980SSeiya Wang reg = <0x400>; 8648489980SSeiya Wang enable-method = "psci"; 8748489980SSeiya Wang clock-frequency = <2171000000>; 889260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 8948489980SSeiya Wang next-level-cache = <&l2_1>; 9048489980SSeiya Wang capacity-dmips-mhz = <1024>; 9148489980SSeiya Wang }; 9248489980SSeiya Wang 9348489980SSeiya Wang cpu5: cpu@500 { 9448489980SSeiya Wang device_type = "cpu"; 9548489980SSeiya Wang compatible = "arm,cortex-a76"; 9648489980SSeiya Wang reg = <0x500>; 9748489980SSeiya Wang enable-method = "psci"; 9848489980SSeiya Wang clock-frequency = <2171000000>; 999260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 10048489980SSeiya Wang next-level-cache = <&l2_1>; 10148489980SSeiya Wang capacity-dmips-mhz = <1024>; 10248489980SSeiya Wang }; 10348489980SSeiya Wang 10448489980SSeiya Wang cpu6: cpu@600 { 10548489980SSeiya Wang device_type = "cpu"; 10648489980SSeiya Wang compatible = "arm,cortex-a76"; 10748489980SSeiya Wang reg = <0x600>; 10848489980SSeiya Wang enable-method = "psci"; 10948489980SSeiya Wang clock-frequency = <2171000000>; 1109260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 11148489980SSeiya Wang next-level-cache = <&l2_1>; 11248489980SSeiya Wang capacity-dmips-mhz = <1024>; 11348489980SSeiya Wang }; 11448489980SSeiya Wang 11548489980SSeiya Wang cpu7: cpu@700 { 11648489980SSeiya Wang device_type = "cpu"; 11748489980SSeiya Wang compatible = "arm,cortex-a76"; 11848489980SSeiya Wang reg = <0x700>; 11948489980SSeiya Wang enable-method = "psci"; 12048489980SSeiya Wang clock-frequency = <2171000000>; 1219260918dSJames Liao cpu-idle-states = <&cpuoff_b &clusteroff_b>; 12248489980SSeiya Wang next-level-cache = <&l2_1>; 12348489980SSeiya Wang capacity-dmips-mhz = <1024>; 12448489980SSeiya Wang }; 12548489980SSeiya Wang 12648489980SSeiya Wang cpu-map { 12748489980SSeiya Wang cluster0 { 12848489980SSeiya Wang core0 { 12948489980SSeiya Wang cpu = <&cpu0>; 13048489980SSeiya Wang }; 13148489980SSeiya Wang core1 { 13248489980SSeiya Wang cpu = <&cpu1>; 13348489980SSeiya Wang }; 13448489980SSeiya Wang core2 { 13548489980SSeiya Wang cpu = <&cpu2>; 13648489980SSeiya Wang }; 13748489980SSeiya Wang core3 { 13848489980SSeiya Wang cpu = <&cpu3>; 13948489980SSeiya Wang }; 14048489980SSeiya Wang }; 14148489980SSeiya Wang 14248489980SSeiya Wang cluster1 { 14348489980SSeiya Wang core0 { 14448489980SSeiya Wang cpu = <&cpu4>; 14548489980SSeiya Wang }; 14648489980SSeiya Wang core1 { 14748489980SSeiya Wang cpu = <&cpu5>; 14848489980SSeiya Wang }; 14948489980SSeiya Wang core2 { 15048489980SSeiya Wang cpu = <&cpu6>; 15148489980SSeiya Wang }; 15248489980SSeiya Wang core3 { 15348489980SSeiya Wang cpu = <&cpu7>; 15448489980SSeiya Wang }; 15548489980SSeiya Wang }; 15648489980SSeiya Wang }; 15748489980SSeiya Wang 15848489980SSeiya Wang l2_0: l2-cache0 { 15948489980SSeiya Wang compatible = "cache"; 16048489980SSeiya Wang next-level-cache = <&l3_0>; 16148489980SSeiya Wang }; 16248489980SSeiya Wang 16348489980SSeiya Wang l2_1: l2-cache1 { 16448489980SSeiya Wang compatible = "cache"; 16548489980SSeiya Wang next-level-cache = <&l3_0>; 16648489980SSeiya Wang }; 16748489980SSeiya Wang 16848489980SSeiya Wang l3_0: l3-cache { 16948489980SSeiya Wang compatible = "cache"; 17048489980SSeiya Wang }; 1719260918dSJames Liao 1729260918dSJames Liao idle-states { 1739260918dSJames Liao entry-method = "arm,psci"; 1749260918dSJames Liao cpuoff_l: cpuoff_l { 1759260918dSJames Liao compatible = "arm,idle-state"; 1769260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1779260918dSJames Liao local-timer-stop; 1789260918dSJames Liao entry-latency-us = <55>; 1799260918dSJames Liao exit-latency-us = <140>; 1809260918dSJames Liao min-residency-us = <780>; 1819260918dSJames Liao }; 1829260918dSJames Liao cpuoff_b: cpuoff_b { 1839260918dSJames Liao compatible = "arm,idle-state"; 1849260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 1859260918dSJames Liao local-timer-stop; 1869260918dSJames Liao entry-latency-us = <35>; 1879260918dSJames Liao exit-latency-us = <145>; 1889260918dSJames Liao min-residency-us = <720>; 1899260918dSJames Liao }; 1909260918dSJames Liao clusteroff_l: clusteroff_l { 1919260918dSJames Liao compatible = "arm,idle-state"; 1929260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 1939260918dSJames Liao local-timer-stop; 1949260918dSJames Liao entry-latency-us = <60>; 1959260918dSJames Liao exit-latency-us = <155>; 1969260918dSJames Liao min-residency-us = <860>; 1979260918dSJames Liao }; 1989260918dSJames Liao clusteroff_b: clusteroff_b { 1999260918dSJames Liao compatible = "arm,idle-state"; 2009260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2019260918dSJames Liao local-timer-stop; 2029260918dSJames Liao entry-latency-us = <40>; 2039260918dSJames Liao exit-latency-us = <155>; 2049260918dSJames Liao min-residency-us = <780>; 2059260918dSJames Liao }; 2069260918dSJames Liao }; 20748489980SSeiya Wang }; 20848489980SSeiya Wang 20948489980SSeiya Wang pmu-a55 { 21048489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 21148489980SSeiya Wang interrupt-parent = <&gic>; 21248489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 21348489980SSeiya Wang }; 21448489980SSeiya Wang 21548489980SSeiya Wang pmu-a76 { 21648489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 21748489980SSeiya Wang interrupt-parent = <&gic>; 21848489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 21948489980SSeiya Wang }; 22048489980SSeiya Wang 22148489980SSeiya Wang psci { 22248489980SSeiya Wang compatible = "arm,psci-1.0"; 22348489980SSeiya Wang method = "smc"; 22448489980SSeiya Wang }; 22548489980SSeiya Wang 22648489980SSeiya Wang timer: timer { 22748489980SSeiya Wang compatible = "arm,armv8-timer"; 22848489980SSeiya Wang interrupt-parent = <&gic>; 22948489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 23048489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 23148489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 23248489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 23348489980SSeiya Wang clock-frequency = <13000000>; 23448489980SSeiya Wang }; 23548489980SSeiya Wang 23648489980SSeiya Wang soc { 23748489980SSeiya Wang #address-cells = <2>; 23848489980SSeiya Wang #size-cells = <2>; 23948489980SSeiya Wang compatible = "simple-bus"; 24048489980SSeiya Wang ranges; 24148489980SSeiya Wang 24248489980SSeiya Wang gic: interrupt-controller@c000000 { 24348489980SSeiya Wang compatible = "arm,gic-v3"; 24448489980SSeiya Wang #interrupt-cells = <4>; 24548489980SSeiya Wang #redistributor-regions = <1>; 24648489980SSeiya Wang interrupt-parent = <&gic>; 24748489980SSeiya Wang interrupt-controller; 24848489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 24948489980SSeiya Wang <0 0x0c040000 0 0x200000>; 25048489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 25148489980SSeiya Wang 25248489980SSeiya Wang ppi-partitions { 25348489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 25448489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 25548489980SSeiya Wang }; 25648489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 25748489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 25848489980SSeiya Wang }; 25948489980SSeiya Wang }; 26048489980SSeiya Wang }; 26148489980SSeiya Wang 2625d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 2635d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 2645d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 2655d2b897bSChun-Jie Chen #clock-cells = <1>; 2665d2b897bSChun-Jie Chen }; 2675d2b897bSChun-Jie Chen 2685d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 2695d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 2705d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 2715d2b897bSChun-Jie Chen #clock-cells = <1>; 2725d2b897bSChun-Jie Chen }; 2735d2b897bSChun-Jie Chen 2745d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 2755d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 2765d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 2775d2b897bSChun-Jie Chen #clock-cells = <1>; 2785d2b897bSChun-Jie Chen }; 2795d2b897bSChun-Jie Chen 28048489980SSeiya Wang pio: pinctrl@10005000 { 28148489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 28248489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 28348489980SSeiya Wang <0 0x11c20000 0 0x1000>, 28448489980SSeiya Wang <0 0x11d10000 0 0x1000>, 28548489980SSeiya Wang <0 0x11d30000 0 0x1000>, 28648489980SSeiya Wang <0 0x11d40000 0 0x1000>, 28748489980SSeiya Wang <0 0x11e20000 0 0x1000>, 28848489980SSeiya Wang <0 0x11e70000 0 0x1000>, 28948489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 29048489980SSeiya Wang <0 0x11f20000 0 0x1000>, 29148489980SSeiya Wang <0 0x11f30000 0 0x1000>, 29248489980SSeiya Wang <0 0x1000b000 0 0x1000>; 29348489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 29448489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 29548489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 29648489980SSeiya Wang "iocfg_tl", "eint"; 29748489980SSeiya Wang gpio-controller; 29848489980SSeiya Wang #gpio-cells = <2>; 29948489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 30048489980SSeiya Wang interrupt-controller; 30148489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 30248489980SSeiya Wang #interrupt-cells = <2>; 30348489980SSeiya Wang }; 30448489980SSeiya Wang 305994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 306994a71a3SChun-Jie Chen compatible = "syscon", "simple-mfd"; 307994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 308994a71a3SChun-Jie Chen #power-domain-cells = <1>; 309994a71a3SChun-Jie Chen 310994a71a3SChun-Jie Chen /* System Power Manager */ 311994a71a3SChun-Jie Chen spm: power-controller { 312994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 313994a71a3SChun-Jie Chen #address-cells = <1>; 314994a71a3SChun-Jie Chen #size-cells = <0>; 315994a71a3SChun-Jie Chen #power-domain-cells = <1>; 316994a71a3SChun-Jie Chen 317994a71a3SChun-Jie Chen /* power domain of the SoC */ 318994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 319994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 320994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 321994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 322994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 323994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 324994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 325994a71a3SChun-Jie Chen #power-domain-cells = <0>; 326994a71a3SChun-Jie Chen }; 327994a71a3SChun-Jie Chen 328994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 329994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 330994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 331994a71a3SChun-Jie Chen clock-names = "conn"; 332994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 333994a71a3SChun-Jie Chen #power-domain-cells = <0>; 334994a71a3SChun-Jie Chen }; 335994a71a3SChun-Jie Chen 336994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG0 { 337994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 338994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 339994a71a3SChun-Jie Chen clock-names = "mfg"; 340994a71a3SChun-Jie Chen #address-cells = <1>; 341994a71a3SChun-Jie Chen #size-cells = <0>; 342994a71a3SChun-Jie Chen #power-domain-cells = <1>; 343994a71a3SChun-Jie Chen 344994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG1 { 345994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 346994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 347994a71a3SChun-Jie Chen #address-cells = <1>; 348994a71a3SChun-Jie Chen #size-cells = <0>; 349994a71a3SChun-Jie Chen #power-domain-cells = <1>; 350994a71a3SChun-Jie Chen 351994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 352994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 353994a71a3SChun-Jie Chen #power-domain-cells = <0>; 354994a71a3SChun-Jie Chen }; 355994a71a3SChun-Jie Chen 356994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 357994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 358994a71a3SChun-Jie Chen #power-domain-cells = <0>; 359994a71a3SChun-Jie Chen }; 360994a71a3SChun-Jie Chen 361994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 362994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 363994a71a3SChun-Jie Chen #power-domain-cells = <0>; 364994a71a3SChun-Jie Chen }; 365994a71a3SChun-Jie Chen 366994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 367994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 368994a71a3SChun-Jie Chen #power-domain-cells = <0>; 369994a71a3SChun-Jie Chen }; 370994a71a3SChun-Jie Chen 371994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 372994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 373994a71a3SChun-Jie Chen #power-domain-cells = <0>; 374994a71a3SChun-Jie Chen }; 375994a71a3SChun-Jie Chen }; 376994a71a3SChun-Jie Chen }; 377994a71a3SChun-Jie Chen 378994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 379994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 380994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 381994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 382994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 383994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 384994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 385994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 386994a71a3SChun-Jie Chen "disp-3"; 387994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 388994a71a3SChun-Jie Chen #address-cells = <1>; 389994a71a3SChun-Jie Chen #size-cells = <0>; 390994a71a3SChun-Jie Chen #power-domain-cells = <1>; 391994a71a3SChun-Jie Chen 392994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 393994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 394994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 395994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 396994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 397994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 398994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 399994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 400994a71a3SChun-Jie Chen "ipe-3"; 401994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 402994a71a3SChun-Jie Chen #power-domain-cells = <0>; 403994a71a3SChun-Jie Chen }; 404994a71a3SChun-Jie Chen 405994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 406994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 407994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 408994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 409994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 410994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 411994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 412994a71a3SChun-Jie Chen #power-domain-cells = <0>; 413994a71a3SChun-Jie Chen }; 414994a71a3SChun-Jie Chen 415994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 416994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 417994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 418994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 419994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 420994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 421994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 422994a71a3SChun-Jie Chen #power-domain-cells = <0>; 423994a71a3SChun-Jie Chen }; 424994a71a3SChun-Jie Chen 425994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 426994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 427994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 428994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 429994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 430994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 431994a71a3SChun-Jie Chen #power-domain-cells = <0>; 432994a71a3SChun-Jie Chen }; 433994a71a3SChun-Jie Chen 434994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 435994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 436994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 437994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 438994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 439994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 440994a71a3SChun-Jie Chen #power-domain-cells = <0>; 441994a71a3SChun-Jie Chen }; 442994a71a3SChun-Jie Chen 443994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 444994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 445994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 446994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 447994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 448994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 449994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 450994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 451994a71a3SChun-Jie Chen #address-cells = <1>; 452994a71a3SChun-Jie Chen #size-cells = <0>; 453994a71a3SChun-Jie Chen #power-domain-cells = <1>; 454994a71a3SChun-Jie Chen 455994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 456994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 457994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 458994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 459994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 460994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 461994a71a3SChun-Jie Chen "vdec2-2"; 462994a71a3SChun-Jie Chen #power-domain-cells = <0>; 463994a71a3SChun-Jie Chen }; 464994a71a3SChun-Jie Chen }; 465994a71a3SChun-Jie Chen 466994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 467994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 468994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 469994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 470994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 471994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 472994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 473994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 474994a71a3SChun-Jie Chen "cam-3"; 475994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 476994a71a3SChun-Jie Chen #address-cells = <1>; 477994a71a3SChun-Jie Chen #size-cells = <0>; 478994a71a3SChun-Jie Chen #power-domain-cells = <1>; 479994a71a3SChun-Jie Chen 480994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 481994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 482994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 483994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 484994a71a3SChun-Jie Chen #power-domain-cells = <0>; 485994a71a3SChun-Jie Chen }; 486994a71a3SChun-Jie Chen 487994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 488994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 489994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 490994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 491994a71a3SChun-Jie Chen #power-domain-cells = <0>; 492994a71a3SChun-Jie Chen }; 493994a71a3SChun-Jie Chen 494994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 495994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 496994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 497994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 498994a71a3SChun-Jie Chen #power-domain-cells = <0>; 499994a71a3SChun-Jie Chen }; 500994a71a3SChun-Jie Chen }; 501994a71a3SChun-Jie Chen }; 502994a71a3SChun-Jie Chen }; 503994a71a3SChun-Jie Chen }; 504994a71a3SChun-Jie Chen 505d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 506d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 507d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 508d1986fbdSAllen-KH Cheng #reset-cells = <1>; 509d1986fbdSAllen-KH Cheng }; 510d1986fbdSAllen-KH Cheng 5115d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 5125d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 5135d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 5145d2b897bSChun-Jie Chen #clock-cells = <1>; 5155d2b897bSChun-Jie Chen }; 5165d2b897bSChun-Jie Chen 51748489980SSeiya Wang systimer: timer@10017000 { 51848489980SSeiya Wang compatible = "mediatek,mt8192-timer", 51948489980SSeiya Wang "mediatek,mt6765-timer"; 52048489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 52148489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 522dde3c175SAllen-KH Cheng clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 52348489980SSeiya Wang clock-names = "clk13m"; 52448489980SSeiya Wang }; 52548489980SSeiya Wang 526*261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 527*261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 528*261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 529*261691b4SAllen-KH Cheng reg-names = "pwrap"; 530*261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 531*261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 532*261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 533*261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 534*261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 535*261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 536*261691b4SAllen-KH Cheng }; 537*261691b4SAllen-KH Cheng 5385d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 5395d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 5405d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 5415d2b897bSChun-Jie Chen #clock-cells = <1>; 5425d2b897bSChun-Jie Chen }; 5435d2b897bSChun-Jie Chen 54448489980SSeiya Wang uart0: serial@11002000 { 54548489980SSeiya Wang compatible = "mediatek,mt8192-uart", 54648489980SSeiya Wang "mediatek,mt6577-uart"; 54748489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 54848489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 54973ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 55048489980SSeiya Wang clock-names = "baud", "bus"; 55148489980SSeiya Wang status = "disabled"; 55248489980SSeiya Wang }; 55348489980SSeiya Wang 55448489980SSeiya Wang uart1: serial@11003000 { 55548489980SSeiya Wang compatible = "mediatek,mt8192-uart", 55648489980SSeiya Wang "mediatek,mt6577-uart"; 55748489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 55848489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 55973ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 56048489980SSeiya Wang clock-names = "baud", "bus"; 56148489980SSeiya Wang status = "disabled"; 56248489980SSeiya Wang }; 56348489980SSeiya Wang 5645d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 5655d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 5665d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 5675d2b897bSChun-Jie Chen #clock-cells = <1>; 5685d2b897bSChun-Jie Chen }; 5695d2b897bSChun-Jie Chen 57048489980SSeiya Wang spi0: spi@1100a000 { 57148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 57248489980SSeiya Wang "mediatek,mt6765-spi"; 57348489980SSeiya Wang #address-cells = <1>; 57448489980SSeiya Wang #size-cells = <0>; 57548489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 57648489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 5777f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5787f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5797f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 58048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 58148489980SSeiya Wang status = "disabled"; 58248489980SSeiya Wang }; 58348489980SSeiya Wang 58448489980SSeiya Wang spi1: spi@11010000 { 58548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 58648489980SSeiya Wang "mediatek,mt6765-spi"; 58748489980SSeiya Wang #address-cells = <1>; 58848489980SSeiya Wang #size-cells = <0>; 58948489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 59048489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 5917f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 5927f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 5937f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 59448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 59548489980SSeiya Wang status = "disabled"; 59648489980SSeiya Wang }; 59748489980SSeiya Wang 59848489980SSeiya Wang spi2: spi@11012000 { 59948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 60048489980SSeiya Wang "mediatek,mt6765-spi"; 60148489980SSeiya Wang #address-cells = <1>; 60248489980SSeiya Wang #size-cells = <0>; 60348489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 60448489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 6057f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6067f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6077f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 60848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 60948489980SSeiya Wang status = "disabled"; 61048489980SSeiya Wang }; 61148489980SSeiya Wang 61248489980SSeiya Wang spi3: spi@11013000 { 61348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 61448489980SSeiya Wang "mediatek,mt6765-spi"; 61548489980SSeiya Wang #address-cells = <1>; 61648489980SSeiya Wang #size-cells = <0>; 61748489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 61848489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 6197f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6207f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6217f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 62248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 62348489980SSeiya Wang status = "disabled"; 62448489980SSeiya Wang }; 62548489980SSeiya Wang 62648489980SSeiya Wang spi4: spi@11018000 { 62748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 62848489980SSeiya Wang "mediatek,mt6765-spi"; 62948489980SSeiya Wang #address-cells = <1>; 63048489980SSeiya Wang #size-cells = <0>; 63148489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 63248489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 6337f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6347f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6357f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 63648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 63748489980SSeiya Wang status = "disabled"; 63848489980SSeiya Wang }; 63948489980SSeiya Wang 64048489980SSeiya Wang spi5: spi@11019000 { 64148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 64248489980SSeiya Wang "mediatek,mt6765-spi"; 64348489980SSeiya Wang #address-cells = <1>; 64448489980SSeiya Wang #size-cells = <0>; 64548489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 64648489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 6477f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6487f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6497f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 65048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 65148489980SSeiya Wang status = "disabled"; 65248489980SSeiya Wang }; 65348489980SSeiya Wang 65448489980SSeiya Wang spi6: spi@1101d000 { 65548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 65648489980SSeiya Wang "mediatek,mt6765-spi"; 65748489980SSeiya Wang #address-cells = <1>; 65848489980SSeiya Wang #size-cells = <0>; 65948489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 66048489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 6617f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6627f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6637f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 66448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 66548489980SSeiya Wang status = "disabled"; 66648489980SSeiya Wang }; 66748489980SSeiya Wang 66848489980SSeiya Wang spi7: spi@1101e000 { 66948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 67048489980SSeiya Wang "mediatek,mt6765-spi"; 67148489980SSeiya Wang #address-cells = <1>; 67248489980SSeiya Wang #size-cells = <0>; 67348489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 67448489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 6757f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 6767f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 6777f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 67848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 67948489980SSeiya Wang status = "disabled"; 68048489980SSeiya Wang }; 68148489980SSeiya Wang 682d0a197a0Sbayi cheng nor_flash: spi@11234000 { 683d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 684d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 685d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 686aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 687aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 688aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 689d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 690aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 691aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 692d0a197a0Sbayi cheng #address-cells = <1>; 693d0a197a0Sbayi cheng #size-cells = <0>; 694d0a197a0Sbayi cheng status = "disable"; 695d0a197a0Sbayi cheng }; 696d0a197a0Sbayi cheng 6975d2b897bSChun-Jie Chen audsys: clock-controller@11210000 { 6985d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-audsys", "syscon"; 6995d2b897bSChun-Jie Chen reg = <0 0x11210000 0 0x1000>; 7005d2b897bSChun-Jie Chen #clock-cells = <1>; 7015d2b897bSChun-Jie Chen }; 7025d2b897bSChun-Jie Chen 7037f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 70448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 70548489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 70648489980SSeiya Wang <0 0x10217300 0 0x80>; 70748489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 70822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 70922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 71048489980SSeiya Wang clock-names = "main", "dma"; 71148489980SSeiya Wang clock-div = <1>; 71248489980SSeiya Wang #address-cells = <1>; 71348489980SSeiya Wang #size-cells = <0>; 71448489980SSeiya Wang status = "disabled"; 71548489980SSeiya Wang }; 71648489980SSeiya Wang 7175d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 7185d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 7195d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 7205d2b897bSChun-Jie Chen #clock-cells = <1>; 7215d2b897bSChun-Jie Chen }; 7225d2b897bSChun-Jie Chen 7237f1a9f47SFabien Parent i2c7: i2c@11d00000 { 72448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 72548489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 72648489980SSeiya Wang <0 0x10217600 0 0x180>; 72748489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 72822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 72922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 73048489980SSeiya Wang clock-names = "main", "dma"; 73148489980SSeiya Wang clock-div = <1>; 73248489980SSeiya Wang #address-cells = <1>; 73348489980SSeiya Wang #size-cells = <0>; 73448489980SSeiya Wang status = "disabled"; 73548489980SSeiya Wang }; 73648489980SSeiya Wang 7377f1a9f47SFabien Parent i2c8: i2c@11d01000 { 73848489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 73948489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 74048489980SSeiya Wang <0 0x10217780 0 0x180>; 74148489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 74222623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 74322623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 74448489980SSeiya Wang clock-names = "main", "dma"; 74548489980SSeiya Wang clock-div = <1>; 74648489980SSeiya Wang #address-cells = <1>; 74748489980SSeiya Wang #size-cells = <0>; 74848489980SSeiya Wang status = "disabled"; 74948489980SSeiya Wang }; 75048489980SSeiya Wang 7517f1a9f47SFabien Parent i2c9: i2c@11d02000 { 75248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 75348489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 75448489980SSeiya Wang <0 0x10217900 0 0x180>; 75548489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 75622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 75722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 75848489980SSeiya Wang clock-names = "main", "dma"; 75948489980SSeiya Wang clock-div = <1>; 76048489980SSeiya Wang #address-cells = <1>; 76148489980SSeiya Wang #size-cells = <0>; 76248489980SSeiya Wang status = "disabled"; 76348489980SSeiya Wang }; 76448489980SSeiya Wang 7655d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 7665d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 7675d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 7685d2b897bSChun-Jie Chen #clock-cells = <1>; 7695d2b897bSChun-Jie Chen }; 7705d2b897bSChun-Jie Chen 7717f1a9f47SFabien Parent i2c1: i2c@11d20000 { 77248489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 77348489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 77448489980SSeiya Wang <0 0x10217100 0 0x80>; 77548489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 77622623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 77722623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 77848489980SSeiya Wang clock-names = "main", "dma"; 77948489980SSeiya Wang clock-div = <1>; 78048489980SSeiya Wang #address-cells = <1>; 78148489980SSeiya Wang #size-cells = <0>; 78248489980SSeiya Wang status = "disabled"; 78348489980SSeiya Wang }; 78448489980SSeiya Wang 7857f1a9f47SFabien Parent i2c2: i2c@11d21000 { 78648489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 78748489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 78848489980SSeiya Wang <0 0x10217180 0 0x180>; 78948489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 79022623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 79122623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 79248489980SSeiya Wang clock-names = "main", "dma"; 79348489980SSeiya Wang clock-div = <1>; 79448489980SSeiya Wang #address-cells = <1>; 79548489980SSeiya Wang #size-cells = <0>; 79648489980SSeiya Wang status = "disabled"; 79748489980SSeiya Wang }; 79848489980SSeiya Wang 7997f1a9f47SFabien Parent i2c4: i2c@11d22000 { 80048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 80148489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 80248489980SSeiya Wang <0 0x10217380 0 0x180>; 80348489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 80422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 80522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 80648489980SSeiya Wang clock-names = "main", "dma"; 80748489980SSeiya Wang clock-div = <1>; 80848489980SSeiya Wang #address-cells = <1>; 80948489980SSeiya Wang #size-cells = <0>; 81048489980SSeiya Wang status = "disabled"; 81148489980SSeiya Wang }; 81248489980SSeiya Wang 8135d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 8145d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 8155d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 8165d2b897bSChun-Jie Chen #clock-cells = <1>; 8175d2b897bSChun-Jie Chen }; 8185d2b897bSChun-Jie Chen 8197f1a9f47SFabien Parent i2c5: i2c@11e00000 { 82048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 82148489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 82248489980SSeiya Wang <0 0x10217500 0 0x80>; 82348489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 82422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 82522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 82648489980SSeiya Wang clock-names = "main", "dma"; 82748489980SSeiya Wang clock-div = <1>; 82848489980SSeiya Wang #address-cells = <1>; 82948489980SSeiya Wang #size-cells = <0>; 83048489980SSeiya Wang status = "disabled"; 83148489980SSeiya Wang }; 83248489980SSeiya Wang 8335d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 8345d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 8355d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 8365d2b897bSChun-Jie Chen #clock-cells = <1>; 8375d2b897bSChun-Jie Chen }; 8385d2b897bSChun-Jie Chen 8397f1a9f47SFabien Parent i2c0: i2c@11f00000 { 84048489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 84148489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 84248489980SSeiya Wang <0 0x10217080 0 0x80>; 84348489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 84422623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 84522623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 84648489980SSeiya Wang clock-names = "main", "dma"; 84748489980SSeiya Wang clock-div = <1>; 84848489980SSeiya Wang #address-cells = <1>; 84948489980SSeiya Wang #size-cells = <0>; 85048489980SSeiya Wang status = "disabled"; 85148489980SSeiya Wang }; 85248489980SSeiya Wang 8537f1a9f47SFabien Parent i2c6: i2c@11f01000 { 85448489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 85548489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 85648489980SSeiya Wang <0 0x10217580 0 0x80>; 85748489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 85822623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 85922623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 86048489980SSeiya Wang clock-names = "main", "dma"; 86148489980SSeiya Wang clock-div = <1>; 86248489980SSeiya Wang #address-cells = <1>; 86348489980SSeiya Wang #size-cells = <0>; 86448489980SSeiya Wang status = "disabled"; 86548489980SSeiya Wang }; 8665d2b897bSChun-Jie Chen 8675d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 8685d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 8695d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 8705d2b897bSChun-Jie Chen #clock-cells = <1>; 8715d2b897bSChun-Jie Chen }; 8725d2b897bSChun-Jie Chen 8735d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 8745d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 8755d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 8765d2b897bSChun-Jie Chen #clock-cells = <1>; 8775d2b897bSChun-Jie Chen }; 8785d2b897bSChun-Jie Chen 8795d2b897bSChun-Jie Chen msdc: clock-controller@11f60000 { 8805d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc"; 8815d2b897bSChun-Jie Chen reg = <0 0x11f60000 0 0x1000>; 8825d2b897bSChun-Jie Chen #clock-cells = <1>; 8835d2b897bSChun-Jie Chen }; 8845d2b897bSChun-Jie Chen 8855d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 8865d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 8875d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 8885d2b897bSChun-Jie Chen #clock-cells = <1>; 8895d2b897bSChun-Jie Chen }; 8905d2b897bSChun-Jie Chen 8915d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 8925d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 8935d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 8945d2b897bSChun-Jie Chen #clock-cells = <1>; 8955d2b897bSChun-Jie Chen }; 8965d2b897bSChun-Jie Chen 8975d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 8985d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 8995d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 9005d2b897bSChun-Jie Chen #clock-cells = <1>; 9015d2b897bSChun-Jie Chen }; 9025d2b897bSChun-Jie Chen 9035d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 9045d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 9055d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 9065d2b897bSChun-Jie Chen #clock-cells = <1>; 9075d2b897bSChun-Jie Chen }; 9085d2b897bSChun-Jie Chen 9095d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 9105d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 9115d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 9125d2b897bSChun-Jie Chen #clock-cells = <1>; 9135d2b897bSChun-Jie Chen }; 9145d2b897bSChun-Jie Chen 9155d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 9165d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 9175d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 9185d2b897bSChun-Jie Chen #clock-cells = <1>; 9195d2b897bSChun-Jie Chen }; 9205d2b897bSChun-Jie Chen 9215d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 9225d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 9235d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 9245d2b897bSChun-Jie Chen #clock-cells = <1>; 9255d2b897bSChun-Jie Chen }; 9265d2b897bSChun-Jie Chen 9275d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 9285d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 9295d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 9305d2b897bSChun-Jie Chen #clock-cells = <1>; 9315d2b897bSChun-Jie Chen }; 9325d2b897bSChun-Jie Chen 9335d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 9345d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 9355d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 9365d2b897bSChun-Jie Chen #clock-cells = <1>; 9375d2b897bSChun-Jie Chen }; 9385d2b897bSChun-Jie Chen 9395d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 9405d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 9415d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 9425d2b897bSChun-Jie Chen #clock-cells = <1>; 9435d2b897bSChun-Jie Chen }; 9445d2b897bSChun-Jie Chen 9455d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 9465d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 9475d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 9485d2b897bSChun-Jie Chen #clock-cells = <1>; 9495d2b897bSChun-Jie Chen }; 9505d2b897bSChun-Jie Chen 9515d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 9525d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 9535d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 9545d2b897bSChun-Jie Chen #clock-cells = <1>; 9555d2b897bSChun-Jie Chen }; 9565d2b897bSChun-Jie Chen 9575d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 9585d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 9595d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 9605d2b897bSChun-Jie Chen #clock-cells = <1>; 9615d2b897bSChun-Jie Chen }; 96248489980SSeiya Wang }; 96348489980SSeiya Wang}; 964